1 | /* |
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2 | * SDRAM Mode Register |
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3 | * Based on Fujitsu MB81F643242B data sheet. |
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4 | * |
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5 | * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia |
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6 | * Author: Victor V. Vengerov <vvv@oktet.ru> |
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7 | * |
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8 | * The license and distribution terms for this file may be |
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9 | * found in the file LICENSE in this distribution or at |
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10 | * http://www.OARcorp.com/rtems/license.html. |
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11 | * |
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12 | * @(#) $Id$ |
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13 | */ |
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14 | |
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15 | #ifndef __SDRAM_H__ |
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16 | #define __SDRAM_H__ |
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17 | |
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18 | /* SDRAM Mode Register */ |
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19 | #define SDRAM_MODE_BL 0x0007 /* Burst Length: */ |
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20 | #define SDRAM_MODE_BL_1 0x0000 /* 0 */ |
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21 | #define SDRAM_MODE_BL_2 0x0001 /* 2 */ |
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22 | #define SDRAM_MODE_BL_4 0x0002 /* 4 */ |
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23 | #define SDRAM_MODE_BL_8 0x0003 /* 8 */ |
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24 | #define SDRAM_MODE_BL_16 0x0004 /* 16 */ |
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25 | #define SDRAM_MODE_BL_32 0x0005 /* 32 */ |
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26 | #define SDRAM_MODE_BL_64 0x0006 /* 64 */ |
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27 | #define SDRAM_MODE_BL_FULL 0x0007 /* Full column */ |
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28 | |
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29 | #define SDRAM_MODE_BT 0x0008 /* Burst Type: */ |
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30 | #define SDRAM_MODE_BT_SEQ 0x0000 /* Sequential */ |
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31 | #define SDRAM_MODE_BT_ILV 0x0008 /* Interleave */ |
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32 | |
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33 | #define SDRAM_MODE_CL 0x0070 /* CAS Latency: */ |
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34 | #define SDRAM_MODE_CL_1 0x0010 /* 1 */ |
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35 | #define SDRAM_MODE_CL_2 0x0020 /* 2 */ |
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36 | #define SDRAM_MODE_CL_3 0x0030 /* 3 */ |
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37 | |
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38 | #define SDRAM_MODE_OPC 0x0200 /* Opcode: */ |
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39 | #define SDRAM_MODE_OPC_BRBW 0x0000 /* Burst read & Burst write */ |
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40 | #define SDRAM_MODE_OPC_BRSW 0x0200 /* Burst read & Single write */ |
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41 | |
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42 | #endif |
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