[4a238002] | 1 | /* |
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| 2 | * This is an adapted linker script from egcs-1.0.1 |
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| 3 | * |
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| 4 | * Memory layout for an SH7045F with main memory in area 2 |
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| 5 | * This memory layout it very similar to that used for Hitachi's |
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| 6 | * EVB with CMON in FLASH |
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| 7 | * |
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| 8 | * NOTE: The ram start address may vary, all other start addresses are fixed |
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| 9 | * Not suiteable for gdb's simulator |
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| 10 | * |
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| 11 | * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and |
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| 12 | * Bernd Becker (becker@faw.uni-ulm.de) |
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| 13 | * |
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| 14 | * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany |
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| 15 | * |
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| 16 | * This program is distributed in the hope that it will be useful, |
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| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
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| 19 | * |
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| 20 | * |
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| 21 | * COPYRIGHT (c) 1998. |
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| 22 | * On-Line Applications Research Corporation (OAR). |
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| 23 | * |
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| 24 | * The license and distribution terms for this file may be |
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| 25 | * found in the file LICENSE in this distribution or at |
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| 26 | * http://www.OARcorp.com/rtems/license.html. |
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| 27 | * |
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| 28 | * Modified to reflect SH7045F processor and EVB: |
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| 29 | * John M. Mills (jmills@tga.com) |
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| 30 | * TGA Technologies, Inc. |
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| 31 | * 100 Pinnacle Way, Suite 140 |
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| 32 | * Norcross, GA 30071 U.S.A. |
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| 33 | * |
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| 34 | * This modified file may be copied and distributed in accordance |
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| 35 | * the above-referenced license. It is provided for critique and |
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| 36 | * developmental purposes without any warranty nor representation |
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| 37 | * by the authors or by TGA Technologies. |
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| 38 | * |
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| 39 | * $Id$ |
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| 40 | */ |
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| 41 | |
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| 42 | OUTPUT_FORMAT("coff-sh") |
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| 43 | OUTPUT_ARCH(sh) |
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| 44 | ENTRY(_start) |
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| 45 | |
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| 46 | /* These asignments represent actual SH7045F EVB architecture */ |
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| 47 | |
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| 48 | MEMORY |
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| 49 | { |
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| 50 | rom : o = 0x00000000, l = 0x00040000 |
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| 51 | ram : o = 0x00400000, l = 0x00080000 |
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| 52 | onchip_peri : o = 0xFFFF8000, l = 0x00000800 |
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| 53 | onchip_ram : o = 0xFFFFF000, l = 0x00001000 |
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| 54 | } |
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| 55 | |
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| 56 | |
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| 57 | /* Sections are defined for RAM loading and monitor debugging */ |
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| 58 | SECTIONS |
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| 59 | { |
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| 60 | /* boot vector table */ |
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| 61 | .monvects 0x00000000 (NOLOAD): { |
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| 62 | _monvects = . ; |
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| 63 | } > rom |
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| 64 | |
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| 65 | /* monitor play area */ |
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| 66 | .monram 0x00400000 (NOLOAD) : |
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| 67 | { |
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| 68 | _ramstart = .; |
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| 69 | } > ram |
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| 70 | |
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| 71 | /* monitor vector table */ |
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| 72 | .vects 0x00402000 (NOLOAD) : { |
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| 73 | _vectab = . ; |
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| 74 | *(.vects); |
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| 75 | } |
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| 76 | |
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| 77 | /* Read-only sections, merged into text segment: */ |
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| 78 | |
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| 79 | . = 0x00404000 ; |
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| 80 | .interp : { *(.interp) } |
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| 81 | .hash : { *(.hash) } |
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| 82 | .dynsym : { *(.dynsym) } |
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| 83 | .dynstr : { *(.dynstr) } |
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| 84 | .gnu.version : { *(.gnu.version) } |
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| 85 | .gnu.version_d : { *(.gnu.version_d) } |
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| 86 | .gnu.version_r : { *(.gnu.version_r) } |
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| 87 | .rel.text : |
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| 88 | { *(.rel.text) *(.rel.gnu.linkonce.t*) } |
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| 89 | .rela.text : |
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| 90 | { *(.rela.text) *(.rela.gnu.linkonce.t*) } |
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| 91 | .rel.data : |
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| 92 | { *(.rel.data) *(.rel.gnu.linkonce.d*) } |
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| 93 | .rela.data : |
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| 94 | { *(.rela.data) *(.rela.gnu.linkonce.d*) } |
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| 95 | .rel.rodata : |
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| 96 | { *(.rel.rodata) *(.rel.gnu.linkonce.r*) } |
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| 97 | .rela.rodata : |
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| 98 | { *(.rela.rodata) *(.rela.gnu.linkonce.r*) } |
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| 99 | .rel.got : { *(.rel.got) } |
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| 100 | .rela.got : { *(.rela.got) } |
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| 101 | .rel.ctors : { *(.rel.ctors) } |
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| 102 | .rela.ctors : { *(.rela.ctors) } |
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| 103 | .rel.dtors : { *(.rel.dtors) } |
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| 104 | .rela.dtors : { *(.rela.dtors) } |
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| 105 | .rel.init : { *(.rel.init) } |
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| 106 | .rela.init : { *(.rela.init) } |
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| 107 | .rel.fini : { *(.rel.fini) } |
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| 108 | .rela.fini : { *(.rela.fini) } |
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| 109 | .rel.bss : { *(.rel.bss) } |
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| 110 | .rela.bss : { *(.rela.bss) } |
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| 111 | .rel.plt : { *(.rel.plt) } |
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| 112 | .rela.plt : { *(.rela.plt) } |
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| 113 | .init : { *(.init) } =0 |
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| 114 | .plt : { *(.plt) } |
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| 115 | .text . : |
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| 116 | { |
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| 117 | *(.text) |
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| 118 | *(.stub) |
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[646e0008] | 119 | |
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| 120 | /* |
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| 121 | * Special FreeBSD sysctl sections. |
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| 122 | */ |
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| 123 | . = ALIGN (16); |
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| 124 | __start_set_sysctl_set = .; |
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| 125 | *(set_sysctl_*); |
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| 126 | __stop_set_sysctl_set = ABSOLUTE(.); |
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| 127 | *(set_domain_*); |
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| 128 | *(set_pseudo_*); |
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| 129 | |
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[4a238002] | 130 | /* .gnu.warning sections are handled specially by elf32.em. */ |
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| 131 | *(.gnu.warning) |
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| 132 | *(.gnu.linkonce.t*) |
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| 133 | } > ram |
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| 134 | _etext = .; |
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| 135 | PROVIDE (etext = .); |
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| 136 | .fini . : { *(.fini) } =0 |
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| 137 | .rodata . : { *(.rodata) *(.gnu.linkonce.r*) } |
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| 138 | .rodata1 . : { *(.rodata1) } |
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| 139 | /* Adjust the address for the data segment. We want to adjust up to |
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| 140 | the same address within the page on the next page up. */ |
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| 141 | . = ALIGN(128) + (. & (128 - 1)); |
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| 142 | .data . : |
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| 143 | { |
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| 144 | *(.data) |
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| 145 | *(.gnu.linkonce.d*) |
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| 146 | CONSTRUCTORS |
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| 147 | } > ram |
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| 148 | .data1 . : { *(.data1) } |
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| 149 | .ctors . : |
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| 150 | { |
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| 151 | ___ctors = .; |
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| 152 | *(.ctors) |
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| 153 | ___ctors_end = .; |
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| 154 | } |
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| 155 | .dtors . : |
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| 156 | { |
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| 157 | ___dtors = .; |
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| 158 | *(.dtors) |
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| 159 | ___dtors_end = .; |
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| 160 | } |
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| 161 | .got . : { *(.got.plt) *(.got) } |
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| 162 | .dynamic . : { *(.dynamic) } |
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| 163 | /* We want the small data sections together, so single-instruction offsets |
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| 164 | can access them all, and initialized data all before uninitialized, so |
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| 165 | we can shorten the on-disk segment size. */ |
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| 166 | .sdata . : { *(.sdata) } |
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| 167 | _edata = .; |
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| 168 | PROVIDE (edata = .); |
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| 169 | __bss_start = .; |
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| 170 | .sbss . : { *(.sbss) *(.scommon) } |
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| 171 | .bss . : |
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| 172 | { |
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| 173 | *(.dynbss) |
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| 174 | *(.bss) |
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| 175 | *(COMMON) |
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| 176 | } > ram |
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| 177 | _end = . ; |
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| 178 | PROVIDE (end = .); |
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| 179 | |
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| 180 | _HeapStart = . ; |
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| 181 | . = . + 1024 * 20 ; |
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| 182 | PROVIDE( _HeapEnd = . ); |
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| 183 | |
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| 184 | _WorkSpaceStart = . ; |
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| 185 | . = 0x00480000 ; |
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| 186 | PROVIDE(_WorkSpaceEnd = .); |
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| 187 | |
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| 188 | _CPU_Interrupt_stack_low = 0xFFFFF000 ; |
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| 189 | _CPU_Interrupt_stack_high = _CPU_Interrupt_stack_low + 4096 ; |
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| 190 | |
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| 191 | /* Stabs debugging sections. */ |
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| 192 | .stab 0 : { *(.stab) } |
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| 193 | .stabstr 0 : { *(.stabstr) } |
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| 194 | .stab.excl 0 : { *(.stab.excl) } |
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| 195 | .stab.exclstr 0 : { *(.stab.exclstr) } |
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| 196 | .stab.index 0 : { *(.stab.index) } |
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| 197 | .stab.indexstr 0 : { *(.stab.indexstr) } |
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| 198 | .comment 0 : { *(.comment) } |
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| 199 | /* DWARF debug sections. |
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| 200 | Symbols in the DWARF debugging sections are relative to the beginning |
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| 201 | of the section so we begin them at 0. */ |
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| 202 | /* DWARF 1 */ |
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| 203 | .debug 0 : { *(.debug) } |
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| 204 | .line 0 : { *(.line) } |
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| 205 | /* GNU DWARF 1 extensions */ |
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| 206 | .debug_srcinfo 0 : { *(.debug_srcinfo) } |
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| 207 | .debug_sfnames 0 : { *(.debug_sfnames) } |
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| 208 | /* DWARF 1.1 and DWARF 2 */ |
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| 209 | .debug_aranges 0 : { *(.debug_aranges) } |
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| 210 | .debug_pubnames 0 : { *(.debug_pubnames) } |
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| 211 | /* DWARF 2 */ |
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| 212 | .debug_info 0 : { *(.debug_info) } |
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| 213 | .debug_abbrev 0 : { *(.debug_abbrev) } |
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| 214 | .debug_line 0 : { *(.debug_line) } |
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| 215 | .debug_frame 0 : { *(.debug_frame) } |
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| 216 | .debug_str 0 : { *(.debug_str) } |
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| 217 | .debug_loc 0 : { *(.debug_loc) } |
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| 218 | .debug_macinfo 0 : { *(.debug_macinfo) } |
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| 219 | /* SGI/MIPS DWARF 2 extensions */ |
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| 220 | .debug_weaknames 0 : { *(.debug_weaknames) } |
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| 221 | .debug_funcnames 0 : { *(.debug_funcnames) } |
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| 222 | .debug_typenames 0 : { *(.debug_typenames) } |
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| 223 | .debug_varnames 0 : { *(.debug_varnames) } |
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| 224 | |
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| 225 | .stack 0xFFFFFEC0 : { _stack = .; *(.stack) } > onchip_ram |
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| 226 | /* These must appear regardless of . */ |
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| 227 | } |
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