source: rtems/c/src/lib/libbsp/sh/gensh2/startup/ispsh7045.c @ 0706581

5
Last change on this file since 0706581 was 0706581, checked in by Joel Sherrill <joel@…>, on Mar 7, 2018 at 8:31:31 PM

misc sh: Remove includes of rtems/score/types.h

  • Property mode set to 100644
File size: 10.1 KB
Line 
1/*
2 * This file contains the isp frames for the user interrupts.
3 * From these procedures __ISR_Handler is called with the vector number
4 * as argument.
5 *
6 * __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in
7 * some releases of gcc doesn't properly handle #pragma interrupt, if a
8 * file contains both isrs and normal functions.
9 *
10 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
11 *           Bernd Becker (becker@faw.uni-ulm.de)
12 *
13 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
14 *
15 *  This program is distributed in the hope that it will be useful,
16 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
17 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
18 *
19 *
20 *  COPYRIGHT (c) 1998.
21 *  On-Line Applications Research Corporation (OAR).
22 *
23 *  The license and distribution terms for this file may be
24 *  found in the file LICENSE in this distribution or at
25 *  http://www.rtems.org/license/LICENSE.
26 *
27 *      Modified to reflect isp entries for sh7045 processor:
28 *      John M. Mills (jmills@tga.com)
29 *      TGA Technologies, Inc.
30 *      100 Pinnacle Way, Suite 140
31 *      Norcross, GA 30071 U.S.A.
32 *      August, 1999
33 *
34 *      This modified file may be copied and distributed in accordance
35 *      the above-referenced license. It is provided for critique and
36 *      developmental purposes without any warranty nor representation
37 *      by the authors or by TGA Technologies.
38 */
39
40#include <rtems/system.h>
41
42/*
43 * This is a exception vector table
44 *
45 * It has the same structure as the actual vector table (vectab)
46 */
47
48
49/* SH-2 ISR Table */
50#include <rtems/score/ispsh7045.h>
51
52proc_ptr _Hardware_isr_Table[256]={
53_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,         /* PWRon Reset, Maual Reset,...*/
54_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
55_dummy_isp, _dummy_isp, _dummy_isp,
56_nmi_isp, _usb_isp,                               /* irq 11, 12*/
57_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
58_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
59_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
60_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
61_dummy_isp, _dummy_isp, _dummy_isp,
62/* trapa 0 -31 */
63_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
64_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
65_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
66_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
67_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
68_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
69_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
70_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
71_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp,   /* external H/W: irq 64-71 */
72_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp,
73_dma0_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* DMAC: irq 72-87*/
74_dma1_isp, _dummy_isp, _dummy_isp, _dummy_isp,
75_dma2_isp, _dummy_isp, _dummy_isp, _dummy_isp,
76_dma3_isp, _dummy_isp, _dummy_isp, _dummy_isp,
77_mtua0_isp, _mtub0_isp, _mtuc0_isp, _mtud0_isp, /* MTUs: irq 88-127 */
78_mtuv0_isp, _dummy_isp, _dummy_isp, _dummy_isp,
79_mtua1_isp, _mtub1_isp, _dummy_isp, _dummy_isp,
80_mtuv1_isp, _mtuu1_isp, _dummy_isp, _dummy_isp,
81_mtua2_isp, _mtub2_isp, _dummy_isp, _dummy_isp,
82_mtuv2_isp, _mtuu2_isp, _dummy_isp, _dummy_isp,
83_mtua3_isp, _mtub3_isp, _mtuc3_isp, _mtud3_isp,
84_mtuv3_isp, _dummy_isp, _dummy_isp, _dummy_isp,
85_mtua4_isp, _mtub4_isp, _mtuc4_isp, _mtud4_isp,
86_mtuv4_isp, _dummy_isp, _dummy_isp, _dummy_isp,
87_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp, /* SCI0-1: irq 128-135*/
88_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp,
89_adi0_isp, _adi1_isp, _dummy_isp, _dummy_isp, /* ADC0-1: irq 136-139*/
90_dtci_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* DTU: irq 140-143 */
91_cmt0_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* CMT0-1: irq 144-151 */
92_cmt1_isp, _dummy_isp, _dummy_isp, _dummy_isp,
93_wdt_isp, /* WDT: irq 152*/
94_bsc_isp, _dummy_isp, _dummy_isp, /* BSC: irq 153-155*/
95_oei_isp, /* I/O Port: irq 156*/
96};
97
98#define Str(a)#a
99
100/*
101 * Some versions of gcc and all version of egcs at least until egcs-1.1b
102 * are not able to handle #pragma interrupt correctly if more than 1 isr is
103 * contained in a file and when optimizing.
104 * We try to work around this problem by using the macro below.
105 */
106#define isp( name, number, func)\
107__asm__ (".global _"Str(name)"\n\t"\
108     "_"Str(name)":       \n\t"\
109     "    mov.l r0,@-r15   \n\t"\
110     "    mov.l r1,@-r15   \n\t"\
111     "    mov.l r2,@-r15   \n\t"\
112     "    mov.l r3,@-r15   \n\t"\
113     "    mov.l r4,@-r15   \n\t"\
114     "    mov.l r5,@-r15   \n\t"\
115     "    mov.l r6,@-r15   \n\t"\
116     "    mov.l r7,@-r15   \n\t"\
117     "    mov.l r14,@-r15  \n\t"\
118     "    sts.l pr,@-r15   \n\t"\
119     "    sts.l mach,@-r15 \n\t"\
120     "    sts.l macl,@-r15 \n\t"\
121     "    mov r15,r14      \n\t"\
122     "    mov.l "Str(name)"_v, r2 \n\t"\
123     "    mov.l "Str(name)"_k, r1\n\t"\
124     "    jsr @r1           \n\t"\
125     "    mov   r2,r4      \n\t"\
126     "    mov   r14,r15    \n\t"\
127     "    lds.l @r15+,macl \n\t"\
128     "    lds.l @r15+,mach \n\t"\
129     "    lds.l @r15+,pr   \n\t"\
130     "    mov.l @r15+,r14  \n\t"\
131     "    mov.l @r15+,r7   \n\t"\
132     "    mov.l @r15+,r6   \n\t"\
133     "    mov.l @r15+,r5   \n\t"\
134     "    mov.l @r15+,r4   \n\t"\
135     "    mov.l @r15+,r3   \n\t"\
136     "    mov.l @r15+,r2   \n\t"\
137     "    mov.l @r15+,r1   \n\t"\
138     "    mov.l @r15+,r0   \n\t"\
139     "    rte              \n\t"\
140     "    nop              \n\t"\
141     "    .align 2         \n\t"\
142     #name"_k: \n\t"\
143     ".long "Str(func)"\n\t"\
144     #name"_v: \n\t"\
145     ".long "Str(number));
146
147/************************************************
148 * Dummy interrupt service procedure for
149 * interrupts being not allowed --> Trap 34
150 ************************************************/
151__asm__ (" .section .text\n\
152.global __dummy_isp\n\
153__dummy_isp:\n\
154      mov.l r14,@-r15\n\
155      mov   r15, r14\n\
156      trapa #34\n\
157      mov.l @r15+,r14\n\
158      rte\n\
159      nop");
160
161/*******************************************************************
162 *     ISP Vector Table for sh7045 family of processors            *
163 *******************************************************************/
164
165
166/*****************************
167 * Non maskable interrupt
168 *****************************/
169isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler);
170
171/*****************************
172 * User break controller
173 *****************************/
174isp( _usb_isp, USB_ISP_V, ___ISR_Handler);
175
176/*****************************
177 *  External interrupts 0-7
178 *****************************/
179isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler);
180isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler);
181isp( _irq2_isp, IRQ2_ISP_V, ___ISR_Handler);
182isp( _irq3_isp, IRQ3_ISP_V, ___ISR_Handler);
183isp( _irq4_isp, IRQ4_ISP_V, ___ISR_Handler);
184isp( _irq5_isp, IRQ5_ISP_V, ___ISR_Handler);
185isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler);
186isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler);
187
188/*****************************
189 * DMA - controller
190 *****************************/
191isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler);
192isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler);
193isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler);
194isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler);
195
196
197/*****************************
198 * Match timer unit
199 *****************************/
200
201/*****************************
202 * Timer 0
203 *****************************/
204isp( _mtua0_isp, MTUA0_ISP_V, ___ISR_Handler);
205isp( _mtub0_isp, MTUB0_ISP_V, ___ISR_Handler);
206isp( _mtuc0_isp, MTUC0_ISP_V, ___ISR_Handler);
207isp( _mtud0_isp, MTUD0_ISP_V, ___ISR_Handler);
208isp( _mtuv0_isp, MTUV0_ISP_V, ___ISR_Handler);
209
210/*****************************
211 * Timer 1
212 *****************************/
213isp( _mtua1_isp, MTUA1_ISP_V, ___ISR_Handler);
214isp( _mtub1_isp, MTUB1_ISP_V, ___ISR_Handler);
215isp( _mtuv1_isp, MTUV1_ISP_V, ___ISR_Handler);
216isp( _mtuu1_isp, MTUU1_ISP_V, ___ISR_Handler);
217
218/*****************************
219 * Timer 2
220 *****************************/
221isp( _mtua2_isp, MTUA2_ISP_V, ___ISR_Handler);
222isp( _mtub2_isp, MTUB2_ISP_V, ___ISR_Handler);
223isp( _mtuv2_isp, MTUV2_ISP_V, ___ISR_Handler);
224isp( _mtuu2_isp, MTUU2_ISP_V, ___ISR_Handler);
225
226/*****************************
227 * Timer 3
228 *****************************/
229isp( _mtua3_isp, MTUA3_ISP_V, ___ISR_Handler);
230isp( _mtub3_isp, MTUB3_ISP_V, ___ISR_Handler);
231isp( _mtuc3_isp, MTUC3_ISP_V, ___ISR_Handler);
232isp( _mtud3_isp, MTUD3_ISP_V, ___ISR_Handler);
233isp( _mtuv3_isp, MTUV3_ISP_V, ___ISR_Handler);
234
235/*****************************
236 * Timer 4
237 *****************************/
238isp( _mtua4_isp, MTUA4_ISP_V, ___ISR_Handler);
239isp( _mtub4_isp, MTUB4_ISP_V, ___ISR_Handler);
240isp( _mtuc4_isp, MTUC4_ISP_V, ___ISR_Handler);
241isp( _mtud4_isp, MTUD4_ISP_V, ___ISR_Handler);
242isp( _mtuv4_isp, MTUV4_ISP_V, ___ISR_Handler);
243
244
245/*****************************
246 * Serial interfaces
247 *****************************/
248
249/*****************************
250 * Serial interface 0
251 *****************************/
252isp( _eri0_isp,  ERI0_ISP_V, ___ISR_Handler);
253isp( _rxi0_isp,  RXI0_ISP_V, ___ISR_Handler);
254isp( _txi0_isp,  TXI0_ISP_V, ___ISR_Handler);
255isp( _tei0_isp,  TEI0_ISP_V, ___ISR_Handler);
256
257/*****************************
258 * Serial interface 1
259 *****************************/
260isp( _eri1_isp,  ERI1_ISP_V, ___ISR_Handler);
261isp( _rxi1_isp,  RXI1_ISP_V, ___ISR_Handler);
262isp( _txi1_isp,  TXI1_ISP_V, ___ISR_Handler);
263isp( _tei1_isp,  TEI1_ISP_V, ___ISR_Handler);
264
265
266/******************************
267 * A/D converters
268 * ADC0-1
269 ******************************/
270isp( _adi0_isp,  ADI0_ISP_V, ___ISR_Handler);
271isp( _adi1_isp,  ADI1_ISP_V, ___ISR_Handler);
272
273
274/******************************
275 *  Data transfer controller
276 ******************************/
277isp( _dtci_isp,  DTC_ISP_V, ___ISR_Handler);
278
279
280/******************************
281 *  Counter match timer
282 ******************************/
283isp( _cmt0_isp,  CMT0_ISP_V, ___ISR_Handler);
284isp( _cmt1_isp,  CMT1_ISP_V, ___ISR_Handler);
285
286
287/******************************
288 *  Watchdog timer
289 ******************************/
290isp( _wdt_isp,  WDT_ISP_V, ___ISR_Handler);
291
292
293/******************************
294 * DRAM refresh control unit
295 * of bus state controller
296 ******************************/
297isp( _bsc_isp,  CMI_ISP_V, ___ISR_Handler);
298
299/******************************
300 *  I/O port
301 ******************************/
302isp( _oei_isp,  OEI_ISP_V, ___ISR_Handler);
303
304
305/*****************************
306 * Parity control unit of
307 * the bus state controller
308 * NOT PROVIDED IN SH-2
309 *****************************/
310/* isp( _prt_isp,  PRT_ISP_V, ___ISR_Handler); */
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