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source: rtems/c/src/lib/libbsp/sh/gensh2/startup/ispsh7045.c @ 533e2c0

5

Last change on this file since 533e2c0 was 533e2c0, checked in by Sebastian Huber <sebastian.huber@…>, on 12/08/17 at 12:31:12

bsp/gensh2: Move libcpu files to BSP

Update #3254.

Property mode set to 100644

File size: 10.1 KB

Rev	Line
[b22a19e]	1	/*
	2	* This file contains the isp frames for the user interrupts.
	3	* From these procedures __ISR_Handler is called with the vector number
	4	* as argument.
	5	*
[3906b3ea]	6	* __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in
	7	* some releases of gcc doesn't properly handle #pragma interrupt, if a
[b22a19e]	8	* file contains both isrs and normal functions.
	9	*
	10	* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
	11	* Bernd Becker (becker@faw.uni-ulm.de)
	12	*
	13	* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
[3906b3ea]	18	*
[b22a19e]	19	*
	20	* COPYRIGHT (c) 1998.
	21	* On-Line Applications Research Corporation (OAR).
	22	*
	23	* The license and distribution terms for this file may be
	24	* found in the file LICENSE in this distribution or at
[c499856]	25	* http://www.rtems.org/license/LICENSE.
[b22a19e]	26	*
	27	* Modified to reflect isp entries for sh7045 processor:
	28	* John M. Mills (jmills@tga.com)
	29	* TGA Technologies, Inc.
	30	* 100 Pinnacle Way, Suite 140
	31	* Norcross, GA 30071 U.S.A.
	32	* August, 1999
	33	*
	34	* This modified file may be copied and distributed in accordance
	35	* the above-referenced license. It is provided for critique and
	36	* developmental purposes without any warranty nor representation
	37	* by the authors or by TGA Technologies.
	38	*/
	39
	40	#include <rtems/system.h>
[d911f16c]	41	#include <rtems/score/types.h>
[b22a19e]	42
	43	/*
	44	* This is a exception vector table
	45	*
	46	* It has the same structure as the actual vector table (vectab)
	47	*/
	48
	49
	50	/* SH-2 ISR Table */
	51	#include <rtems/score/ispsh7045.h>
	52
	53	proc_ptr _Hardware_isr_Table[256]={
	54	_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* PWRon Reset, Maual Reset,...*/
[3906b3ea]	55	_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
[b22a19e]	56	_dummy_isp, _dummy_isp, _dummy_isp,
	57	_nmi_isp, _usb_isp, /* irq 11, 12*/
[3906b3ea]	58	_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
	59	_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
	60	_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
	61	_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
	62	_dummy_isp, _dummy_isp, _dummy_isp,
[b22a19e]	63	/* trapa 0 -31 */
	64	_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
[3906b3ea]	65	_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
	66	_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
	67	_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
	68	_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
	69	_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
	70	_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
	71	_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
[b22a19e]	72	_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp, /* external H/W: irq 64-71 */
	73	_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp,
	74	_dma0_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* DMAC: irq 72-87*/
	75	_dma1_isp, _dummy_isp, _dummy_isp, _dummy_isp,
	76	_dma2_isp, _dummy_isp, _dummy_isp, _dummy_isp,
	77	_dma3_isp, _dummy_isp, _dummy_isp, _dummy_isp,
	78	_mtua0_isp, _mtub0_isp, _mtuc0_isp, _mtud0_isp, /* MTUs: irq 88-127 */
[3906b3ea]	79	_mtuv0_isp, _dummy_isp, _dummy_isp, _dummy_isp,
[b22a19e]	80	_mtua1_isp, _mtub1_isp, _dummy_isp, _dummy_isp,
[3906b3ea]	81	_mtuv1_isp, _mtuu1_isp, _dummy_isp, _dummy_isp,
[b22a19e]	82	_mtua2_isp, _mtub2_isp, _dummy_isp, _dummy_isp,
[3906b3ea]	83	_mtuv2_isp, _mtuu2_isp, _dummy_isp, _dummy_isp,
[b22a19e]	84	_mtua3_isp, _mtub3_isp, _mtuc3_isp, _mtud3_isp,
[3906b3ea]	85	_mtuv3_isp, _dummy_isp, _dummy_isp, _dummy_isp,
[b22a19e]	86	_mtua4_isp, _mtub4_isp, _mtuc4_isp, _mtud4_isp,
[3906b3ea]	87	_mtuv4_isp, _dummy_isp, _dummy_isp, _dummy_isp,
[b22a19e]	88	_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp, /* SCI0-1: irq 128-135*/
	89	_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp,
	90	_adi0_isp, _adi1_isp, _dummy_isp, _dummy_isp, /* ADC0-1: irq 136-139*/
	91	_dtci_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* DTU: irq 140-143 */
	92	_cmt0_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* CMT0-1: irq 144-151 */
	93	_cmt1_isp, _dummy_isp, _dummy_isp, _dummy_isp,
	94	_wdt_isp, /* WDT: irq 152*/
	95	_bsc_isp, _dummy_isp, _dummy_isp, /* BSC: irq 153-155*/
	96	_oei_isp, /* I/O Port: irq 156*/
	97	};
	98
	99	#define Str(a)#a
	100
	101	/*
	102	* Some versions of gcc and all version of egcs at least until egcs-1.1b
[3906b3ea]	103	* are not able to handle #pragma interrupt correctly if more than 1 isr is
[b22a19e]	104	* contained in a file and when optimizing.
	105	* We try to work around this problem by using the macro below.
	106	*/
	107	#define isp( name, number, func)\
[099ea991]	108	__asm__ (".global _"Str(name)"\n\t"\
[d089d90]	109	"_"Str(name)": \n\t"\
	110	" mov.l r0,@-r15 \n\t"\
	111	" mov.l r1,@-r15 \n\t"\
	112	" mov.l r2,@-r15 \n\t"\
	113	" mov.l r3,@-r15 \n\t"\
	114	" mov.l r4,@-r15 \n\t"\
	115	" mov.l r5,@-r15 \n\t"\
	116	" mov.l r6,@-r15 \n\t"\
	117	" mov.l r7,@-r15 \n\t"\
	118	" mov.l r14,@-r15 \n\t"\
	119	" sts.l pr,@-r15 \n\t"\
	120	" sts.l mach,@-r15 \n\t"\
	121	" sts.l macl,@-r15 \n\t"\
	122	" mov r15,r14 \n\t"\
	123	" mov.l "Str(name)"_v, r2 \n\t"\
	124	" mov.l "Str(name)"_k, r1\n\t"\
	125	" jsr @r1 \n\t"\
	126	" mov r2,r4 \n\t"\
	127	" mov r14,r15 \n\t"\
	128	" lds.l @r15+,macl \n\t"\
	129	" lds.l @r15+,mach \n\t"\
	130	" lds.l @r15+,pr \n\t"\
	131	" mov.l @r15+,r14 \n\t"\
	132	" mov.l @r15+,r7 \n\t"\
	133	" mov.l @r15+,r6 \n\t"\
	134	" mov.l @r15+,r5 \n\t"\
	135	" mov.l @r15+,r4 \n\t"\
	136	" mov.l @r15+,r3 \n\t"\
	137	" mov.l @r15+,r2 \n\t"\
	138	" mov.l @r15+,r1 \n\t"\
	139	" mov.l @r15+,r0 \n\t"\
	140	" rte \n\t"\
	141	" nop \n\t"\
	142	" .align 2 \n\t"\
	143	#name"_k: \n\t"\
	144	".long "Str(func)"\n\t"\
	145	#name"_v: \n\t"\
[7ae5125]	146	".long "Str(number));
[b22a19e]	147
	148	/************************************************
[3906b3ea]	149	* Dummy interrupt service procedure for
	150	* interrupts being not allowed --> Trap 34
[b22a19e]	151	************************************************/
[3d0af835]	152	__asm__ (" .section .text\n\
[fa5a451]	153	.global __dummy_isp\n\
	154	__dummy_isp:\n\
	155	mov.l r14,@-r15\n\
	156	mov r15, r14\n\
	157	trapa #34\n\
	158	mov.l @r15+,r14\n\
	159	rte\n\
[b22a19e]	160	nop");
	161
	162	/*******************************************************************
	163	* ISP Vector Table for sh7045 family of processors *
	164	*******************************************************************/
	165
	166
	167	/*****************************
[3906b3ea]	168	* Non maskable interrupt
[b22a19e]	169	*****************************/
	170	isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler);
	171
[3906b3ea]	172	/*****************************
	173	* User break controller
[b22a19e]	174	*****************************/
	175	isp( _usb_isp, USB_ISP_V, ___ISR_Handler);
	176
	177	/*****************************
[3906b3ea]	178	* External interrupts 0-7
[b22a19e]	179	*****************************/
	180	isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler);
	181	isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler);
	182	isp( _irq2_isp, IRQ2_ISP_V, ___ISR_Handler);
	183	isp( _irq3_isp, IRQ3_ISP_V, ___ISR_Handler);
	184	isp( _irq4_isp, IRQ4_ISP_V, ___ISR_Handler);
	185	isp( _irq5_isp, IRQ5_ISP_V, ___ISR_Handler);
	186	isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler);
	187	isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler);
	188
	189	/*****************************
[3906b3ea]	190	* DMA - controller
[b22a19e]	191	*****************************/
	192	isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler);
	193	isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler);
	194	isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler);
	195	isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler);
	196
	197
[3906b3ea]	198	/*****************************
	199	* Match timer unit
[b22a19e]	200	*****************************/
	201
	202	/*****************************
[3906b3ea]	203	* Timer 0
[b22a19e]	204	*****************************/
	205	isp( _mtua0_isp, MTUA0_ISP_V, ___ISR_Handler);
	206	isp( _mtub0_isp, MTUB0_ISP_V, ___ISR_Handler);
	207	isp( _mtuc0_isp, MTUC0_ISP_V, ___ISR_Handler);
	208	isp( _mtud0_isp, MTUD0_ISP_V, ___ISR_Handler);
	209	isp( _mtuv0_isp, MTUV0_ISP_V, ___ISR_Handler);
	210
	211	/*****************************
	212	* Timer 1
	213	*****************************/
	214	isp( _mtua1_isp, MTUA1_ISP_V, ___ISR_Handler);
	215	isp( _mtub1_isp, MTUB1_ISP_V, ___ISR_Handler);
	216	isp( _mtuv1_isp, MTUV1_ISP_V, ___ISR_Handler);
	217	isp( _mtuu1_isp, MTUU1_ISP_V, ___ISR_Handler);
	218
	219	/*****************************
	220	* Timer 2
	221	*****************************/
	222	isp( _mtua2_isp, MTUA2_ISP_V, ___ISR_Handler);
	223	isp( _mtub2_isp, MTUB2_ISP_V, ___ISR_Handler);
	224	isp( _mtuv2_isp, MTUV2_ISP_V, ___ISR_Handler);
	225	isp( _mtuu2_isp, MTUU2_ISP_V, ___ISR_Handler);
	226
	227	/*****************************
	228	* Timer 3
	229	*****************************/
	230	isp( _mtua3_isp, MTUA3_ISP_V, ___ISR_Handler);
	231	isp( _mtub3_isp, MTUB3_ISP_V, ___ISR_Handler);
	232	isp( _mtuc3_isp, MTUC3_ISP_V, ___ISR_Handler);
	233	isp( _mtud3_isp, MTUD3_ISP_V, ___ISR_Handler);
	234	isp( _mtuv3_isp, MTUV3_ISP_V, ___ISR_Handler);
	235
	236	/*****************************
	237	* Timer 4
	238	*****************************/
	239	isp( _mtua4_isp, MTUA4_ISP_V, ___ISR_Handler);
	240	isp( _mtub4_isp, MTUB4_ISP_V, ___ISR_Handler);
	241	isp( _mtuc4_isp, MTUC4_ISP_V, ___ISR_Handler);
	242	isp( _mtud4_isp, MTUD4_ISP_V, ___ISR_Handler);
	243	isp( _mtuv4_isp, MTUV4_ISP_V, ___ISR_Handler);
	244
	245
	246	/*****************************
[3906b3ea]	247	* Serial interfaces
[b22a19e]	248	*****************************/
	249
	250	/*****************************
	251	* Serial interface 0
	252	*****************************/
	253	isp( _eri0_isp, ERI0_ISP_V, ___ISR_Handler);
	254	isp( _rxi0_isp, RXI0_ISP_V, ___ISR_Handler);
	255	isp( _txi0_isp, TXI0_ISP_V, ___ISR_Handler);
	256	isp( _tei0_isp, TEI0_ISP_V, ___ISR_Handler);
	257
	258	/*****************************
	259	* Serial interface 1
	260	*****************************/
	261	isp( _eri1_isp, ERI1_ISP_V, ___ISR_Handler);
	262	isp( _rxi1_isp, RXI1_ISP_V, ___ISR_Handler);
	263	isp( _txi1_isp, TXI1_ISP_V, ___ISR_Handler);
	264	isp( _tei1_isp, TEI1_ISP_V, ___ISR_Handler);
	265
	266
[3906b3ea]	267	/******************************
[b22a19e]	268	* A/D converters
[3906b3ea]	269	* ADC0-1
[b22a19e]	270	******************************/
	271	isp( _adi0_isp, ADI0_ISP_V, ___ISR_Handler);
	272	isp( _adi1_isp, ADI1_ISP_V, ___ISR_Handler);
	273
	274
	275	/******************************
[3906b3ea]	276	* Data transfer controller
[b22a19e]	277	******************************/
	278	isp( _dtci_isp, DTC_ISP_V, ___ISR_Handler);
	279
	280
	281	/******************************
[3906b3ea]	282	* Counter match timer
[b22a19e]	283	******************************/
	284	isp( _cmt0_isp, CMT0_ISP_V, ___ISR_Handler);
	285	isp( _cmt1_isp, CMT1_ISP_V, ___ISR_Handler);
	286
	287
	288	/******************************
[3906b3ea]	289	* Watchdog timer
[b22a19e]	290	******************************/
	291	isp( _wdt_isp, WDT_ISP_V, ___ISR_Handler);
	292
	293
	294	/******************************
[3906b3ea]	295	* DRAM refresh control unit
	296	* of bus state controller
[b22a19e]	297	******************************/
	298	isp( _bsc_isp, CMI_ISP_V, ___ISR_Handler);
	299
	300	/******************************
	301	* I/O port
	302	******************************/
	303	isp( _oei_isp, OEI_ISP_V, ___ISR_Handler);
	304
	305
	306	/*****************************
[3906b3ea]	307	* Parity control unit of
	308	* the bus state controller
[b22a19e]	309	* NOT PROVIDED IN SH-2
	310	*****************************/
	311	/* isp( _prt_isp, PRT_ISP_V, ___ISR_Handler); */

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