source: rtems/c/src/lib/libbsp/sh/gensh2/startup/hw_init.c @ 4a238002

4.104.114.84.95
Last change on this file since 4a238002 was 4a238002, checked in by Joel Sherrill <joel.sherrill@…>, on Nov 18, 1999 at 9:22:58 PM

Patch from "John M. Mills" <jmills@…> with subsequent cleanup from
Ralf Corsepius <corsepiu@…> that adds initial Hitachi SH-2
support to RTEMS. Ralf's comments are:

Changes:
------

  1. SH-Port:
  • Many files renamed.
  • CONSOLE_DEVNAME and MHZ defines removed from libcpu.
  • console.c moved to libbsp/sh/shared, build in libbsp/sh/<BSP>/console applying VPATH.
  • CONSOLE_DEVNAME made BSP-specific, replacement is defined in bsp.h
  • MHZ define replaced with HZ (extendent resolution) in custom/*.cfg
  • -DHZ=HZ used in bspstart.c, only
  • Makefile variable HZ used in bsp-dependent directories only.
  1. SH1-Port
  • clock-driver rewritten to provide better resolution for odd CPU frequencies. This driver is only partially tested on hardware, ie. sightly experimental, but I don't expect severe problems with it.
  • Polling SCI-driver added. This driver is experimental and completly untested yet. Therefore it is not yet used for the console (/dev/console is still pointing to /dev/null, cf. gensh1/bsp.h).
  • minor changes to the timer driver
  • SH1 specific delay()/CPU_delay() now is implemented as a function
  1. SH2-Port
  • Merged
  • IMO, the code is still in its infancy. Therefore I have interspersed comments (FIXME) it for items which I think John should look after.
  • sci and console drivers partially rewritten and extended (John, I hope you don't mind).
  • Copyright notices are not yet adapted
  • Property mode set to 100644
File size: 4.5 KB
Line 
1/*
2 *  hw_init.c: set up sh7045F internal subunits
3 *
4 *  Author: John M. Mills (jmills@tga.com)
5 *  COPYRIGHT(c) 1999, TGA Technologies, Inc
6 *                     Norcross, GA 30071 U.S.A
7 *
8 *  This program is distributed in the hope that it will be useful,
9 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
10 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
11 *
12 *
13 *  The license and distribution terms for this file may be
14 *  found in the file LICENSE in this distribution or at
15 *  http://www.OARcorp.com/rtems/license.html.
16 *
17 *  Adapted from Hitachi EVB7045F tutorial files by:
18 *  John M. Mills (jmills@tga.com)
19 *  TGA Technologies, Inc.
20 *  100 Pinnacle Way, Suite 140
21 *  Norcross, GA 30071 U.S.A.
22 * 
23 *
24 *  This file may be copied and distributed in accordance
25 *  the above-referenced license. It is provided for critique and
26 *  developmental purposes without any warranty nor representation
27 *  by the authors or by TGA Technologies.
28 *
29 *  $Id$
30 */
31
32#include <bsp.h>
33
34#include <stdlib.h>
35
36#include <rtems/libio.h>
37#include <iosupp.h>
38#include <rtems/score/sh_io.h>
39#include <rtems/score/iosh7045.h>
40
41/* exported entry */
42extern void hw_initialize (void);
43
44/* STANDALONE_EVB sets up bus, DRAM, PFC, and SCI0 */
45/* no STANDALONE_EVB accepts defaults, adds RESET, SCI1, WDT */
46
47/***************************************************/
48/*      Inline function to access CPU features     */
49/*      from C.  This makes use of GNU extensions. */
50/***************************************************/
51
52__inline__ void set_interrupt_mask(unsigned char mask)
53{
54  asm("mov.l r0,@-r15");
55  asm("mov %0,r0"::"r"(mask)); 
56  asm("and #0xF,r0");
57  asm("rotl r0");
58  asm("rotl r0");
59  asm("rotl r0");
60  asm("rotl r0");
61  asm("ldc r0,sr");
62  asm("mov.l @r15+,r0");
63}
64
65void hw_initialize (void) 
66{
67        int a;
68        unsigned8 temp8;
69        unsigned16 temp16;
70
71#ifdef STANDALONE_EVB
72        write16(0x2020, BSC_BCR1);  /* Bus width access - 32-bit on CS1 */
73        write16(0xF3DD, BSC_BCR2);  /* Idle cycles CS3-CS0 - 0 idle cycles*/
74        write16(0xFF3F, BSC_WCR1);  /* Waits for CS3-CS0 - 3 waits on CS1 */
75        write16(0x000F, BSC_WCR2);  /* Waits for DRAM/DMA access - default */
76        write16(0x0000, BSC_DCR);   /* DRAM control - default */
77        write16(0x0000, BSC_RTCSR); /* DRAM refresh - default */
78        write16(0x0000, BSC_RTCNT); /* DRAM refresh counter - default*/
79        write16(0x0000, BSC_RTCOR); /* DRAM refresh compare match - default */
80       
81        write16(0x5000, PFC_PACRH); /* Pin function controller - WRHH, WRHL */
82        write16(0x1550, PFC_PACRL1); /* Pin fun. controller - WRH,WRL,RD,CS1 */
83        write16(0x0000, PFC_PBCR1); /* Pin function controller - default */
84        write16(0x2005, PFC_PBCR2); /* Pin function controller - A18,A17,A16 */
85        write16(0xFFFF, PFC_PCCR);  /* Pin function controller - A15-A0  */
86        write16(0x5555, PFC_PDCRH1; /* Pin function controller - D31-D24 */
87        write16(0x5555, PFC_PDCRH2); /* Pin function controller - D23-D16 */
88        write16(0xFFFF, PFC_PDCRL); /* Pin function controller - D15-D0  */
89        write16(0x0000, PFC_IFCR);  /* Pin function controller - default */
90        write16(0x0005, PFC_PACRL2); /* Pin function controller - Tx0, Rx0 */
91
92        /* SCI0 */
93/* FIXME: This doesn't belong here */
94        write8(0x00, SCI_SCR0);     /* Clear SCR */
95        write8(0x00, SCI_SMR0);     /* Clear SMR */
96        write8(0x5F, SCI_BRR0);     /* Default 9600 baud rate */
97#if 0
98        write8(0x1F, SCI_BRR0);    /* 28800 baud */
99#endif
100/* FIXME: Will get optimized away */
101        for(a=0;a<00000L;a++);      /* One bit delay */
102        write8(0x30, SCI_SCR0);     /* Enable clock output */
103        temp8 = read8(SCI_RDR0);    /* Clear out old input */
104
105#endif
106
107        /* default hardware setup */
108
109        /* PFC: General I/O except pin 13 (reset): */
110        temp16 = read16(PFC_PECR1) | 0x0800;
111        write16(temp16, PFC_PECR1);
112
113        /* All I/O lines bits 7-0: */
114        write16(0x00, PFC_PECR2);
115
116        /* P5 out, all other pins in: */
117        temp16 = read16(PFC_PEIOR) | 0x0020;
118        write16(temp16, PFC_PEIOR);
119
120        /* PFC - pins for Tx0-1, Rx0-1: */
121        temp16 = read16(PFC_PACRL2) | 0x0145;
122        write16(temp16, PFC_PACRL2);
123
124        /* SCI1 - Default RTEMS console */
125#if FIXME
126        /* write8(0x00, SCI_SCR1);      /* Clear SCR */
127        /* write8(0x00, SCI_SMR1);      /* Clear SMR */
128        /* write8(0x5F, SCI_BRR1);      /* Default 9600 baud rate */
129        /* write8(0x1F, SCI_BRR1);    /* 28800 baud */
130/* FIXME: Will get optimized away */
131        /* for(a=0;a<10000L;a++);       /* One bit delay */
132        /* write8(0x30, SCI_SCR1);      /* Enable clock output */
133        /* temp8 = read8(SCI_RDR1);      /* Clear out old input */
134
135        /* INTC setup */
136        /* set_interrupt_mask(0);       /* enable interrupts */
137        /* INTC_IPRF &= ~(SCI1_IPMSK);  /* set SIO1 priority at INTC */
138        /* INTC_IPRF |= SCI1_LOWIP;     */
139#endif
140}
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