source: rtems/c/src/lib/libbsp/sh/gensh2/include/rtems/score/ispsh7045.h @ 533e2c0

5
Last change on this file since 533e2c0 was 533e2c0, checked in by Sebastian Huber <sebastian.huber@…>, on 12/08/17 at 12:31:12

bsp/gensh2: Move libcpu files to BSP

Update #3254.
  • Property mode set to 100644
File size: 4.9 KB
Line 
1/*
2 *  This include file contains information pertaining to the Hitachi SH
3 *  processor.
4 *
5 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
6 *           Bernd Becker (becker@faw.uni-ulm.de)
7 *
8 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
9 *
10 *  This program is distributed in the hope that it will be useful,
11 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
12 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 *
14 *
15 *  COPYRIGHT (c) 1998.
16 *  On-Line Applications Research Corporation (OAR).
17 *
18 *  The license and distribution terms for this file may be
19 *  found in the file LICENSE in this distribution or at
20 *  http://www.rtems.org/license/LICENSE.
21 *
22 *  Modified to reflect isp entries for sh7045 processor:
23 *  John M. Mills (jmills@tga.com)
24 *  TGA Technologies, Inc.
25 *  100 Pinnacle Way, Suite 140
26 *  Norcross, GA 30071 U.S.A.
27 *
28 *
29 *  This modified file may be copied and distributed in accordance
30 *  the above-referenced license. It is provided for critique and
31 *  developmental purposes without any warranty nor representation
32 *  by the authors or by TGA Technologies.
33 */
34
35#ifndef __CPU_ISPS_H
36#define __CPU_ISPS_H
37
38#ifdef __cplusplus
39extern "C" {
40#endif
41
42#include <rtems/score/types.h>
43
44extern void __ISR_Handler( uint32_t   vector );
45
46
47/*
48 * interrupt vector table offsets
49 */
50#define NMI_ISP_V 11
51#define USB_ISP_V 12
52#define IRQ0_ISP_V 64
53#define IRQ1_ISP_V 65
54#define IRQ2_ISP_V 66
55#define IRQ3_ISP_V 67
56#define IRQ4_ISP_V 68
57#define IRQ5_ISP_V 69
58#define IRQ6_ISP_V 70
59#define IRQ7_ISP_V 71
60#define DMA0_ISP_V 72
61#define DMA1_ISP_V 76
62#define DMA2_ISP_V 80
63#define DMA3_ISP_V 84
64
65#define MTUA0_ISP_V 88
66#define MTUB0_ISP_V 89
67#define MTUC0_ISP_V 90
68#define MTUD0_ISP_V 91
69#define MTUV0_ISP_V 92
70
71#define MTUA1_ISP_V 96
72#define MTUB1_ISP_V 97
73#define MTUV1_ISP_V 100
74#define MTUU1_ISP_V 101
75
76#define MTUA2_ISP_V 104
77#define MTUB2_ISP_V 105
78#define MTUV2_ISP_V 108
79#define MTUU2_ISP_V 109
80
81#define MTUA3_ISP_V 112
82#define MTUB3_ISP_V 113
83#define MTUC3_ISP_V 114
84#define MTUD3_ISP_V 115
85#define MTUV3_ISP_V 116
86
87#define MTUA4_ISP_V 120
88#define MTUB4_ISP_V 121
89#define MTUC4_ISP_V 122
90#define MTUD4_ISP_V 123
91#define MTUV4_ISP_V 124
92
93#define ERI0_ISP_V 128
94#define RXI0_ISP_V 129
95#define TXI0_ISP_V 130
96#define TEI0_ISP_V 131
97
98#define ERI1_ISP_V 132
99#define RXI1_ISP_V 133
100#define TXI1_ISP_V 134
101#define TEI1_ISP_V 135
102
103#define ADI0_ISP_V 136
104#define ADI1_ISP_V 137
105#define DTC_ISP_V 140  /* Data Transfer Controller */
106#define CMT0_ISP_V 144 /* Compare Match Timer */
107#define CMT1_ISP_V 148
108#define WDT_ISP_V 152  /* Wtachdog Timer */
109#define CMI_ISP_V 153  /* BSC RAS interrupt */
110#define OEI_ISP_V 156  /* I/O Port */
111#define DREF_ISP_V CMI_ISP_V /* DRAM Refresh from BSC */
112#if 0
113#define PRT_ISP_V /* parity error - no equivalent */
114#endif
115
116/* dummy ISP */
117extern void _dummy_isp( void );
118
119/* Non Maskable Interrupt */
120extern void _nmi_isp( void );
121
122/* User Break Controller */
123extern void _usb_isp( void );
124
125/* External interrupts 0-7 */
126extern void _irq0_isp( void );
127extern void _irq1_isp( void );
128extern void _irq2_isp( void );
129extern void _irq3_isp( void );
130extern void _irq4_isp( void );
131extern void _irq5_isp( void );
132extern void _irq6_isp( void );
133extern void _irq7_isp( void );
134
135/* DMA - Controller */
136extern void _dma0_isp( void );
137extern void _dma1_isp( void );
138extern void _dma2_isp( void );
139extern void _dma3_isp( void );
140
141/* Interrupt Timer Unit */
142/* Timer 0 */
143extern void _mtua0_isp( void );
144extern void _mtub0_isp( void );
145extern void _mtuc0_isp( void );
146extern void _mtud0_isp( void );
147extern void _mtuv0_isp( void );
148/* Timer 1 */
149extern void _mtua1_isp( void );
150extern void _mtub1_isp( void );
151extern void _mtuv1_isp( void );
152extern void _mtuu1_isp( void );
153/* Timer 2 */
154extern void _mtua2_isp( void );
155extern void _mtub2_isp( void );
156extern void _mtuv2_isp( void );
157extern void _mtuu2_isp( void );
158/* Timer 3 */
159extern void _mtua3_isp( void );
160extern void _mtub3_isp( void );
161extern void _mtuc3_isp( void );
162extern void _mtud3_isp( void );
163extern void _mtuv3_isp( void );
164/* Timer 4 */
165extern void _mtua4_isp( void );
166extern void _mtub4_isp( void );
167extern void _mtuc4_isp( void );
168extern void _mtud4_isp( void );
169extern void _mtuv4_isp( void );
170
171/* serial interfaces */
172extern void _eri0_isp( void );
173extern void _rxi0_isp( void );
174extern void _txi0_isp( void );
175extern void _tei0_isp( void );
176extern void _eri1_isp( void );
177extern void _rxi1_isp( void );
178extern void _txi1_isp( void );
179extern void _tei1_isp( void );
180
181/* ADC */
182extern void _adi0_isp( void );
183extern void _adi1_isp( void );
184
185/* Data Transfer Controller */
186extern void _dtci_isp( void );
187
188/* Compare Match Timer */
189extern void _cmt0_isp( void );
190extern void _cmt1_isp( void );
191
192/* Watchdog Timer */
193extern void _wdt_isp( void );
194
195/* DRAM refresh control unit of bus state controller */
196extern void _bsc_isp( void );
197
198/* I/O Port */
199extern void _oei_isp( void );
200
201/* Parity Control Unit of the Bus State Controllers */
202/* extern void _prt_isp( void ); */
203
204#ifdef __cplusplus
205}
206#endif
207
208#endif
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