1 | /* clock.c |
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2 | * |
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3 | * This routine initializes the interval timer on the |
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4 | * PowerPC 403 CPU. The tick frequency is specified by the bsp. |
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5 | * |
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6 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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7 | * |
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8 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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9 | * |
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10 | * To anyone who acknowledges that this file is provided "AS IS" |
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11 | * without any express or implied warranty: |
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12 | * permission to use, copy, modify, and distribute this file |
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13 | * for any purpose is hereby granted without fee, provided that |
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14 | * the above copyright notice and this notice appears in all |
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15 | * copies, and that the name of i-cubed limited not be used in |
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16 | * advertising or publicity pertaining to distribution of the |
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17 | * software without specific, written prior permission. |
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18 | * i-cubed limited makes no representations about the suitability |
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19 | * of this software for any purpose. |
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20 | * |
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21 | * Derived from c/src/lib/libcpu/hppa1.1/clock/clock.c: |
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22 | * |
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23 | * Modifications for deriving timer clock from cpu system clock by |
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24 | * Thomas Doerfler <td@imd.m.isar.de> |
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25 | * for these modifications: |
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26 | * COPYRIGHT (c) 1997 by IMD, Puchheim, Germany. |
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27 | * |
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28 | * COPYRIGHT (c) 1989-2007. |
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29 | * On-Line Applications Research Corporation (OAR). |
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30 | * |
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31 | * The license and distribution terms for this file may be |
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32 | * found in the file LICENSE in this distribution or at |
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33 | * http://www.rtems.com/license/LICENSE. |
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34 | * |
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35 | * Modifications for PPC405GP by Dennis Ehlin |
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36 | * |
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37 | * $Id: clock.c 63 2011-04-26 00:23:51Z claus $ |
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38 | */ |
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39 | |
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40 | #include <rtems.h> |
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41 | #include <rtems/clockdrv.h> |
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42 | #include <rtems/libio.h> |
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43 | #include <stdlib.h> /* for atexit() */ |
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44 | #include <rtems/bspIo.h> |
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45 | #include <rtems/powerpc/powerpc.h> |
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46 | |
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47 | /* |
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48 | * check, which exception handling code is present |
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49 | */ |
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50 | |
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51 | #include <bsp.h> |
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52 | |
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53 | #include <bsp/vectors.h> |
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54 | #include <bsp/irq_supp.h> |
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55 | |
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56 | volatile uint32_t Clock_driver_ticks; |
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57 | static uint32_t pit_value, tick_time; |
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58 | static bool auto_restart; |
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59 | |
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60 | void Clock_exit( void ); |
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61 | |
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62 | /* |
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63 | * These are set by clock driver during its init |
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64 | */ |
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65 | |
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66 | rtems_device_major_number rtems_clock_major = ~0; |
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67 | rtems_device_minor_number rtems_clock_minor; |
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68 | |
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69 | static inline uint32_t get_itimer(void) |
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70 | { |
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71 | register uint32_t rc; |
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72 | |
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73 | asm volatile ("mfspr %0, 0x10c" : "=r" ((rc))); /* 405GP TBL */ |
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74 | |
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75 | return rc; |
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76 | } |
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77 | |
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78 | /* |
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79 | * ISR Handler |
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80 | */ |
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81 | |
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82 | int Clock_isr(BSP_Exception_frame *f, unsigned int vector) |
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83 | { |
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84 | uint32_t clicks_til_next_interrupt; |
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85 | #if defined(BSP_PPC403_CLOCK_ISR_IRQ_LEVEL) |
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86 | uint32_t l_orig = _ISR_Get_level(); |
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87 | #endif |
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88 | if (!auto_restart) |
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89 | { |
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90 | uint32_t itimer_value; |
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91 | /* |
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92 | * setup for next interrupt; making sure the new value is reasonably |
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93 | * in the future.... in case we lost out on an interrupt somehow |
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94 | */ |
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95 | |
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96 | itimer_value = get_itimer(); |
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97 | tick_time += pit_value; |
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98 | |
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99 | /* |
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100 | * how far away is next interrupt *really* |
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101 | * It may be a long time; this subtraction works even if |
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102 | * Clock_clicks_interrupt < Clock_clicks_low_order via |
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103 | * the miracle of unsigned math. |
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104 | */ |
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105 | clicks_til_next_interrupt = tick_time - itimer_value; |
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106 | |
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107 | /* |
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108 | * If it is too soon then bump it up. |
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109 | * This should only happen if CPU_HPPA_CLICKS_PER_TICK is too small. |
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110 | * But setting it low is useful for debug, so... |
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111 | */ |
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112 | |
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113 | if (clicks_til_next_interrupt < 400) |
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114 | { |
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115 | tick_time = itimer_value + 1000; |
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116 | clicks_til_next_interrupt = 1000; |
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117 | /* XXX: count these! this should be rare */ |
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118 | } |
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119 | |
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120 | /* |
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121 | * If it is too late, that means we missed the interrupt somehow. |
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122 | * Rather than wait 35-50s for a wrap, we just fudge it here. |
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123 | */ |
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124 | |
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125 | if (clicks_til_next_interrupt > pit_value) |
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126 | { |
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127 | tick_time = itimer_value + 1000; |
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128 | clicks_til_next_interrupt = 1000; |
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129 | /* XXX: count these! this should never happen :-) */ |
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130 | } |
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131 | |
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132 | asm volatile ("mtspr 0x3db, %0" :: "r" |
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133 | (clicks_til_next_interrupt)); /* PIT */ |
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134 | } |
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135 | |
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136 | /* Clear the Programmable Interrupt Status */ |
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137 | asm volatile ( "mtspr 0x3d8, %0" :: "r" (0x08000000)); /* TSR */ |
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138 | |
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139 | Clock_driver_ticks++; |
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140 | |
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141 | rtems_clock_tick(); |
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142 | |
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143 | return 0; |
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144 | } |
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145 | |
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146 | void ClockOff(void) |
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147 | { |
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148 | register uint32_t tcr; |
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149 | |
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150 | asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */ |
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151 | |
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152 | tcr &= ~ 0x04400000; |
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153 | |
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154 | asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */ |
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155 | } |
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156 | |
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157 | void ClockOn(void) |
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158 | { |
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159 | uint32_t iocr; |
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160 | register uint32_t tcr; |
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161 | |
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162 | Clock_driver_ticks = 0; |
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163 | |
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164 | asm volatile ("mfdcr %0, 0x0b2" : "=r" (iocr)); /*405GP CPC0_CR1 */ |
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165 | if (bsp_timer_internal_clock) { |
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166 | iocr &=~0x800000; /* timer clocked from system clock CETE*/ |
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167 | } |
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168 | else { |
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169 | iocr |= 0x800000; /* select external timer clock CETE*/ |
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170 | } |
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171 | asm volatile ("mtdcr 0x0b2, %0" : "=r" (iocr) : "0" (iocr)); /* 405GP CPC0_CR1 */ |
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172 | |
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173 | /* |
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174 | * Enable auto restart |
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175 | */ |
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176 | |
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177 | auto_restart = true; |
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178 | |
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179 | pit_value = rtems_configuration_get_microseconds_per_tick() * |
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180 | bsp_clicks_per_usec; |
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181 | |
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182 | /* |
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183 | * Set PIT value |
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184 | */ |
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185 | |
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186 | asm volatile ("mtspr 0x3db, %0" : : "r" (pit_value)); /* PIT */ |
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187 | |
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188 | /* |
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189 | * Set timer to autoreload, bit TCR->ARE = 1 0x0400000 |
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190 | * Enable PIT interrupt, bit TCR->PIE = 1 0x4000000 |
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191 | */ |
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192 | tick_time = get_itimer() + pit_value; |
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193 | |
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194 | asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */ |
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195 | tcr = (tcr & ~0x04400000) | (auto_restart ? 0x04400000 : 0x04000000); |
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196 | asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */ |
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197 | } |
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198 | |
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199 | |
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200 | |
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201 | void Install_clock(ppc_exc_handler_t clock_isr) |
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202 | { |
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203 | #ifdef ppc403 |
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204 | uint32_t pvr; |
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205 | #endif /* ppc403 */ |
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206 | |
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207 | Clock_driver_ticks = 0; |
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208 | |
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209 | /* |
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210 | * initialize the interval here |
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211 | * First tick is set to right amount of time in the future |
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212 | * Future ticks will be incremented over last value set |
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213 | * in order to provide consistent clicks in the face of |
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214 | * interrupt overhead |
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215 | */ |
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216 | |
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217 | ppc_exc_set_handler( BSP_PPC403_CLOCK_HOOK_EXCEPTION, clock_isr ); |
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218 | ClockOn(); |
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219 | |
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220 | atexit(Clock_exit); |
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221 | } |
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222 | |
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223 | void |
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224 | ReInstall_clock(ppc_exc_handler_t clock_isr) |
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225 | { |
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226 | uint32_t isrlevel = 0; |
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227 | |
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228 | rtems_interrupt_disable(isrlevel); |
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229 | |
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230 | ppc_exc_set_handler( BSP_PPC403_CLOCK_HOOK_EXCEPTION, clock_isr ); |
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231 | ClockOn(); |
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232 | |
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233 | rtems_interrupt_enable(isrlevel); |
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234 | } |
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235 | |
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236 | |
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237 | /* |
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238 | * Called via atexit() |
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239 | * Remove the clock interrupt handler by setting handler to NULL |
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240 | * |
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241 | * This will not work on the 405GP because |
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242 | * when bit's are set in TCR they can only be unset by a reset |
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243 | */ |
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244 | |
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245 | void Clock_exit(void) |
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246 | { |
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247 | ClockOff(); |
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248 | ppc_exc_set_handler( BSP_PPC403_CLOCK_HOOK_EXCEPTION, 0 ); |
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249 | } |
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250 | |
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251 | rtems_device_driver Clock_initialize( |
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252 | rtems_device_major_number major, |
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253 | rtems_device_minor_number minor, |
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254 | void *pargp |
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255 | ) |
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256 | { |
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257 | Install_clock( Clock_isr ); |
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258 | |
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259 | /* |
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260 | * make major/minor avail to others such as shared memory driver |
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261 | */ |
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262 | |
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263 | rtems_clock_major = major; |
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264 | rtems_clock_minor = minor; |
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265 | |
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266 | return RTEMS_SUCCESSFUL; |
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267 | } |
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