1 | /*===============================================================*\ |
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2 | | Project: RTEMS virtex BSP | |
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3 | +-----------------------------------------------------------------+ |
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4 | | Partially based on the code references which are named below. | |
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5 | | Adaptions, modifications, enhancements and any recent parts of | |
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6 | | the code are: | |
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7 | | Copyright (c) 2007 | |
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8 | | Embedded Brains GmbH | |
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9 | | Obere Lagerstr. 30 | |
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10 | | D-82178 Puchheim | |
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11 | | Germany | |
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12 | | rtems@embedded-brains.de | |
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13 | +-----------------------------------------------------------------+ |
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14 | | The license and distribution terms for this file may be | |
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15 | | found in the file LICENSE in this distribution or at | |
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16 | | | |
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17 | | http://www.rtems.org/license/LICENSE. | |
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18 | | | |
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19 | +-----------------------------------------------------------------+ |
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20 | | this file contains the irq controller handler | |
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21 | \*===============================================================*/ |
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22 | |
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23 | /* Content moved from opbintctrl.c: |
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24 | * |
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25 | * This file contains definitions and declarations for the |
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26 | * Xilinx Off Processor Bus (OPB) Interrupt Controller |
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27 | * |
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28 | * Author: Keith Robertson <kjrobert@alumni.uwaterloo.ca> |
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29 | * COPYRIGHT (c) 2005 Linn Products Ltd, Scotland. |
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30 | * |
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31 | * The license and distribution terms for this file may be |
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32 | * found in the file LICENSE in this distribution or at |
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33 | * http://www.rtems.org/license/LICENSE. |
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34 | */ |
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35 | |
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36 | #include <bsp.h> |
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37 | #include <bsp/irq.h> |
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38 | #include <bsp/irq-generic.h> |
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39 | #include <bsp/vectors.h> |
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40 | |
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41 | #include <libcpu/powerpc-utility.h> |
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42 | |
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43 | /* |
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44 | * Acknowledge a mask of interrupts. |
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45 | */ |
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46 | static void set_iar(uint32_t mask) |
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47 | { |
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48 | *((volatile uint32_t *) (OPB_INTC_BASE + OPB_INTC_IAR)) = mask; |
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49 | } |
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50 | |
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51 | /* |
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52 | * Set IER state. Used to (dis)enable a mask of vectors. |
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53 | * If you only have to do one, use enable/disable_vector. |
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54 | */ |
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55 | static void set_ier(uint32_t mask) |
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56 | { |
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57 | *((volatile uint32_t *) (OPB_INTC_BASE + OPB_INTC_IER)) = mask; |
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58 | } |
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59 | |
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60 | /* |
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61 | * Retrieve contents of Interrupt Pending Register |
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62 | */ |
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63 | static uint32_t get_ipr(void) |
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64 | { |
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65 | uint32_t c = *((volatile uint32_t *) (OPB_INTC_BASE + OPB_INTC_IPR)); |
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66 | return c; |
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67 | } |
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68 | |
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69 | static void BSP_irq_enable_at_opbintc (rtems_irq_number irqnum) |
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70 | { |
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71 | *((volatile uint32_t *) (OPB_INTC_BASE + OPB_INTC_SIE)) |
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72 | = 1 << (irqnum - BSP_OPBINTC_IRQ_LOWEST_OFFSET); |
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73 | } |
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74 | |
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75 | static void BSP_irq_disable_at_opbintc (rtems_irq_number irqnum) |
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76 | { |
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77 | *((volatile uint32_t *) (OPB_INTC_BASE + OPB_INTC_CIE)) |
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78 | = 1 << (irqnum - BSP_OPBINTC_IRQ_LOWEST_OFFSET); |
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79 | } |
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80 | |
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81 | /* |
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82 | * IRQ Handler: this is called from the primary exception dispatcher |
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83 | */ |
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84 | static void BSP_irq_handle_at_opbintc(void) |
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85 | { |
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86 | uint32_t ipr; |
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87 | |
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88 | /* Get pending interrupts */ |
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89 | ipr = get_ipr(); |
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90 | |
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91 | if (ipr != 0) { |
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92 | /* Acknowledge all pending interrupts now and service them afterwards */ |
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93 | set_iar(ipr); |
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94 | |
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95 | do { |
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96 | /* Get highest priority pending interrupt */ |
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97 | uint32_t i = 31 - ppc_count_leading_zeros(ipr); |
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98 | |
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99 | ipr &= ~(1U << i); |
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100 | |
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101 | bsp_interrupt_handler_dispatch(i+BSP_OPBINTC_IRQ_LOWEST_OFFSET); |
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102 | } while (ipr != 0); |
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103 | } |
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104 | } |
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105 | |
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106 | /* |
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107 | * activate the interrupt controller |
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108 | */ |
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109 | static void opb_intc_init(void) |
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110 | { |
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111 | uint32_t i, mask = 0; |
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112 | |
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113 | /* mask off all interrupts */ |
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114 | set_ier(0x0); |
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115 | |
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116 | for (i = 0; i < OPB_INTC_IRQ_MAX; i++) { |
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117 | mask |= (1 << i); |
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118 | } |
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119 | |
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120 | /* make sure interupt status register is clear before we enable the interrupt controller */ |
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121 | *((volatile uint32_t *) (OPB_INTC_BASE + OPB_INTC_ISR)) = 0; |
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122 | |
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123 | /* acknowledge all interrupt sources */ |
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124 | set_iar(mask); |
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125 | |
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126 | /* Turn on normal hardware operation of interrupt controller */ |
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127 | *((volatile uint32_t *) (OPB_INTC_BASE + OPB_INTC_MER)) = |
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128 | (OPB_INTC_MER_HIE); |
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129 | |
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130 | /* Enable master interrupt switch for the interrupt controller */ |
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131 | *((volatile uint32_t *) (OPB_INTC_BASE + OPB_INTC_MER)) = |
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132 | (OPB_INTC_MER_HIE | OPB_INTC_MER_ME); |
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133 | } |
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134 | |
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135 | rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector) |
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136 | { |
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137 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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138 | |
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139 | if (bsp_interrupt_is_valid_vector(vector)) { |
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140 | if (BSP_IS_OPBINTC_IRQ(vector)) { |
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141 | BSP_irq_enable_at_opbintc(vector); |
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142 | } |
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143 | } else { |
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144 | sc = RTEMS_INVALID_ID; |
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145 | } |
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146 | |
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147 | return sc; |
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148 | } |
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149 | |
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150 | rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector) |
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151 | { |
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152 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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153 | |
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154 | if (bsp_interrupt_is_valid_vector(vector)) { |
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155 | if (BSP_IS_OPBINTC_IRQ(vector)) { |
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156 | BSP_irq_disable_at_opbintc(vector); |
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157 | } |
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158 | } else { |
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159 | sc = RTEMS_INVALID_ID; |
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160 | } |
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161 | |
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162 | return sc; |
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163 | } |
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164 | |
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165 | static int C_dispatch_irq_handler(BSP_Exception_frame *frame, unsigned int excNum) |
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166 | { |
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167 | BSP_irq_handle_at_opbintc(); |
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168 | |
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169 | return 0; |
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170 | } |
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171 | |
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172 | rtems_status_code bsp_interrupt_facility_initialize(void) |
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173 | { |
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174 | opb_intc_init(); |
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175 | |
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176 | ppc_exc_set_handler(ASM_EXT_VECTOR, C_dispatch_irq_handler); |
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177 | |
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178 | return RTEMS_SUCCESSFUL; |
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179 | } |
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