source: rtems/c/src/lib/libbsp/powerpc/virtex/include/xparameters_dflt.h @ 862c2317

4.104.114.84.95
Last change on this file since 862c2317 was 862c2317, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on 07/04/07 at 12:37:36

added virtex BSP support and some missing files for common PPC
exception handling
  • Property mode set to 100644
File size: 5.6 KB
Line 
1
2/*******************************************************************
3*
4* CAUTION: This file is automatically generated by libgen.
5* Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
6* DO NOT EDIT.
7*
8* Copyright (c) 2005 Xilinx, Inc.  All rights reserved.
9*
10* Description: Driver parameters
11*
12*******************************************************************/
13
14#define STDIN_BASEADDRESS 0x40600000
15#define STDOUT_BASEADDRESS 0x40600000
16
17/******************************************************************/
18
19/* Definitions for driver PLBARB */
20#define XPAR_XPLBARB_NUM_INSTANCES 1
21
22/* Definitions for peripheral PLB */
23#define XPAR_PLB_BASEADDR 0x00000000
24#define XPAR_PLB_HIGHADDR 0x00000000
25#define XPAR_PLB_DEVICE_ID 0
26#define XPAR_PLB_PLB_NUM_MASTERS 3
27
28
29/******************************************************************/
30
31/* Definitions for driver OPBARB */
32#define XPAR_XOPBARB_NUM_INSTANCES 1
33
34/* Definitions for peripheral OPB */
35#define XPAR_OPB_BASEADDR 0xFFFFFFFF
36#define XPAR_OPB_HIGHADDR 0x00000000
37#define XPAR_OPB_DEVICE_ID 0
38#define XPAR_OPB_NUM_MASTERS 1
39
40
41/******************************************************************/
42
43/* Definitions for driver UARTLITE */
44#define XPAR_XUARTLITE_NUM_INSTANCES 1
45
46/* Definitions for peripheral CONSOLE */
47#define XPAR_CONSOLE_BASEADDR 0x40600000
48#define XPAR_CONSOLE_HIGHADDR 0x4060FFFF
49#define XPAR_CONSOLE_DEVICE_ID 0
50#define XPAR_CONSOLE_BAUDRATE 115200
51#define XPAR_CONSOLE_USE_PARITY 0
52#define XPAR_CONSOLE_ODD_PARITY 0
53#define XPAR_CONSOLE_DATA_BITS 8
54
55
56/******************************************************************/
57
58/* Definitions for driver GPIO */
59#define XPAR_XGPIO_NUM_INSTANCES 3
60
61/* Definitions for peripheral LEDS */
62#define XPAR_LEDS_BASEADDR 0x40000000
63#define XPAR_LEDS_HIGHADDR 0x4000FFFF
64#define XPAR_LEDS_DEVICE_ID 0
65#define XPAR_LEDS_INTERRUPT_PRESENT 0
66#define XPAR_LEDS_IS_DUAL 0
67
68
69/* Definitions for peripheral PBLEDS */
70#define XPAR_PBLEDS_BASEADDR 0x40020000
71#define XPAR_PBLEDS_HIGHADDR 0x4002FFFF
72#define XPAR_PBLEDS_DEVICE_ID 1
73#define XPAR_PBLEDS_INTERRUPT_PRESENT 0
74#define XPAR_PBLEDS_IS_DUAL 0
75
76
77/* Definitions for peripheral PUSHBUTTONS */
78#define XPAR_PUSHBUTTONS_BASEADDR 0x40040000
79#define XPAR_PUSHBUTTONS_HIGHADDR 0x4004FFFF
80#define XPAR_PUSHBUTTONS_DEVICE_ID 2
81#define XPAR_PUSHBUTTONS_INTERRUPT_PRESENT 1
82#define XPAR_PUSHBUTTONS_IS_DUAL 0
83
84
85/******************************************************************/
86
87/* Definitions for driver TMRCTR */
88#define XPAR_XTMRCTR_NUM_INSTANCES 1
89
90/* Definitions for peripheral OPBTIMER */
91#define XPAR_OPBTIMER_BASEADDR 0x41C00000
92#define XPAR_OPBTIMER_HIGHADDR 0x41C0FFFF
93#define XPAR_OPBTIMER_DEVICE_ID 0
94
95
96/******************************************************************/
97
98#define XPAR_INTC_MAX_NUM_INTR_INPUTS 3
99#define XPAR_XINTC_HAS_IPR 1
100#define XPAR_XINTC_USE_DCR 0
101/* Definitions for driver INTC */
102#define XPAR_XINTC_NUM_INSTANCES 1
103
104/* Definitions for peripheral INTC */
105#define XPAR_INTC_BASEADDR 0x41200000
106#define XPAR_INTC_HIGHADDR 0x4120FFFF
107#define XPAR_INTC_DEVICE_ID 0
108#define XPAR_INTC_KIND_OF_INTR 0x00000000
109
110
111/******************************************************************/
112
113#define XPAR_INTC_SINGLE_BASEADDR 0x41200000
114#define XPAR_INTC_SINGLE_HIGHADDR 0x4120FFFF
115#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_INTC_DEVICE_ID
116#define XPAR_OPBTIMER_INTERRUPT_MASK 0X000001
117#define XPAR_INTC_OPBTIMER_INTERRUPT_INTR 0
118#define XPAR_ETHERNET_IP2INTC_IRPT_MASK 0X000002
119#define XPAR_INTC_ETHERNET_IP2INTC_IRPT_INTR 1
120#define XPAR_PUSHBUTTONS_IP2INTC_IRPT_MASK 0X000004
121#define XPAR_INTC_PUSHBUTTONS_IP2INTC_IRPT_INTR 2
122
123/******************************************************************/
124
125/* Definitions for driver DDR */
126#define XPAR_XDDR_NUM_INSTANCES 1
127
128/* Definitions for peripheral DDR_SDRAM_64MX32 */
129#define XPAR_DDR_SDRAM_64MX32_ECC_BASEADDR 0xFFFFFFFF
130#define XPAR_DDR_SDRAM_64MX32_ECC_HIGHADDR 0x00000000
131#define XPAR_DDR_SDRAM_64MX32_DEVICE_ID 0
132#define XPAR_DDR_SDRAM_64MX32_INCLUDE_ECC_INTR 0
133
134
135/******************************************************************/
136
137/* Definitions for peripheral DDR_SDRAM_64MX32 */
138#define XPAR_DDR_SDRAM_64MX32_MEM0_BASEADDR 0x00000000
139#define XPAR_DDR_SDRAM_64MX32_MEM0_HIGHADDR 0x03FFFFFF
140
141/******************************************************************/
142
143
144/* Definitions for peripheral HARD_TEMAC_0 */
145#define XPAR_HARD_TEMAC_0_PHY_TYPE 1
146
147
148/******************************************************************/
149
150/* Definitions for driver TEMAC */
151#define XPAR_XTEMAC_NUM_INSTANCES 1
152
153/* Definitions for peripheral ETHERNET */
154#define XPAR_ETHERNET_DEVICE_ID 0
155#define XPAR_ETHERNET_BASEADDR 0x81200000
156#define XPAR_ETHERNET_HIGHADDR 0x8120FFFF
157#define XPAR_ETHERNET_RXFIFO_DEPTH 32768
158#define XPAR_ETHERNET_TXFIFO_DEPTH 32768
159#define XPAR_ETHERNET_MAC_FIFO_DEPTH 64
160#define XPAR_ETHERNET_DMA_TYPE 1
161#define XPAR_ETHERNET_TX_DRE_TYPE 0
162#define XPAR_ETHERNET_RX_DRE_TYPE 0
163#define XPAR_ETHERNET_INCLUDE_TX_CSUM 0
164#define XPAR_ETHERNET_INCLUDE_RX_CSUM 0
165
166
167/******************************************************************/
168
169
170/* Definitions for peripheral FLASH */
171#define XPAR_FLASH_NUM_BANKS_MEM 1
172
173
174/******************************************************************/
175
176/* Definitions for peripheral FLASH */
177#define XPAR_FLASH_MEM0_BASEADDR 0x06000000
178#define XPAR_FLASH_MEM0_HIGHADDR 0x067FFFFF
179
180/******************************************************************/
181
182
183/* Definitions for peripheral PLB_BRAM_IF_CNTLR_1 */
184#define XPAR_PLB_BRAM_IF_CNTLR_1_BASEADDR 0xffff8000
185#define XPAR_PLB_BRAM_IF_CNTLR_1_HIGHADDR 0xffffffff
186
187
188/******************************************************************/
189
190#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000
191
192/******************************************************************/
193
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