1 | /* |
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2 | * This file contains the console driver for the xilinx uart lite. |
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3 | * |
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4 | * Author: Keith Robertson <kjrobert@alumni.uwaterloo.ca> |
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5 | * COPYRIGHT (c) 2005 by Linn Products Ltd, Scotland. |
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6 | * |
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7 | * Derived from libbsp/no_cpu/no_bsp/console.c and therefore also: |
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8 | * |
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9 | * COPYRIGHT (c) 1989-1999. |
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10 | * On-Line Applications Research Corporation (OAR). |
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11 | * |
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12 | * The license and distribution terms for this file may be |
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13 | * found in the file LICENSE in this distribution or at |
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14 | * http://www.rtems.com/license/LICENSE. |
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15 | * |
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16 | */ |
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17 | |
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18 | #include <rtems.h> |
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19 | #include <rtems/libio.h> |
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20 | #include <bsp/irq.h> |
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21 | |
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22 | #include <bsp.h> |
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23 | #include <libchip/serial.h> |
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24 | #include <libchip/sersupp.h> |
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25 | |
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26 | |
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27 | /* Status Register Masks */ |
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28 | #define PARITY_ERROR 0x80 /* Parity Error */ |
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29 | #define FRAME_ERROR 0x40 /* Frame Error */ |
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30 | #define OVERRUN_ERROR 0x20 /* Overrun Error */ |
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31 | #define STATUS_REG_ERROR_MASK ( PARITY_ERROR | FRAME_ERROR | OVERRUN_ERROR ) |
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32 | |
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33 | #define INTR_ENABLED 0x10 /* Interrupts are enabled */ |
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34 | #define TX_FIFO_FULL 0x08 /* Transmit FIFO is full */ |
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35 | #define TX_FIFO_EMPTY 0x04 /* Transmit FIFO is empty */ |
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36 | #define RX_FIFO_FULL 0x02 /* Receive FIFO is full */ |
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37 | #define RX_FIFO_VALID_DATA 0x01 /* Receive FIFO has valid data */ |
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38 | /* Control Register Masks*/ |
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39 | #define ENABLE_INTR 0x10 /* Enable interrupts */ |
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40 | #define RST_RX_FIFO 0x02 /* Reset and clear RX FIFO */ |
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41 | #define RST_TX_FIFO 0x01 /* Reset and clear TX FIFO */ |
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42 | |
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43 | /* General Defines */ |
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44 | #define TX_FIFO_SIZE 16 |
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45 | #define RX_FIFO_SIZE 16 |
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46 | |
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47 | |
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48 | |
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49 | |
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50 | #define RECV_REG 0 |
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51 | #define TRAN_REG 4 |
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52 | #define STAT_REG 8 |
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53 | #define CTRL_REG 12 |
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54 | |
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55 | |
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56 | |
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57 | RTEMS_INLINE_ROUTINE uint32_t xlite_uart_control(uint32_t base) |
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58 | { |
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59 | uint32_t c = *((volatile uint32_t*)(base+CTRL_REG)); |
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60 | return c; |
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61 | } |
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62 | |
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63 | |
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64 | RTEMS_INLINE_ROUTINE uint32_t xlite_uart_status(uint32_t base) |
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65 | { |
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66 | uint32_t c = *((volatile uint32_t*)(base+STAT_REG)); |
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67 | return c; |
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68 | } |
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69 | |
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70 | |
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71 | RTEMS_INLINE_ROUTINE uint32_t xlite_uart_read(uint32_t base) |
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72 | { |
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73 | uint32_t c = *((volatile uint32_t*)(base+RECV_REG)); |
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74 | return c; |
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75 | } |
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76 | |
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77 | |
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78 | RTEMS_INLINE_ROUTINE void xlite_uart_write(uint32_t base, char ch) |
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79 | { |
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80 | *(volatile uint32_t*)(base+TRAN_REG) = (uint32_t)ch; |
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81 | return; |
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82 | } |
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83 | |
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84 | |
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85 | |
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86 | int xlite_write_char(uint32_t base, char ch) |
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87 | { |
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88 | uint32_t retrycount= 0, idler, status; |
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89 | |
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90 | while( ((status = xlite_uart_status(base)) & TX_FIFO_FULL) != 0 ) |
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91 | { |
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92 | ++retrycount; |
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93 | |
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94 | /* uart tx is busy */ |
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95 | if( retrycount == 0x4000 ) |
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96 | { |
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97 | /* retrycount is arbitrary- just make it big enough so the uart is sure to be timed out before it trips */ |
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98 | return -1; |
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99 | } |
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100 | |
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101 | /* spin for a bit so we can sample the register rather than |
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102 | * continually reading it */ |
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103 | for( idler= 0; idler < 0x2000; idler++); |
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104 | } |
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105 | |
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106 | xlite_uart_write(base, ch); |
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107 | |
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108 | return 1; |
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109 | } |
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110 | |
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111 | |
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112 | |
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113 | |
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114 | |
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115 | |
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116 | |
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117 | |
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118 | |
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119 | |
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120 | |
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121 | void xlite_init (int minor ) |
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122 | { |
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123 | uint32_t base = Console_Port_Tbl[minor].ulCtrlPort1; |
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124 | |
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125 | /* clear status register */ |
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126 | *((volatile uint32_t*)(base+STAT_REG)) = 0; |
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127 | |
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128 | /* clear control register; reset fifos & interrupt enable */ |
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129 | *((volatile uint32_t*)(base+CTRL_REG)) = RST_RX_FIFO | RST_TX_FIFO; |
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130 | } |
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131 | |
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132 | |
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133 | int xlite_open( |
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134 | int major, |
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135 | int minor, |
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136 | void *arg |
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137 | ) |
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138 | { |
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139 | uint32_t base = Console_Port_Tbl[minor].ulCtrlPort1; |
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140 | |
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141 | /* the lite uarts have hardcoded baud & serial parms so no port |
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142 | * conditioning is needed. We're running polled so no interrupt |
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143 | * enables either */ |
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144 | |
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145 | /* clear status register */ |
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146 | *((volatile uint32_t*)(base+STAT_REG)) = 0; |
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147 | |
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148 | /* clear control register; reset fifos & disable interrupts */ |
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149 | *((volatile uint32_t*)(base+CTRL_REG)) = RST_RX_FIFO | RST_TX_FIFO; |
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150 | |
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151 | return RTEMS_SUCCESSFUL; |
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152 | } |
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153 | |
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154 | |
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155 | int xlite_close( |
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156 | int major, |
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157 | int minor, |
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158 | void *arg |
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159 | ) |
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160 | { |
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161 | /* no shutdown protocol necessary */ |
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162 | return RTEMS_SUCCESSFUL; |
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163 | } |
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164 | |
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165 | |
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166 | |
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167 | int xlite_read_polled (int minor ) |
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168 | { |
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169 | uint32_t base = Console_Port_Tbl[minor].ulCtrlPort1; |
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170 | |
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171 | unsigned int status = xlite_uart_status(base); |
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172 | |
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173 | if(status & RX_FIFO_VALID_DATA) |
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174 | return (int)xlite_uart_read(base); |
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175 | else |
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176 | return -1; |
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177 | } |
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178 | |
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179 | |
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180 | |
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181 | |
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182 | int xlite_write_buffer_polled( |
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183 | int minor, |
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184 | const char *buf, |
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185 | int len |
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186 | ) |
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187 | { |
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188 | uint32_t base = Console_Port_Tbl[minor].ulCtrlPort1; |
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189 | int nwrite = 0; |
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190 | |
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191 | /* |
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192 | * poll each byte in the string out of the port. |
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193 | */ |
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194 | while (nwrite < len) |
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195 | { |
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196 | if( xlite_write_char(base, *buf++) < 0 ) break; |
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197 | nwrite++; |
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198 | } |
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199 | |
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200 | /* |
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201 | * return the number of bytes written. |
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202 | */ |
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203 | return nwrite; |
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204 | } |
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205 | |
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206 | |
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207 | void xlite_write_char_polled( |
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208 | int minor, |
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209 | char c |
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210 | ) |
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211 | { |
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212 | uint32_t base = Console_Port_Tbl[minor].ulCtrlPort1; |
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213 | xlite_write_char(base, c); |
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214 | return; |
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215 | } |
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216 | |
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217 | |
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218 | |
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219 | int xlite_set_attributes(int minor, const struct termios *t) |
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220 | { |
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221 | return RTEMS_SUCCESSFUL; |
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222 | } |
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223 | |
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224 | |
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225 | |
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226 | |
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227 | |
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228 | |
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229 | |
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230 | console_fns xlite_fns_polled = |
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231 | { |
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232 | libchip_serial_default_probe, /* deviceProbe */ |
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233 | xlite_open, /* deviceFirstOpen */ |
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234 | xlite_close, /* deviceLastClose */ |
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235 | xlite_read_polled, /* deviceRead */ |
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236 | xlite_write_buffer_polled, /* deviceWrite */ |
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237 | xlite_init, /* deviceInitialize */ |
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238 | xlite_write_char_polled, /* deviceWritePolled */ |
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239 | xlite_set_attributes, /* deviceSetAttributes */ |
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240 | FALSE, /* deviceOutputUsesInterrupts */ |
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241 | }; |
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242 | |
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243 | |
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244 | |
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245 | |
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246 | |
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247 | |
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248 | /* |
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249 | ** Set ulCtrlPort1 to the base address of each UART Lite instance. Set in vhdl model. |
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250 | */ |
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251 | |
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252 | |
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253 | console_tbl Console_Port_Tbl[] = { |
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254 | { |
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255 | "/dev/ttyS0", /* sDeviceName */ |
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256 | SERIAL_CUSTOM, /* deviceType */ |
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257 | &xlite_fns_polled, /* pDeviceFns */ |
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258 | NULL, /* deviceProbe, assume it is there */ |
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259 | NULL, /* pDeviceFlow */ |
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260 | 16, /* ulMargin */ |
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261 | 8, /* ulHysteresis */ |
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262 | (void *) NULL, /* NULL */ /* pDeviceParams */ |
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263 | 0x40600000, /* ulCtrlPort1 */ |
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264 | 0, /* ulCtrlPort2 */ |
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265 | 0, /* ulDataPort */ |
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266 | NULL, /* getRegister */ |
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267 | NULL, /* setRegister */ |
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268 | NULL, /* unused */ /* getData */ |
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269 | NULL, /* unused */ /* setData */ |
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270 | 0, /* ulClock */ |
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271 | 0 /* ulIntVector -- base for port */ |
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272 | }, |
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273 | { |
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274 | "/dev/ttyS1", /* sDeviceName */ |
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275 | SERIAL_CUSTOM, /* deviceType */ |
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276 | &xlite_fns_polled, /* pDeviceFns */ |
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277 | NULL, /* deviceProbe, assume it is there */ |
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278 | NULL, /* pDeviceFlow */ |
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279 | 16, /* ulMargin */ |
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280 | 8, /* ulHysteresis */ |
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281 | (void *) NULL, /* NULL */ /* pDeviceParams */ |
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282 | 0x40610000, /* ulCtrlPort1 */ |
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283 | 0, /* ulCtrlPort2 */ |
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284 | 0, /* ulDataPort */ |
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285 | NULL, /* getRegister */ |
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286 | NULL, /* setRegister */ |
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287 | NULL, /* unused */ /* getData */ |
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288 | NULL, /* unused */ /* setData */ |
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289 | 0, /* ulClock */ |
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290 | 0 /* ulIntVector -- base for port */ |
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291 | }, |
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292 | { |
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293 | "/dev/ttyS2", /* sDeviceName */ |
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294 | SERIAL_CUSTOM, /* deviceType */ |
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295 | &xlite_fns_polled, /* pDeviceFns */ |
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296 | NULL, /* deviceProbe, assume it is there */ |
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297 | NULL, /* pDeviceFlow */ |
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298 | 16, /* ulMargin */ |
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299 | 8, /* ulHysteresis */ |
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300 | (void *) NULL, /* NULL */ /* pDeviceParams */ |
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301 | 0x40620000, /* ulCtrlPort1 */ |
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302 | 0, /* ulCtrlPort2 */ |
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303 | 0, /* ulDataPort */ |
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304 | NULL, /* getRegister */ |
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305 | NULL, /* setRegister */ |
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306 | NULL, /* unused */ /* getData */ |
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307 | NULL, /* unused */ /* setData */ |
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308 | 0, /* ulClock */ |
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309 | 0 /* ulIntVector -- base for port */ |
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310 | }, |
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311 | { |
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312 | "/dev/ttyS3", /* sDeviceName */ |
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313 | SERIAL_CUSTOM, /* deviceType */ |
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314 | &xlite_fns_polled, /* pDeviceFns */ |
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315 | NULL, /* deviceProbe, assume it is there */ |
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316 | NULL, /* pDeviceFlow */ |
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317 | 16, /* ulMargin */ |
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318 | 8, /* ulHysteresis */ |
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319 | (void *) NULL, /* NULL */ /* pDeviceParams */ |
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320 | 0x40630000, /* ulCtrlPort1 */ |
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321 | 0, /* ulCtrlPort2 */ |
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322 | 0, /* ulDataPort */ |
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323 | NULL, /* getRegister */ |
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324 | NULL, /* setRegister */ |
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325 | NULL, /* unused */ /* getData */ |
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326 | NULL, /* unused */ /* setData */ |
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327 | 0, /* ulClock */ |
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328 | 0 /* ulIntVector -- base for port */ |
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329 | } |
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330 | }; |
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331 | |
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332 | |
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333 | |
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334 | |
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335 | #define NUM_CONSOLE_PORTS (sizeof(Console_Port_Tbl)/sizeof(console_tbl)) |
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336 | |
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337 | unsigned long Console_Port_Count = NUM_CONSOLE_PORTS; |
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338 | console_data Console_Port_Data[NUM_CONSOLE_PORTS]; |
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339 | rtems_device_minor_number Console_Port_Minor; |
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340 | |
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341 | |
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342 | |
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343 | |
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344 | |
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345 | |
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346 | |
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347 | |
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348 | #include <rtems/bspIo.h> |
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349 | |
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350 | void outputChar(char ch) |
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351 | { |
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352 | if (ch == '\n') { |
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353 | xlite_write_char_polled( 0, '\r' ); |
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354 | } |
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355 | xlite_write_char_polled( 0, ch ); |
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356 | } |
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357 | |
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358 | char inputChar() |
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359 | { |
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360 | return (char)xlite_read_polled(0); |
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361 | } |
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362 | |
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363 | BSP_output_char_function_type BSP_output_char = outputChar; |
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364 | BSP_polling_getchar_function_type BSP_poll_char = inputChar; |
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365 | |
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366 | |
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