1 | /*===============================================================*\ |
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2 | | Project: RTEMS TQM8xx BSP | |
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3 | +-----------------------------------------------------------------+ |
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4 | | This file has been adapted to MPC8xx by | |
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5 | | Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> | |
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6 | | Copyright (c) 2008 | |
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7 | | Embedded Brains GmbH | |
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8 | | Obere Lagerstr. 30 | |
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9 | | D-82178 Puchheim | |
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10 | | Germany | |
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11 | | rtems@embedded-brains.de | |
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12 | | | |
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13 | | See the other copyright notice below for the original parts. | |
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14 | +-----------------------------------------------------------------+ |
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15 | | The license and distribution terms for this file may be | |
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16 | | found in the file LICENSE in this distribution or at | |
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17 | | | |
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18 | | http://www.rtems.org/license/LICENSE. | |
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19 | | | |
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20 | +-----------------------------------------------------------------+ |
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21 | | this file contains the console driver | |
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22 | \*===============================================================*/ |
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23 | /* derived from: */ |
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24 | /* |
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25 | * mmutlbtab.c |
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26 | * |
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27 | * Copyright (c) 1999, National Research Council of Canada |
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28 | * |
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29 | * The license and distribution terms for this file may be |
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30 | * found in the file LICENSE in this distribution or at |
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31 | * http://www.rtems.org/license/LICENSE. |
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32 | */ |
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33 | |
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34 | #include <bsp.h> |
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35 | #include <mpc8xx/mmu.h> |
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36 | /* |
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37 | * This MMU_TLB_table is used to statically initialize the Table Lookaside |
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38 | * Buffers in the MMU of the TQM8xx board. |
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39 | * |
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40 | * We initialize the entries in both the instruction and data TLBs |
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41 | * with the same values - a few bits relevant to the data TLB are unused |
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42 | * in the instruction TLB. |
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43 | * |
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44 | * An Effective Page Number (EPN), Tablewalk Control Register (TWC) and |
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45 | * Real Page Number (RPN) value are supplied in the table for each TLB entry. |
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46 | * |
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47 | * The instruction and data TLBs each can hold 32 entries, so _TLB_Table must |
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48 | * not have more than 32 lines in it! |
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49 | * |
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50 | * We set up the virtual memory map so that virtual address of a |
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51 | * location is equal to its real address. |
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52 | */ |
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53 | MMU_TLB_table_t MMU_TLB_table[] = { |
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54 | /* |
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55 | * DRAM: Start address 0x00000000, 128M, |
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56 | * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, |
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57 | * R/W,X for all, no ASID comparison, not cache-inhibited. |
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58 | * EPN TWC RPN |
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59 | */ |
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60 | { 0x00000200, 0x0D, 0x000009FD }, /* DRAM - PS=8M */ |
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61 | { 0x00800200, 0x0D, 0x008009FD }, /* DRAM - PS=8M */ |
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62 | { 0x01000200, 0x0D, 0x010009FD }, /* DRAM - PS=8M */ |
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63 | { 0x01800200, 0x0D, 0x018009FD }, /* DRAM - PS=8M */ |
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64 | { 0x02000200, 0x0D, 0x020009FD }, /* DRAM - PS=8M */ |
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65 | { 0x02800200, 0x0D, 0x028009FD }, /* DRAM - PS=8M */ |
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66 | { 0x03000200, 0x0D, 0x030009FD }, /* DRAM - PS=8M */ |
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67 | { 0x03800200, 0x0D, 0x038009FD }, /* DRAM - PS=8M */ |
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68 | { 0x04000200, 0x0D, 0x040009FD }, /* DRAM - PS=8M */ |
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69 | { 0x04800200, 0x0D, 0x048009FD }, /* DRAM - PS=8M */ |
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70 | { 0x05000200, 0x0D, 0x050009FD }, /* DRAM - PS=8M */ |
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71 | { 0x05800200, 0x0D, 0x058009FD }, /* DRAM - PS=8M */ |
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72 | { 0x06000200, 0x0D, 0x060009FD }, /* DRAM - PS=8M */ |
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73 | { 0x06800200, 0x0D, 0x068009FD }, /* DRAM - PS=8M */ |
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74 | { 0x07000200, 0x0D, 0x070009FD }, /* DRAM - PS=8M */ |
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75 | { 0x07800200, 0x0D, 0x078009FD }, /* DRAM - PS=8M */ |
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76 | /* |
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77 | * |
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78 | * (IMMR-SPRs) Dual Port RAM: Start address 0xFA200000, 16K, |
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79 | * ASID=0x0, APG=0x0, guarded memory, write-through data cache policy, |
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80 | * R/W,X for all, no ASID comparison, cache-inhibited. |
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81 | * |
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82 | * Note: We use the value in MBXA/PG2, which is also the value that |
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83 | * EPPC-Bug programmed into our boards. The alternative is the value |
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84 | * in MBXA/PG1: 0xFFA00000. This value might well depend on the revision |
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85 | * of the firmware. |
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86 | * EPN TWC RPN |
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87 | */ |
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88 | { 0xFA200200, 0x13, 0xFA2009FF }, /* IMMR - PS=16K */ |
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89 | /* |
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90 | * |
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91 | * Flash: Start address 0x40000000, 8M, |
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92 | * ASID=0x0, APG=0x0, not guarded memory, |
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93 | * R/O,X for all, no ASID comparison, not cache-inhibited. |
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94 | * EPN TWC RPN |
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95 | */ |
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96 | { 0x40000200, 0x0D, 0x40000CFD } /* Flash - PS=8M */ |
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97 | }; |
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98 | |
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99 | /* |
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100 | * MMU_N_TLB_Table_Entries is defined here because the size of the |
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101 | * MMU_TLB_table is only known in this file. |
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102 | */ |
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103 | int MMU_N_TLB_Table_Entries = ( sizeof(MMU_TLB_table) / sizeof(MMU_TLB_table[0]) ); |
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