1 | /* |
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2 | * cpuinit.c |
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3 | * |
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4 | * TQM8xx initialization routines. |
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5 | * derived from MBX8xx BSP |
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6 | * adapted to TQM8xx by Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> |
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7 | * |
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8 | * Copyright (c) 1999, National Research Council of Canada |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #include <bsp.h> |
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16 | #include <bsp/tqm.h> |
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17 | |
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18 | |
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19 | /* |
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20 | * Initialize TQM8xx |
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21 | */ |
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22 | void _InitTQM8xx (void) |
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23 | { |
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24 | register uint32_t r1; |
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25 | |
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26 | /* |
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27 | * Initialize the Instruction Support Control Register (ICTRL) to a |
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28 | * an appropriate value for normal operation. A different value, |
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29 | * such as 0x0, may be more appropriate for debugging. |
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30 | */ |
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31 | r1 = 0x00000007; |
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32 | _mtspr( M8xx_ICTRL, r1 ); |
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33 | |
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34 | /* |
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35 | * Disable and invalidate the instruction and data caches. |
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36 | */ |
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37 | r1 = M8xx_CACHE_CMD_DISABLE; |
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38 | _mtspr( M8xx_IC_CST, r1 ); |
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39 | _isync; |
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40 | r1 = M8xx_CACHE_CMD_UNLOCKALL; |
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41 | _mtspr( M8xx_IC_CST, r1 ); |
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42 | _isync; |
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43 | r1 = M8xx_CACHE_CMD_INVALIDATE; /* invalidate all */ |
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44 | _mtspr( M8xx_IC_CST, r1 ); |
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45 | _isync; |
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46 | |
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47 | r1 = M8xx_CACHE_CMD_DISABLE; |
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48 | _mtspr( M8xx_DC_CST, r1 ); |
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49 | _isync; |
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50 | r1 = M8xx_CACHE_CMD_UNLOCKALL; |
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51 | _mtspr( M8xx_DC_CST, r1 ); |
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52 | _isync; |
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53 | r1 = M8xx_CACHE_CMD_INVALIDATE; /* invalidate all */ |
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54 | _mtspr( M8xx_DC_CST, r1 ); |
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55 | _isync; |
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56 | |
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57 | /* |
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58 | * Initialize the SIU Module Configuration Register (SIUMCR) |
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59 | * m8xx.siumcr = 0x00602900, the default value. |
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60 | */ |
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61 | m8xx.siumcr = M8xx_SIUMCR_EARP0 | M8xx_SIUMCR_DBGC3 | M8xx_SIUMCR_DBPC0 | |
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62 | M8xx_SIUMCR_DPC | M8xx_SIUMCR_MLRC2 | M8xx_SIUMCR_SEME; |
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63 | |
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64 | /* |
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65 | * Initialize the System Protection Control Register (SYPCR). |
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66 | * The SYPCR can only be written once after Reset. |
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67 | * - Enable bus monitor |
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68 | * - Disable software watchdog timer |
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69 | * m8xx.sypcr = 0xFFFFFF88, the default MBX and firmware value. |
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70 | */ |
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71 | m8xx.sypcr = M8xx_SYPCR_SWTC(0xFFFF) | M8xx_SYPCR_BMT(0xFF) | |
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72 | M8xx_SYPCR_BME | M8xx_SYPCR_SWF; |
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73 | |
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74 | /* Initialize the SIU Interrupt Edge Level Mask Register (SIEL) */ |
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75 | m8xx.siel = 0xAAAA0000; /* Default MBX and firmware value. */ |
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76 | |
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77 | /* Initialize the Transfer Error Status Register (TESR) */ |
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78 | m8xx.tesr = 0xFFFFFFFF; /* Default firmware value. */ |
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79 | |
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80 | /* Initialize the SDMA Configuration Register (SDCR) */ |
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81 | m8xx.sdcr = 0x00000001; /* Default firmware value. */ |
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82 | |
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83 | /* |
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84 | * Initialize the Timebase Status and Control Register (TBSCR) |
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85 | * m8xx.tbscr = 0x00C3, default MBX and firmware value. |
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86 | */ |
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87 | m8xx.tbscrk = M8xx_UNLOCK_KEY; /* unlock TBSCR */ |
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88 | m8xx.tbscr = M8xx_TBSCR_REFA | M8xx_TBSCR_REFB | |
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89 | M8xx_TBSCR_TBF | M8xx_TBSCR_TBE; |
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90 | |
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91 | /* Initialize the Real-Time Clock Status and Control Register (RTCSC) */ |
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92 | m8xx.rtcsk = M8xx_UNLOCK_KEY; /* unlock RTCSC */ |
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93 | m8xx.rtcsc = 0x00C3; /* Default MBX and firmware value. */ |
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94 | |
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95 | /* Unlock other Real-Time Clock registers */ |
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96 | m8xx.rtck = M8xx_UNLOCK_KEY; /* unlock RTC */ |
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97 | m8xx.rtseck = M8xx_UNLOCK_KEY; /* unlock RTSEC */ |
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98 | m8xx.rtcalk = M8xx_UNLOCK_KEY; /* unlock RTCAL */ |
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99 | |
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100 | /* Initialize the Periodic Interrupt Status and Control Register (PISCR) */ |
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101 | m8xx.piscrk = M8xx_UNLOCK_KEY; /* unlock PISCR */ |
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102 | m8xx.piscr = 0x0083; /* Default MBX and firmware value. */ |
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103 | |
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104 | /* Initialize the System Clock and Reset Control Register (SCCR) |
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105 | * Set the clock sources and division factors: |
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106 | * Timebase Source is GCLK2 / 16 |
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107 | */ |
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108 | m8xx.sccrk = M8xx_UNLOCK_KEY; /* unlock SCCR */ |
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109 | m8xx.sccr |= 0x02000000; |
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110 | |
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111 | /* Unlock the timebase and decrementer registers. */ |
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112 | m8xx.tbk = M8xx_UNLOCK_KEY; |
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113 | /* |
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114 | * Initialize decrementer register to a large value to |
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115 | * guarantee that a decrementer interrupt will not be |
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116 | * generated before the kernel is fully initialized. |
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117 | */ |
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118 | r1 = 0x7FFFFFFF; |
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119 | _mtspr( M8xx_DEC, r1 ); |
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120 | |
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121 | /* Initialize the timebase register (TB is 64 bits) */ |
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122 | r1 = 0x00000000; |
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123 | _mtspr( M8xx_TBU_WR, r1 ); |
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124 | _mtspr( M8xx_TBL_WR, r1 ); |
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125 | } |
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126 | /* |
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127 | * further initialization (called from bsp_start) |
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128 | */ |
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129 | void cpu_init(void) |
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130 | { |
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131 | /* mmu initialization */ |
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132 | mmu_init(); |
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133 | } |
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