source: rtems/c/src/lib/libbsp/powerpc/tqm8xx/startup/cpuinit.c @ c499856

4.115
Last change on this file since c499856 was c499856, checked in by Chris Johns <chrisj@…>, on Mar 20, 2014 at 9:10:47 PM

Change all references of rtems.com to rtems.org.

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File size: 3.9 KB
Line 
1/*
2 *  cpuinit.c
3 *
4 *  TQM8xx initialization routines.
5 * derived from MBX8xx BSP
6 * adapted to TQM8xx by Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
7 *
8 *  Copyright (c) 1999, National Research Council of Canada
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.rtems.org/license/LICENSE.
13 */
14
15#include <bsp.h>
16#include <bsp/tqm.h>
17
18
19/*
20 *  Initialize TQM8xx
21 */
22void _InitTQM8xx (void)
23{
24  register uint32_t   r1;
25
26  /*
27   * Initialize the Instruction Support Control Register (ICTRL) to a
28   * an appropriate value for normal operation. A different value,
29   * such as 0x0, may be more appropriate for debugging.
30   */
31  r1 = 0x00000007;
32  _mtspr( M8xx_ICTRL, r1 );
33
34  /*
35   * Disable and invalidate the instruction and data caches.
36   */
37  r1 = M8xx_CACHE_CMD_DISABLE;
38  _mtspr( M8xx_IC_CST, r1 );
39  _isync;
40  r1 = M8xx_CACHE_CMD_UNLOCKALL;
41  _mtspr( M8xx_IC_CST, r1 );
42  _isync;
43  r1 = M8xx_CACHE_CMD_INVALIDATE;       /* invalidate all */
44  _mtspr( M8xx_IC_CST, r1 );
45  _isync;
46
47  r1 = M8xx_CACHE_CMD_DISABLE;
48  _mtspr( M8xx_DC_CST, r1 );
49  _isync;
50  r1 = M8xx_CACHE_CMD_UNLOCKALL;
51  _mtspr( M8xx_DC_CST, r1 );
52  _isync;
53  r1 = M8xx_CACHE_CMD_INVALIDATE;       /* invalidate all */
54  _mtspr( M8xx_DC_CST, r1 );
55  _isync;
56
57  /*
58   * Initialize the SIU Module Configuration Register (SIUMCR)
59   * m8xx.siumcr = 0x00602900, the default value.
60   */
61  m8xx.siumcr = M8xx_SIUMCR_EARP0 | M8xx_SIUMCR_DBGC3 | M8xx_SIUMCR_DBPC0 |
62                M8xx_SIUMCR_DPC | M8xx_SIUMCR_MLRC2 | M8xx_SIUMCR_SEME;
63
64  /*
65   * Initialize the System Protection Control Register (SYPCR).
66   * The SYPCR can only be written once after Reset.
67   *    - Enable bus monitor
68   *    - Disable software watchdog timer
69   * m8xx.sypcr = 0xFFFFFF88, the default MBX and firmware value.
70   */
71  m8xx.sypcr = M8xx_SYPCR_SWTC(0xFFFF) | M8xx_SYPCR_BMT(0xFF) |
72                M8xx_SYPCR_BME | M8xx_SYPCR_SWF;
73
74  /* Initialize the SIU Interrupt Edge Level Mask Register (SIEL) */
75  m8xx.siel = 0xAAAA0000;               /* Default MBX and firmware value. */
76
77  /* Initialize the Transfer Error Status Register (TESR) */
78  m8xx.tesr = 0xFFFFFFFF;               /* Default firmware value. */
79
80  /* Initialize the SDMA Configuration Register (SDCR) */
81  m8xx.sdcr = 0x00000001;               /* Default firmware value. */
82
83  /*
84   * Initialize the Timebase Status and Control Register (TBSCR)
85   * m8xx.tbscr = 0x00C3, default MBX and firmware value.
86   */
87  m8xx.tbscrk = M8xx_UNLOCK_KEY;        /* unlock TBSCR */
88  m8xx.tbscr = M8xx_TBSCR_REFA | M8xx_TBSCR_REFB |
89                M8xx_TBSCR_TBF | M8xx_TBSCR_TBE;
90
91  /* Initialize the Real-Time Clock Status and Control Register (RTCSC) */
92  m8xx.rtcsk = M8xx_UNLOCK_KEY;         /* unlock RTCSC */
93  m8xx.rtcsc = 0x00C3;                  /* Default MBX and firmware value. */
94
95  /* Unlock other Real-Time Clock registers */
96  m8xx.rtck = M8xx_UNLOCK_KEY;          /* unlock RTC */
97  m8xx.rtseck = M8xx_UNLOCK_KEY;        /* unlock RTSEC */
98  m8xx.rtcalk = M8xx_UNLOCK_KEY;        /* unlock RTCAL */
99
100  /* Initialize the Periodic Interrupt Status and Control Register (PISCR) */
101  m8xx.piscrk = M8xx_UNLOCK_KEY;        /* unlock PISCR */
102  m8xx.piscr = 0x0083;                  /* Default MBX and firmware value. */
103
104  /* Initialize the System Clock and Reset Control Register (SCCR)
105   * Set the clock sources and division factors:
106   *   Timebase Source is GCLK2 / 16
107   */
108  m8xx.sccrk = M8xx_UNLOCK_KEY;         /* unlock SCCR */
109  m8xx.sccr |= 0x02000000;
110
111  /* Unlock the timebase and decrementer registers. */
112  m8xx.tbk = M8xx_UNLOCK_KEY;
113  /*
114   * Initialize decrementer register to a large value to
115   * guarantee that a decrementer interrupt will not be
116   * generated before the kernel is fully initialized.
117   */
118  r1 = 0x7FFFFFFF;
119  _mtspr( M8xx_DEC, r1 );
120
121  /* Initialize the timebase register (TB is 64 bits) */
122  r1 = 0x00000000;
123  _mtspr( M8xx_TBU_WR, r1 );
124  _mtspr( M8xx_TBL_WR, r1 );
125}
126/*
127 * further initialization (called from bsp_start)
128 */
129void cpu_init(void)
130{
131  /* mmu initialization */
132  mmu_init();
133}
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