1 | /*===============================================================*\ |
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2 | | Project: RTEMS TQM8xx BSP | |
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3 | +-----------------------------------------------------------------+ |
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4 | | This file has been adapted to MPC8xx by | |
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5 | | Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> | |
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6 | | Copyright (c) 2008 | |
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7 | | Embedded Brains GmbH | |
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8 | | Obere Lagerstr. 30 | |
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9 | | D-82178 Puchheim | |
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10 | | Germany | |
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11 | | rtems@embedded-brains.de | |
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12 | | | |
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13 | | See the other copyright notice below for the original parts. | |
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14 | +-----------------------------------------------------------------+ |
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15 | | The license and distribution terms for this file may be | |
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16 | | found in the file LICENSE in this distribution or at | |
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17 | | | |
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18 | | http://www.rtems.org/license/LICENSE. | |
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19 | | | |
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20 | +-----------------------------------------------------------------+ |
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21 | | this file contains the console driver | |
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22 | \*===============================================================*/ |
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23 | /* derived from: generic MPC83xx BSP */ |
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24 | |
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25 | #include <rtems.h> |
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26 | #include <mpc8xx.h> |
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27 | |
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28 | #include <libcpu/powerpc-utility.h> |
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29 | #include <bsp/vectors.h> |
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30 | |
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31 | #include <bsp.h> |
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32 | #include <bsp/irq.h> |
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33 | #include <bsp/irq-generic.h> |
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34 | /* |
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35 | * functions to enable/disable a source at the SIU/CPM irq controller |
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36 | */ |
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37 | |
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38 | static rtems_status_code bsp_irq_disable_at_SIU(rtems_vector_number irqnum) |
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39 | { |
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40 | rtems_vector_number vecnum = irqnum - BSP_SIU_IRQ_LOWEST_OFFSET; |
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41 | m8xx.simask &= ~(1 << (31 - vecnum)); |
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42 | return RTEMS_SUCCESSFUL; |
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43 | } |
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44 | |
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45 | static rtems_status_code bsp_irq_enable_at_SIU(rtems_vector_number irqnum) |
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46 | { |
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47 | rtems_vector_number vecnum = irqnum - BSP_SIU_IRQ_LOWEST_OFFSET; |
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48 | m8xx.simask |= (1 << (31 - vecnum)); |
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49 | return RTEMS_SUCCESSFUL; |
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50 | } |
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51 | |
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52 | static rtems_status_code bsp_irq_disable_at_CPM(rtems_vector_number irqnum) |
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53 | { |
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54 | rtems_vector_number vecnum = irqnum - BSP_CPM_IRQ_LOWEST_OFFSET; |
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55 | m8xx.cimr &= ~(1 << (vecnum)); |
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56 | return RTEMS_SUCCESSFUL; |
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57 | } |
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58 | |
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59 | static rtems_status_code bsp_irq_enable_at_CPM(rtems_vector_number irqnum) |
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60 | { |
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61 | rtems_vector_number vecnum = irqnum - BSP_CPM_IRQ_LOWEST_OFFSET; |
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62 | m8xx.cimr |= (1 << (vecnum)); |
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63 | return RTEMS_SUCCESSFUL; |
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64 | } |
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65 | |
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66 | rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number irqnum) |
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67 | { |
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68 | if (BSP_IS_CPM_IRQ(irqnum)) { |
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69 | bsp_irq_enable_at_CPM(irqnum); |
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70 | return RTEMS_SUCCESSFUL; |
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71 | } |
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72 | else if (BSP_IS_SIU_IRQ(irqnum)) { |
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73 | bsp_irq_enable_at_SIU(irqnum); |
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74 | return RTEMS_SUCCESSFUL; |
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75 | } |
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76 | return RTEMS_INVALID_ID; |
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77 | } |
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78 | |
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79 | rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number irqnum) |
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80 | { |
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81 | if (BSP_IS_CPM_IRQ(irqnum)) { |
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82 | bsp_irq_disable_at_CPM(irqnum); |
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83 | return RTEMS_SUCCESSFUL; |
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84 | } |
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85 | else if (BSP_IS_SIU_IRQ(irqnum)) { |
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86 | bsp_irq_disable_at_SIU(irqnum); |
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87 | return RTEMS_SUCCESSFUL; |
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88 | } |
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89 | return RTEMS_INVALID_ID; |
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90 | } |
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91 | |
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92 | /* |
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93 | * IRQ Handler: this is called from the primary exception dispatcher |
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94 | */ |
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95 | static int BSP_irq_handle_at_cpm(void) |
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96 | { |
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97 | int32_t cpvecnum; |
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98 | uint32_t msr; |
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99 | |
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100 | /* Get vector number: write IACK=1, then read vectir */ |
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101 | m8xx.civr = 1; |
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102 | cpvecnum = (m8xx.civr >> 11) + BSP_CPM_IRQ_LOWEST_OFFSET; |
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103 | |
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104 | /* |
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105 | * Check the vector number, |
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106 | * enable exceptions and dispatch the handler. |
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107 | * NOTE: lower-prio interrupts are automatically masked in CPIC |
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108 | */ |
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109 | if (BSP_IS_CPM_IRQ(cpvecnum)) { |
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110 | /* Enable all interrupts */ |
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111 | msr = ppc_external_exceptions_enable(); |
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112 | /* Dispatch interrupt handlers */ |
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113 | bsp_interrupt_handler_dispatch(cpvecnum); |
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114 | /* Restore machine state */ |
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115 | ppc_external_exceptions_disable(msr); |
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116 | } |
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117 | else { |
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118 | /* not valid vector */ |
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119 | bsp_interrupt_handler_default(cpvecnum); |
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120 | } |
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121 | /* |
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122 | * clear "in-service" bit |
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123 | */ |
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124 | m8xx.cisr = 1 << (cpvecnum - BSP_CPM_IRQ_LOWEST_OFFSET); |
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125 | |
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126 | return 0; |
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127 | } |
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128 | |
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129 | static int BSP_irq_handle_at_siu( unsigned excNum) |
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130 | { |
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131 | int32_t sivecnum; |
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132 | uint32_t msr; |
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133 | bool is_cpm_irq; |
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134 | uint32_t simask_save; |
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135 | /* |
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136 | * check, if interrupt is pending |
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137 | * and repeat as long as valid interrupts are pending |
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138 | */ |
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139 | while (0 != (m8xx.simask & m8xx.sipend)) { |
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140 | /* Get vector number */ |
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141 | sivecnum = (m8xx.sivec >> 26); |
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142 | is_cpm_irq = (sivecnum == BSP_CPM_INTERRUPT); |
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143 | /* |
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144 | * Check the vector number, mask lower priority interrupts, enable |
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145 | * exceptions and dispatch the handler. |
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146 | */ |
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147 | if (BSP_IS_SIU_IRQ(sivecnum)) { |
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148 | simask_save = m8xx.simask; |
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149 | /* |
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150 | * if this is the CPM interrupt, mask lower prio interrupts at SIU |
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151 | * else mask lower and same priority interrupts |
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152 | */ |
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153 | m8xx.simask &= ~0 << (32 |
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154 | - sivecnum |
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155 | - ((is_cpm_irq) ? 1 : 0)); |
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156 | |
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157 | if (is_cpm_irq) { |
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158 | BSP_irq_handle_at_cpm(); |
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159 | } |
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160 | else { |
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161 | /* Enable all interrupts */ |
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162 | msr = ppc_external_exceptions_enable(); |
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163 | /* Dispatch interrupt handlers */ |
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164 | bsp_interrupt_handler_dispatch(sivecnum + BSP_SIU_IRQ_LOWEST_OFFSET); |
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165 | /* Restore machine state */ |
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166 | ppc_external_exceptions_disable(msr); |
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167 | /* |
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168 | * clear pending bit, if edge triggered interrupt input |
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169 | */ |
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170 | m8xx.sipend = 1 << (31 - sivecnum); |
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171 | } |
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172 | |
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173 | |
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174 | /* Restore initial masks */ |
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175 | m8xx.simask = simask_save; |
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176 | } else { |
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177 | /* not valid vector */ |
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178 | bsp_interrupt_handler_default(sivecnum); |
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179 | } |
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180 | } |
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181 | return 0; |
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182 | } |
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183 | |
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184 | /* |
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185 | * Activate the CPIC |
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186 | */ |
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187 | static rtems_status_code mpc8xx_cpic_initialize( void) |
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188 | { |
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189 | /* |
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190 | * mask off all interrupts |
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191 | */ |
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192 | m8xx.cimr = 0; |
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193 | /* |
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194 | * make sure CPIC request proper level at SIU interrupt controller |
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195 | */ |
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196 | m8xx.cicr = (0x00e41f80 | |
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197 | ((BSP_CPM_INTERRUPT/2) << 13)); |
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198 | /* |
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199 | * enable CPIC interrupt in SIU interrupt controller |
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200 | */ |
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201 | return bsp_irq_enable_at_SIU(BSP_CPM_INTERRUPT); |
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202 | } |
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203 | |
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204 | /* |
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205 | * Activate the SIU interrupt controller |
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206 | */ |
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207 | static rtems_status_code mpc8xx_siu_int_initialize( void) |
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208 | { |
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209 | /* |
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210 | * mask off all interrupts |
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211 | */ |
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212 | m8xx.simask = 0; |
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213 | |
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214 | return RTEMS_SUCCESSFUL; |
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215 | } |
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216 | |
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217 | static int mpc8xx_exception_handler(BSP_Exception_frame *frame, |
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218 | unsigned exception_number) |
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219 | { |
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220 | return BSP_irq_handle_at_siu(exception_number); |
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221 | } |
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222 | |
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223 | rtems_status_code bsp_interrupt_facility_initialize() |
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224 | { |
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225 | /* Install exception handler */ |
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226 | if (ppc_exc_set_handler(ASM_EXT_VECTOR, mpc8xx_exception_handler)) { |
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227 | return RTEMS_IO_ERROR; |
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228 | } |
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229 | /* Initialize the SIU interrupt controller */ |
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230 | if (mpc8xx_siu_int_initialize()) { |
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231 | return RTEMS_IO_ERROR; |
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232 | } |
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233 | /* Initialize the CPIC interrupt controller */ |
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234 | return mpc8xx_cpic_initialize(); |
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235 | } |
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