1 | /*===============================================================*\ |
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2 | | Project: RTEMS BSP support for TQ modules | |
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3 | +-----------------------------------------------------------------+ |
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4 | | Partially based on the code references which are named below. | |
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5 | | Adaptions, modifications, enhancements and any recent parts of | |
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6 | | the code are: | |
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7 | | Copyright (c) 2007 | |
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8 | | Embedded Brains GmbH | |
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9 | | Obere Lagerstr. 30 | |
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10 | | D-82178 Puchheim | |
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11 | | Germany | |
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12 | | rtems@embedded-brains.de | |
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13 | +-----------------------------------------------------------------+ |
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14 | | The license and distribution terms for this file may be | |
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15 | | found in the file LICENSE in this distribution or at | |
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16 | | | |
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17 | | http://www.rtems.org/license/LICENSE. | |
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18 | | | |
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19 | +-----------------------------------------------------------------+ |
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20 | | this file contains definitions to interact with TQC's | |
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21 | | processor modules | |
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22 | \*===============================================================*/ |
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23 | /* derived from mbx8xx BSP */ |
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24 | /* |
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25 | * MPC8xx Internal Memory Map |
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26 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) |
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27 | * |
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28 | * The I/O on the MPC860 is comprised of blocks of special registers |
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29 | * and the dual port ram for the Communication Processor Module. |
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30 | * Within this space are functional units such as the SIU, memory |
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31 | * controller, system timers, and other control functions. It is |
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32 | * a combination that I found difficult to separate into logical |
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33 | * functional files.....but anyone else is welcome to try. -- Dan |
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34 | */ |
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35 | #ifndef __IMMAP_8XX__ |
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36 | #define __IMMAP_8XX__ |
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37 | |
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38 | /* System configuration registers. |
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39 | */ |
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40 | typedef struct sys_conf { |
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41 | unsigned int sc_siumcr; |
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42 | unsigned int sc_sypcr; |
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43 | unsigned int sc_swt; |
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44 | char res1[2]; |
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45 | unsigned short sc_swsr; |
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46 | unsigned int sc_sipend; |
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47 | unsigned int sc_simask; |
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48 | unsigned int sc_siel; |
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49 | unsigned int sc_sivec; |
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50 | unsigned int sc_tesr; |
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51 | char res2[0xc]; |
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52 | unsigned int sc_sdcr; |
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53 | char res3[0x4c]; |
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54 | } sysconf8xx_t; |
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55 | |
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56 | /* PCMCIA configuration registers. |
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57 | */ |
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58 | typedef struct pcmcia_conf { |
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59 | unsigned int pcmc_pbr0; |
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60 | unsigned int pcmc_por0; |
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61 | unsigned int pcmc_pbr1; |
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62 | unsigned int pcmc_por1; |
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63 | unsigned int pcmc_pbr2; |
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64 | unsigned int pcmc_por2; |
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65 | unsigned int pcmc_pbr3; |
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66 | unsigned int pcmc_por3; |
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67 | unsigned int pcmc_pbr4; |
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68 | unsigned int pcmc_por4; |
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69 | unsigned int pcmc_pbr5; |
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70 | unsigned int pcmc_por5; |
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71 | unsigned int pcmc_pbr6; |
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72 | unsigned int pcmc_por6; |
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73 | unsigned int pcmc_pbr7; |
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74 | unsigned int pcmc_por7; |
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75 | char res1[0x20]; |
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76 | unsigned int pcmc_pgcra; |
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77 | unsigned int pcmc_pgcrb; |
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78 | unsigned int pcmc_pscr; |
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79 | char res2[4]; |
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80 | unsigned int pcmc_pipr; |
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81 | char res3[4]; |
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82 | unsigned int pcmc_per; |
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83 | char res4[4]; |
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84 | } pcmconf8xx_t; |
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85 | |
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86 | /* Memory controller registers. |
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87 | */ |
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88 | typedef struct mem_ctlr { |
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89 | unsigned int memc_br0; |
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90 | unsigned int memc_or0; |
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91 | unsigned int memc_br1; |
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92 | unsigned int memc_or1; |
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93 | unsigned int memc_br2; |
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94 | unsigned int memc_or2; |
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95 | unsigned int memc_br3; |
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96 | unsigned int memc_or3; |
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97 | unsigned int memc_br4; |
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98 | unsigned int memc_or4; |
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99 | unsigned int memc_br5; |
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100 | unsigned int memc_or5; |
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101 | unsigned int memc_br6; |
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102 | unsigned int memc_or6; |
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103 | unsigned int memc_br7; |
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104 | unsigned int memc_or7; |
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105 | char res1[0x24]; |
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106 | unsigned int memc_mar; |
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107 | unsigned int memc_mcr; |
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108 | char res2[4]; |
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109 | unsigned int memc_mamr; |
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110 | unsigned int memc_mbmr; |
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111 | unsigned short memc_mstat; |
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112 | unsigned short memc_mptpr; |
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113 | unsigned int memc_mdr; |
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114 | char res3[0x80]; |
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115 | } memctl8xx_t; |
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116 | |
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117 | /* System Integration Timers. |
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118 | */ |
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119 | typedef struct sys_int_timers { |
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120 | unsigned short sit_tbscr; |
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121 | unsigned int sit_tbreff0; |
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122 | unsigned int sit_tbreff1; |
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123 | char res1[0x14]; |
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124 | unsigned short sit_rtcsc; |
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125 | unsigned int sit_rtc; |
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126 | unsigned int sit_rtsec; |
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127 | unsigned int sit_rtcal; |
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128 | char res2[0x10]; |
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129 | unsigned short sit_piscr; |
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130 | char res3[2]; |
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131 | unsigned int sit_pitc; |
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132 | unsigned int sit_pitr; |
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133 | char res4[0x34]; |
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134 | } sit8xx_t; |
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135 | |
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136 | #define TBSCR_TBIRQ_MASK ((unsigned short)0xff00) |
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137 | #define TBSCR_REFA ((unsigned short)0x0080) |
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138 | #define TBSCR_REFB ((unsigned short)0x0040) |
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139 | #define TBSCR_REFAE ((unsigned short)0x0008) |
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140 | #define TBSCR_REFBE ((unsigned short)0x0004) |
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141 | #define TBSCR_TBF ((unsigned short)0x0002) |
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142 | #define TBSCR_TBE ((unsigned short)0x0001) |
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143 | |
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144 | #define RTCSC_RTCIRQ_MASK ((unsigned short)0xff00) |
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145 | #define RTCSC_SEC ((unsigned short)0x0080) |
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146 | #define RTCSC_ALR ((unsigned short)0x0040) |
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147 | #define RTCSC_38K ((unsigned short)0x0010) |
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148 | #define RTCSC_SIE ((unsigned short)0x0008) |
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149 | #define RTCSC_ALE ((unsigned short)0x0004) |
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150 | #define RTCSC_RTF ((unsigned short)0x0002) |
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151 | #define RTCSC_RTE ((unsigned short)0x0001) |
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152 | |
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153 | #define PISCR_PIRQ_MASK ((unsigned short)0xff00) |
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154 | #define PISCR_PS ((unsigned short)0x0080) |
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155 | #define PISCR_PIE ((unsigned short)0x0004) |
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156 | #define PISCR_PTF ((unsigned short)0x0002) |
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157 | #define PISCR_PTE ((unsigned short)0x0001) |
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158 | |
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159 | /* Clocks and Reset. |
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160 | */ |
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161 | typedef struct clk_and_reset { |
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162 | unsigned int car_sccr; |
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163 | unsigned int car_plprcr; |
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164 | unsigned int car_rsr; |
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165 | char res[0x74]; /* Reserved area */ |
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166 | } car8xx_t; |
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167 | |
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168 | /* System Integration Timers keys. |
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169 | */ |
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170 | typedef struct sitk { |
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171 | unsigned int sitk_tbscrk; |
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172 | unsigned int sitk_tbreff0k; |
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173 | unsigned int sitk_tbreff1k; |
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174 | unsigned int sitk_tbk; |
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175 | char res1[0x10]; |
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176 | unsigned int sitk_rtcsck; |
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177 | unsigned int sitk_rtck; |
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178 | unsigned int sitk_rtseck; |
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179 | unsigned int sitk_rtcalk; |
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180 | char res2[0x10]; |
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181 | unsigned int sitk_piscrk; |
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182 | unsigned int sitk_pitck; |
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183 | char res3[0x38]; |
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184 | } sitk8xx_t; |
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185 | |
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186 | /* Clocks and reset keys. |
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187 | */ |
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188 | typedef struct cark { |
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189 | unsigned int cark_sccrk; |
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190 | unsigned int cark_plprcrk; |
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191 | unsigned int cark_rsrk; |
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192 | char res[0x474]; |
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193 | } cark8xx_t; |
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194 | |
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195 | /* The key to unlock registers maintained by keep-alive power. |
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196 | */ |
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197 | #define KAPWR_KEY ((unsigned int)0x55ccaa33) |
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198 | |
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199 | /* LCD interface. MPC821 Only. |
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200 | */ |
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201 | typedef struct lcd { |
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202 | unsigned short lcd_lcolr[16]; |
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203 | char res[0x20]; |
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204 | unsigned int lcd_lccr; |
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205 | unsigned int lcd_lchcr; |
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206 | unsigned int lcd_lcvcr; |
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207 | char res2[4]; |
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208 | unsigned int lcd_lcfaa; |
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209 | unsigned int lcd_lcfba; |
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210 | char lcd_lcsr; |
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211 | char res3[0x7]; |
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212 | } lcd8xx_t; |
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213 | |
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214 | /* I2C |
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215 | */ |
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216 | typedef struct i2c { |
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217 | unsigned char i2c_i2mod; |
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218 | char res1[3]; |
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219 | unsigned char i2c_i2add; |
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220 | char res2[3]; |
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221 | unsigned char i2c_i2brg; |
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222 | char res3[3]; |
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223 | unsigned char i2c_i2com; |
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224 | char res4[3]; |
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225 | unsigned char i2c_i2cer; |
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226 | char res5[3]; |
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227 | unsigned char i2c_i2cmr; |
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228 | char res6[0x8b]; |
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229 | } i2c8xx_t; |
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230 | |
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231 | /* DMA control/status registers. |
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232 | */ |
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233 | typedef struct sdma_csr { |
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234 | char res1[4]; |
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235 | unsigned int sdma_sdar; |
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236 | unsigned char sdma_sdsr; |
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237 | char res3[3]; |
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238 | unsigned char sdma_sdmr; |
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239 | char res4[3]; |
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240 | unsigned char sdma_idsr1; |
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241 | char res5[3]; |
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242 | unsigned char sdma_idmr1; |
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243 | char res6[3]; |
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244 | unsigned char sdma_idsr2; |
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245 | char res7[3]; |
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246 | unsigned char sdma_idmr2; |
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247 | char res8[0x13]; |
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248 | } sdma8xx_t; |
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249 | |
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250 | /* Communication Processor Module Interrupt Controller. |
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251 | */ |
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252 | typedef struct cpm_ic { |
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253 | unsigned short cpic_civr; |
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254 | char res[0xe]; |
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255 | unsigned int cpic_cicr; |
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256 | unsigned int cpic_cipr; |
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257 | unsigned int cpic_cimr; |
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258 | unsigned int cpic_cisr; |
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259 | } cpic8xx_t; |
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260 | |
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261 | /* Input/Output Port control/status registers. |
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262 | */ |
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263 | typedef struct io_port { |
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264 | unsigned short iop_padir; |
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265 | unsigned short iop_papar; |
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266 | unsigned short iop_paodr; |
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267 | unsigned short iop_padat; |
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268 | char res1[8]; |
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269 | unsigned short iop_pcdir; |
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270 | unsigned short iop_pcpar; |
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271 | unsigned short iop_pcso; |
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272 | unsigned short iop_pcdat; |
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273 | unsigned short iop_pcint; |
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274 | char res2[6]; |
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275 | unsigned short iop_pddir; |
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276 | unsigned short iop_pdpar; |
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277 | char res3[2]; |
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278 | unsigned short iop_pddat; |
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279 | char res4[8]; |
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280 | } iop8xx_t; |
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281 | |
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282 | /* Communication Processor Module Timers |
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283 | */ |
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284 | typedef struct cpm_timers { |
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285 | unsigned short cpmt_tgcr; |
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286 | char res1[0xe]; |
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287 | unsigned short cpmt_tmr1; |
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288 | unsigned short cpmt_tmr2; |
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289 | unsigned short cpmt_trr1; |
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290 | unsigned short cpmt_trr2; |
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291 | unsigned short cpmt_tcr1; |
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292 | unsigned short cpmt_tcr2; |
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293 | unsigned short cpmt_tcn1; |
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294 | unsigned short cpmt_tcn2; |
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295 | unsigned short cpmt_tmr3; |
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296 | unsigned short cpmt_tmr4; |
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297 | unsigned short cpmt_trr3; |
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298 | unsigned short cpmt_trr4; |
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299 | unsigned short cpmt_tcr3; |
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300 | unsigned short cpmt_tcr4; |
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301 | unsigned short cpmt_tcn3; |
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302 | unsigned short cpmt_tcn4; |
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303 | unsigned short cpmt_ter1; |
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304 | unsigned short cpmt_ter2; |
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305 | unsigned short cpmt_ter3; |
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306 | unsigned short cpmt_ter4; |
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307 | char res2[8]; |
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308 | } cpmtimer8xx_t; |
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309 | |
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310 | /* Finally, the Communication Processor stuff..... |
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311 | */ |
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312 | typedef struct scc { /* Serial communication channels */ |
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313 | unsigned int scc_gsmrl; |
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314 | unsigned int scc_gsmrh; |
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315 | unsigned short scc_pmsr; |
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316 | char res1[2]; |
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317 | unsigned short scc_todr; |
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318 | unsigned short scc_dsr; |
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319 | unsigned short scc_scce; |
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320 | char res2[2]; |
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321 | unsigned short scc_sccm; |
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322 | char res3; |
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323 | unsigned char scc_sccs; |
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324 | char res4[8]; |
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325 | } scc_t; |
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326 | |
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327 | typedef struct smc { /* Serial management channels */ |
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328 | char res1[2]; |
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329 | unsigned short smc_smcmr; |
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330 | char res2[2]; |
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331 | unsigned char smc_smce; |
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332 | char res3[3]; |
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333 | unsigned char smc_smcm; |
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334 | char res4[5]; |
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335 | } smc_t; |
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336 | |
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337 | /* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but |
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338 | * it fits within the address space. |
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339 | */ |
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340 | typedef struct fec { |
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341 | unsigned int fec_addr_low; /* LS 32 bits of station address */ |
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342 | unsigned short fec_addr_high; /* MS 16 bits of address */ |
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343 | unsigned short res1; |
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344 | unsigned int fec_hash_table_high; |
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345 | unsigned int fec_hash_table_low; |
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346 | unsigned int fec_r_des_start; |
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347 | unsigned int fec_x_des_start; |
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348 | unsigned int fec_r_buff_size; |
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349 | unsigned int res2[9]; |
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350 | unsigned int fec_ecntrl; |
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351 | unsigned int fec_ievent; |
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352 | unsigned int fec_imask; |
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353 | unsigned int fec_ivec; |
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354 | unsigned int fec_r_des_active; |
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355 | unsigned int fec_x_des_active; |
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356 | unsigned int res3[10]; |
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357 | unsigned int fec_mii_data; |
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358 | unsigned int fec_mii_speed; |
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359 | unsigned int res4[17]; |
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360 | unsigned int fec_r_bound; |
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361 | unsigned int fec_r_fstart; |
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362 | unsigned int res5[6]; |
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363 | unsigned int fec_x_fstart; |
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364 | unsigned int res6[17]; |
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365 | unsigned int fec_fun_code; |
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366 | unsigned int res7[3]; |
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367 | unsigned int fec_r_cntrl; |
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368 | unsigned int fec_r_hash; |
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369 | unsigned int res8[14]; |
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370 | unsigned int fec_x_cntrl; |
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371 | unsigned int res9[0x1e]; |
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372 | } fec_t; |
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373 | |
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374 | typedef struct comm_proc { |
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375 | /* General control and status registers. |
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376 | */ |
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377 | unsigned short cp_cpcr; |
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378 | char res1[2]; |
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379 | unsigned short cp_rccr; |
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380 | char res2[6]; |
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381 | unsigned short cp_cpmcr1; |
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382 | unsigned short cp_cpmcr2; |
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383 | unsigned short cp_cpmcr3; |
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384 | unsigned short cp_cpmcr4; |
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385 | char res3[2]; |
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386 | unsigned short cp_rter; |
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387 | char res4[2]; |
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388 | unsigned short cp_rtmr; |
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389 | char res5[0x14]; |
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390 | |
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391 | /* Baud rate generators. |
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392 | */ |
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393 | unsigned int cp_brgc1; |
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394 | unsigned int cp_brgc2; |
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395 | unsigned int cp_brgc3; |
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396 | unsigned int cp_brgc4; |
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397 | |
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398 | /* Serial Communication Channels. |
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399 | */ |
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400 | scc_t cp_scc[4]; |
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401 | |
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402 | /* Serial Management Channels. |
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403 | */ |
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404 | smc_t cp_smc[2]; |
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405 | |
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406 | /* Serial Peripheral Interface. |
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407 | */ |
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408 | unsigned short cp_spmode; |
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409 | char res6[4]; |
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410 | unsigned char cp_spie; |
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411 | char res7[3]; |
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412 | unsigned char cp_spim; |
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413 | char res8[2]; |
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414 | unsigned char cp_spcom; |
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415 | char res9[2]; |
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416 | |
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417 | /* Parallel Interface Port. |
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418 | */ |
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419 | char res10[2]; |
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420 | unsigned short cp_pipc; |
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421 | char res11[2]; |
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422 | unsigned short cp_ptpr; |
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423 | unsigned int cp_pbdir; |
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424 | unsigned int cp_pbpar; |
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425 | char res12[2]; |
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426 | unsigned short cp_pbodr; |
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427 | unsigned int cp_pbdat; |
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428 | char res13[0x18]; |
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429 | |
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430 | /* Serial Interface and Time Slot Assignment. |
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431 | */ |
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432 | unsigned int cp_simode; |
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433 | unsigned char cp_sigmr; |
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434 | char res14; |
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435 | unsigned char cp_sistr; |
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436 | unsigned char cp_sicmr; |
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437 | char res15[4]; |
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438 | unsigned int cp_sicr; |
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439 | unsigned int cp_sirp; |
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440 | char res16[0x10c]; |
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441 | unsigned char cp_siram[0x200]; |
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442 | |
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443 | /* The fast ethernet controller is not really part of the CPM, |
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444 | * but it resides in the address space. |
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445 | */ |
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446 | fec_t cp_fec; |
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447 | char res18[0x1000]; |
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448 | |
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449 | /* Dual Ported RAM follows. |
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450 | * There are many different formats for this memory area |
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451 | * depending upon the devices used and options chosen. |
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452 | */ |
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453 | unsigned char cp_dpmem[0x1000]; /* BD / Data / ucode */ |
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454 | unsigned char res19[0xc00]; |
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455 | unsigned char cp_dparam[0x400]; /* Parameter RAM */ |
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456 | } cpm8xx_t; |
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457 | |
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458 | /* Internal memory map. |
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459 | */ |
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460 | typedef struct immap { |
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461 | sysconf8xx_t im_siu_conf; /* SIU Configuration */ |
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462 | pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */ |
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463 | memctl8xx_t im_memctl; /* Memory Controller */ |
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464 | sit8xx_t im_sit; /* System integration timers */ |
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465 | car8xx_t im_clkrst; /* Clocks and reset */ |
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466 | sitk8xx_t im_sitk; /* Sys int timer keys */ |
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467 | cark8xx_t im_clkrstk; /* Clocks and reset keys */ |
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468 | lcd8xx_t im_lcd; /* LCD (821 only) */ |
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469 | i2c8xx_t im_i2c; /* I2C control/status */ |
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470 | sdma8xx_t im_sdma; /* SDMA control/status */ |
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471 | cpic8xx_t im_cpic; /* CPM Interrupt Controller */ |
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472 | iop8xx_t im_ioport; /* IO Port control/status */ |
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473 | cpmtimer8xx_t im_cpmtimer; /* CPM timers */ |
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474 | cpm8xx_t im_cpm; /* Communication processor */ |
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475 | } immap_t; |
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476 | |
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477 | #endif /* __IMMAP_8XX__ */ |
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