source: rtems/c/src/lib/libbsp/powerpc/t32mppc/startup/bspstart.c @ 7078a00b

Last change on this file since 7078a00b was 7078a00b, checked in by Sebastian Huber <sebastian.huber@…>, on Nov 8, 2017 at 12:13:32 PM

bsp/t32mppc: Use fixed exception handlers

  • Property mode set to 100644
File size: 2.8 KB
Line 
1/*
2 * Copyright (c) 2012, 2017 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Dornierstr. 4
6 *  82178 Puchheim
7 *  Germany
8 *  <rtems@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.org/license/LICENSE.
13 */
14
15#include <rtems/config.h>
16#include <rtems/counter.h>
17
18#include <bsp.h>
19#include <bsp/vectors.h>
20#include <bsp/bootcard.h>
21#include <bsp/irq-generic.h>
22#include <bsp/linker-symbols.h>
23
24LINKER_SYMBOL(bsp_exc_vector_base);
25
26/*
27 * Configuration parameter for clock driver.  The Trace32 PowerPC simulator has
28 * an odd decrementer frequency.  The time base frequency is one tick per
29 * instruction.  The decrementer frequency is one tick per ten instructions.
30 * The clock driver assumes that the time base and decrementer frequencies are
31 * equal.  For now we simulate processor that issues 10000000 instructions per
32 * second.
33 */
34uint32_t bsp_time_base_frequency = 10000000;
35
36void BSP_panic(char *s)
37{
38  rtems_interrupt_level level;
39
40  rtems_interrupt_local_disable(level);
41  (void) level;
42
43  printk("%s PANIC %s\n", rtems_get_version_string(), s);
44
45  while (1) {
46    /* Do nothing */
47  }
48}
49
50void _BSP_Fatal_error(unsigned n)
51{
52  rtems_interrupt_level level;
53
54  rtems_interrupt_local_disable(level);
55  (void) level;
56
57  printk("%s PANIC ERROR %u\n", rtems_get_version_string(), n);
58
59  while (1) {
60    /* Do nothing */
61  }
62}
63
64#define MTIVPR(base) \
65  __asm__ volatile ("mtivpr %0" : : "r" (base))
66
67#define VECTOR_TABLE_ENTRY_SIZE 16
68
69#define MTIVOR(vec, offset) \
70  do { \
71    __asm__ volatile ("mtspr " RTEMS_XSTRING(vec) ", %0" : : "r" (offset)); \
72    offset += VECTOR_TABLE_ENTRY_SIZE; \
73  } while (0)
74
75static void t32mppc_initialize_exceptions(void *interrupt_stack_begin)
76{
77  uintptr_t addr;
78
79  ppc_exc_initialize_interrupt_stack(
80    (uintptr_t) interrupt_stack_begin,
81    rtems_configuration_get_interrupt_stack_size()
82  );
83
84  addr = (uintptr_t) bsp_exc_vector_base;
85  MTIVPR(addr);
86  MTIVOR(BOOKE_IVOR0,  addr);
87  MTIVOR(BOOKE_IVOR1,  addr);
88  MTIVOR(BOOKE_IVOR2,  addr);
89  MTIVOR(BOOKE_IVOR3,  addr);
90  MTIVOR(BOOKE_IVOR4,  addr);
91  MTIVOR(BOOKE_IVOR5,  addr);
92  MTIVOR(BOOKE_IVOR6,  addr);
93  MTIVOR(BOOKE_IVOR7,  addr);
94  MTIVOR(BOOKE_IVOR8,  addr);
95  MTIVOR(BOOKE_IVOR9,  addr);
96  MTIVOR(BOOKE_IVOR10, addr);
97  MTIVOR(BOOKE_IVOR11, addr);
98  MTIVOR(BOOKE_IVOR12, addr);
99  MTIVOR(BOOKE_IVOR13, addr);
100  MTIVOR(BOOKE_IVOR14, addr);
101  MTIVOR(BOOKE_IVOR15, addr);
102  MTIVOR(BOOKE_IVOR32, addr);
103  MTIVOR(BOOKE_IVOR33, addr);
104  MTIVOR(BOOKE_IVOR34, addr);
105  MTIVOR(BOOKE_IVOR35, addr);
106}
107
108void bsp_start(void)
109{
110  get_ppc_cpu_type();
111  get_ppc_cpu_revision();
112
113  rtems_counter_initialize_converter(bsp_time_base_frequency);
114
115  t32mppc_initialize_exceptions(bsp_section_work_begin);
116  bsp_interrupt_initialize();
117}
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