1 | /* |
---|
2 | * This file contains the interrupt handler assembly code for the PowerPC |
---|
3 | * implementation of RTEMS. It is #included from cpu_asm.s. |
---|
4 | * |
---|
5 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
---|
6 | * |
---|
7 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
---|
8 | * |
---|
9 | * To anyone who acknowledges that this file is provided "AS IS" |
---|
10 | * without any express or implied warranty: |
---|
11 | * permission to use, copy, modify, and distribute this file |
---|
12 | * for any purpose is hereby granted without fee, provided that |
---|
13 | * the above copyright notice and this notice appears in all |
---|
14 | * copies, and that the name of i-cubed limited not be used in |
---|
15 | * advertising or publicity pertaining to distribution of the |
---|
16 | * software without specific, written prior permission. |
---|
17 | * i-cubed limited makes no representations about the suitability |
---|
18 | * of this software for any purpose. |
---|
19 | * |
---|
20 | * $Id$ |
---|
21 | */ |
---|
22 | |
---|
23 | /* |
---|
24 | * FIXME: this file is bsp dependent. |
---|
25 | */ |
---|
26 | #include <bspopts.h> |
---|
27 | |
---|
28 | /* void __ISR_Handler() |
---|
29 | * |
---|
30 | * This routine provides the RTEMS interrupt management. |
---|
31 | * The vector number is in r0. R0 has already been stacked. |
---|
32 | * |
---|
33 | */ |
---|
34 | PUBLIC_VAR (_CPU_IRQ_info ) |
---|
35 | |
---|
36 | /* Finish off the interrupt frame */ |
---|
37 | stw r2, IP_2(r1) |
---|
38 | stw r3, IP_3(r1) |
---|
39 | stw r4, IP_4(r1) |
---|
40 | stw r5, IP_5(r1) |
---|
41 | stw r6, IP_6(r1) |
---|
42 | stw r7, IP_7(r1) |
---|
43 | stw r8, IP_8(r1) |
---|
44 | stw r9, IP_9(r1) |
---|
45 | stw r10, IP_10(r1) |
---|
46 | stw r11, IP_11(r1) |
---|
47 | stw r12, IP_12(r1) |
---|
48 | stw r13, IP_13(r1) |
---|
49 | stmw r28, IP_28(r1) |
---|
50 | mfcr r5 |
---|
51 | mfctr r6 |
---|
52 | mfxer r7 |
---|
53 | mflr r8 |
---|
54 | MFPC (r9) |
---|
55 | MFMSR (r10) |
---|
56 | /* Establish addressing */ |
---|
57 | #if (PPC_USE_SPRG) |
---|
58 | mfspr r11, sprg3 |
---|
59 | #else |
---|
60 | lis r11,_CPU_IRQ_info@ha |
---|
61 | addi r11,r11,_CPU_IRQ_info@l |
---|
62 | #endif |
---|
63 | #if ( PPC_USE_DATA_CACHE ) |
---|
64 | dcbt r0, r11 |
---|
65 | #endif |
---|
66 | stw r5, IP_CR(r1) |
---|
67 | stw r6, IP_CTR(r1) |
---|
68 | stw r7, IP_XER(r1) |
---|
69 | stw r8, IP_LR(r1) |
---|
70 | stw r9, IP_PC(r1) |
---|
71 | stw r10, IP_MSR(r1) |
---|
72 | |
---|
73 | lwz r30, Vector_table(r11) |
---|
74 | slwi r4,r0,2 |
---|
75 | lwz r28, Nest_level(r11) |
---|
76 | add r4, r4, r30 |
---|
77 | |
---|
78 | lwz r30, 0(r28) |
---|
79 | mr r3, r0 |
---|
80 | lwz r31, Stack(r11) |
---|
81 | /* |
---|
82 | * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) |
---|
83 | * if ( _ISR_Nest_level == 0 ) |
---|
84 | * switch to software interrupt stack |
---|
85 | * #endif |
---|
86 | */ |
---|
87 | /* Switch stacks, here we must prevent ALL interrupts */ |
---|
88 | #if (PPC_USE_SPRG) |
---|
89 | mfmsr r5 |
---|
90 | mfspr r6, sprg2 |
---|
91 | #else |
---|
92 | lwz r6,msr_initial(r11) |
---|
93 | lis r5,~PPC_MSR_DISABLE_MASK@ha |
---|
94 | ori r5,r5,~PPC_MSR_DISABLE_MASK@l |
---|
95 | and r6,r6,r5 |
---|
96 | mfmsr r5 |
---|
97 | #endif |
---|
98 | mtmsr r6 |
---|
99 | cmpwi r30, 0 |
---|
100 | lwz r29, Disable_level(r11) |
---|
101 | subf r31,r1,r31 |
---|
102 | bne LABEL (nested) |
---|
103 | stwux r1,r1,r31 |
---|
104 | LABEL (nested): |
---|
105 | /* |
---|
106 | * _ISR_Nest_level++; |
---|
107 | */ |
---|
108 | lwz r31, 0(r29) |
---|
109 | addi r30,r30,1 |
---|
110 | stw r30,0(r28) |
---|
111 | /* From here on out, interrupts can be re-enabled. RTEMS |
---|
112 | * convention says not. |
---|
113 | */ |
---|
114 | lwz r4,0(r4) |
---|
115 | /* |
---|
116 | * _Thread_Dispatch_disable_level++; |
---|
117 | */ |
---|
118 | addi r31,r31,1 |
---|
119 | stw r31, 0(r29) |
---|
120 | /* SCE 980217 |
---|
121 | * |
---|
122 | * We need address translation ON when we call our ISR routine |
---|
123 | |
---|
124 | mtmsr r5 |
---|
125 | |
---|
126 | */ |
---|
127 | |
---|
128 | /* |
---|
129 | * (*_ISR_Vector_table[ vector ])( vector ); |
---|
130 | */ |
---|
131 | #if (PPC_ABI == PPC_ABI_POWEROPEN) |
---|
132 | lwz r6,0(r4) |
---|
133 | lwz r2,4(r4) |
---|
134 | mtlr r6 |
---|
135 | lwz r11,8(r4) |
---|
136 | #endif |
---|
137 | #if (PPC_ABI == PPC_ABI_SVR4 || PPC_ABI == PPC_ABI_EABI) |
---|
138 | mtlr r4 |
---|
139 | lwz r2, Default_r2(r11) |
---|
140 | lwz r13, Default_r13(r11) |
---|
141 | #lwz r2, 0(r2) |
---|
142 | #lwz r13, 0(r13) |
---|
143 | #endif |
---|
144 | mr r4,r1 |
---|
145 | blrl |
---|
146 | /* NOP marker for debuggers */ |
---|
147 | or r6,r6,r6 |
---|
148 | |
---|
149 | /* We must re-disable the interrupts */ |
---|
150 | #if (PPC_USE_SPRG) |
---|
151 | mfspr r11, sprg3 |
---|
152 | mfspr r0, sprg2 |
---|
153 | #else |
---|
154 | lis r11,_CPU_IRQ_info@ha |
---|
155 | addi r11,r11,_CPU_IRQ_info@l |
---|
156 | lwz r0,msr_initial(r11) |
---|
157 | lis r30,~PPC_MSR_DISABLE_MASK@ha |
---|
158 | ori r30,r30,~PPC_MSR_DISABLE_MASK@l |
---|
159 | and r0,r0,r30 |
---|
160 | #endif |
---|
161 | mtmsr r0 |
---|
162 | lwz r30, 0(r28) |
---|
163 | lwz r31, 0(r29) |
---|
164 | |
---|
165 | /* |
---|
166 | * if (--Thread_Dispatch_disable,--_ISR_Nest_level) |
---|
167 | * goto easy_exit; |
---|
168 | */ |
---|
169 | addi r30, r30, -1 |
---|
170 | cmpwi r30, 0 |
---|
171 | addi r31, r31, -1 |
---|
172 | stw r30, 0(r28) |
---|
173 | stw r31, 0(r29) |
---|
174 | bne LABEL (easy_exit) |
---|
175 | cmpwi r31, 0 |
---|
176 | |
---|
177 | lwz r30, Switch_necessary(r11) |
---|
178 | |
---|
179 | /* |
---|
180 | * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) |
---|
181 | * restore stack |
---|
182 | * #endif |
---|
183 | */ |
---|
184 | lwz r1,0(r1) |
---|
185 | bne LABEL (easy_exit) |
---|
186 | lwz r30, 0(r30) |
---|
187 | lwz r31, Signal(r11) |
---|
188 | |
---|
189 | /* |
---|
190 | * if ( _Context_Switch_necessary ) |
---|
191 | * goto switch |
---|
192 | */ |
---|
193 | cmpwi r30, 0 |
---|
194 | lwz r28, 0(r31) |
---|
195 | li r6,0 |
---|
196 | bne LABEL (switch) |
---|
197 | /* |
---|
198 | * if ( !_ISR_Signals_to_thread_executing ) |
---|
199 | * goto easy_exit |
---|
200 | * _ISR_Signals_to_thread_executing = 0; |
---|
201 | */ |
---|
202 | cmpwi r28, 0 |
---|
203 | beq LABEL (easy_exit) |
---|
204 | |
---|
205 | /* |
---|
206 | * switch: |
---|
207 | * call _Thread_Dispatch() or prepare to return to _ISR_Dispatch |
---|
208 | */ |
---|
209 | LABEL (switch): |
---|
210 | stw r6, 0(r31) |
---|
211 | /* Re-enable interrupts */ |
---|
212 | lwz r0, IP_MSR(r1) |
---|
213 | #if (PPC_ABI == PPC_ABI_POWEROPEN) |
---|
214 | lwz r2, Dispatch_r2(r11) |
---|
215 | #else |
---|
216 | /* R2 and R13 still hold their values from the last call */ |
---|
217 | #endif |
---|
218 | mtmsr r0 |
---|
219 | bl SYM (_Thread_Dispatch) |
---|
220 | /* NOP marker for debuggers */ |
---|
221 | or r6,r6,r6 |
---|
222 | /* |
---|
223 | * prepare to get out of interrupt |
---|
224 | */ |
---|
225 | /* Re-disable IRQs */ |
---|
226 | #if (PPC_USE_SPRG) |
---|
227 | mfspr r0, sprg2 |
---|
228 | #else |
---|
229 | lis r11,_CPU_IRQ_info@ha |
---|
230 | addi r11,r11,_CPU_IRQ_info@l |
---|
231 | lwz r0,msr_initial(r11) |
---|
232 | lis r5,~PPC_MSR_DISABLE_MASK@ha |
---|
233 | ori r5,r5,~PPC_MSR_DISABLE_MASK@l |
---|
234 | and r0,r0,r5 |
---|
235 | #endif |
---|
236 | mtmsr r0 |
---|
237 | |
---|
238 | /* |
---|
239 | * easy_exit: |
---|
240 | * prepare to get out of interrupt |
---|
241 | * return from interrupt |
---|
242 | */ |
---|
243 | LABEL (easy_exit): |
---|
244 | lwz r5, IP_CR(r1) |
---|
245 | lwz r6, IP_CTR(r1) |
---|
246 | lwz r7, IP_XER(r1) |
---|
247 | lwz r8, IP_LR(r1) |
---|
248 | lwz r9, IP_PC(r1) |
---|
249 | lwz r10, IP_MSR(r1) |
---|
250 | mtcrf 255,r5 |
---|
251 | mtctr r6 |
---|
252 | mtxer r7 |
---|
253 | mtlr r8 |
---|
254 | MTPC (r9) |
---|
255 | MTMSR (r10) |
---|
256 | lwz r0, IP_0(r1) |
---|
257 | lwz r2, IP_2(r1) |
---|
258 | lwz r3, IP_3(r1) |
---|
259 | lwz r4, IP_4(r1) |
---|
260 | lwz r5, IP_5(r1) |
---|
261 | lwz r6, IP_6(r1) |
---|
262 | lwz r7, IP_7(r1) |
---|
263 | lwz r8, IP_8(r1) |
---|
264 | lwz r9, IP_9(r1) |
---|
265 | lwz r10, IP_10(r1) |
---|
266 | lwz r11, IP_11(r1) |
---|
267 | lwz r12, IP_12(r1) |
---|
268 | lwz r13, IP_13(r1) |
---|
269 | lmw r28, IP_28(r1) |
---|
270 | lwz r1, 0(r1) |
---|