Context Navigation

cpu_asm.S @ 466e590

4.104.114.84.95

Last change on this file since 466e590 was 39fb164, checked in by Joel Sherrill <joel.sherrill@…>, on 11/20/01 at 18:48:43

2001-11-20 Ralf Corsepius <corsepiu@…>

support/new_exception_processing/Makefile.am, support/old_exception_processing/Makefile.am, support/old_exception_processing/cpu_asm.S, support/old_exception_processing/irq_stub.S: Modified to reflect old versus new exception processing being a per BSP option.
support/new_exception_processing/c_isr.inl, support/new_exception_processing/cpu.h, support/old_exception_processing/c_isr.inl, support/old_exception_processing/cpu.h, support/old_exception_processing/ppc_offs.h: Removed.

Property mode set to 100644

File size: 13.7 KB

Line
1
2	/* cpu_asm.s 1.1 - 95/12/04
3	*
4	* This file contains the assembly code for the PowerPC implementation
5	* of RTEMS.
6	*
7	* Author: Andrew Bray <andy@i-cubed.co.uk>
8	*
9	* COPYRIGHT (c) 1995 by i-cubed ltd.
10	*
11	* To anyone who acknowledges that this file is provided "AS IS"
12	* without any express or implied warranty:
13	* permission to use, copy, modify, and distribute this file
14	* for any purpose is hereby granted without fee, provided that
15	* the above copyright notice and this notice appears in all
16	* copies, and that the name of i-cubed limited not be used in
17	* advertising or publicity pertaining to distribution of the
18	* software without specific, written prior permission.
19	* i-cubed limited makes no representations about the suitability
20	* of this software for any purpose.
21	*
22	* Derived from c/src/exec/cpu/no_cpu/cpu_asm.c:
23	*
24	* COPYRIGHT (c) 1989-1997.
25	* On-Line Applications Research Corporation (OAR).
26	*
27	* The license and distribution terms for this file may in
28	* the file LICENSE in this distribution or at
29	* http://www.OARcorp.com/rtems/license.html.
30	*
31	* $Id$
32	*/
33
34	/*
35	* FIXME: This file is bsp-dependent.
36	*/
37	#include <bspopts.h>
38
39	#include <asm.h>
40	#include <rtems/score/ppc_offs.h>
41
42	BEGIN_CODE
43	/*
44	* _CPU_Context_save_fp_context
45	*
46	* This routine is responsible for saving the FP context
47	* at *fp_context_ptr. If the point to load the FP context
48	* from is changed then the pointer is modified by this routine.
49	*
50	* Sometimes a macro implementation of this is in cpu.h which dereferences
51	* the ** and a similarly named routine in this file is passed something
52	* like a (Context_Control_fp *). The general rule on making this decision
53	* is to avoid writing assembly language.
54	*/
55
56	ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
57	PUBLIC_PROC (_CPU_Context_save_fp)
58	PROC (_CPU_Context_save_fp):
59	#if (PPC_HAS_FPU == 1)
60	lwz r3, 0(r3)
61	#if (PPC_HAS_DOUBLE == 1)
62	stfd f0, FP_0(r3)
63	stfd f1, FP_1(r3)
64	stfd f2, FP_2(r3)
65	stfd f3, FP_3(r3)
66	stfd f4, FP_4(r3)
67	stfd f5, FP_5(r3)
68	stfd f6, FP_6(r3)
69	stfd f7, FP_7(r3)
70	stfd f8, FP_8(r3)
71	stfd f9, FP_9(r3)
72	stfd f10, FP_10(r3)
73	stfd f11, FP_11(r3)
74	stfd f12, FP_12(r3)
75	stfd f13, FP_13(r3)
76	stfd f14, FP_14(r3)
77	stfd f15, FP_15(r3)
78	stfd f16, FP_16(r3)
79	stfd f17, FP_17(r3)
80	stfd f18, FP_18(r3)
81	stfd f19, FP_19(r3)
82	stfd f20, FP_20(r3)
83	stfd f21, FP_21(r3)
84	stfd f22, FP_22(r3)
85	stfd f23, FP_23(r3)
86	stfd f24, FP_24(r3)
87	stfd f25, FP_25(r3)
88	stfd f26, FP_26(r3)
89	stfd f27, FP_27(r3)
90	stfd f28, FP_28(r3)
91	stfd f29, FP_29(r3)
92	stfd f30, FP_30(r3)
93	stfd f31, FP_31(r3)
94	mffs f2
95	stfd f2, FP_FPSCR(r3)
96	#else
97	stfs f0, FP_0(r3)
98	stfs f1, FP_1(r3)
99	stfs f2, FP_2(r3)
100	stfs f3, FP_3(r3)
101	stfs f4, FP_4(r3)
102	stfs f5, FP_5(r3)
103	stfs f6, FP_6(r3)
104	stfs f7, FP_7(r3)
105	stfs f8, FP_8(r3)
106	stfs f9, FP_9(r3)
107	stfs f10, FP_10(r3)
108	stfs f11, FP_11(r3)
109	stfs f12, FP_12(r3)
110	stfs f13, FP_13(r3)
111	stfs f14, FP_14(r3)
112	stfs f15, FP_15(r3)
113	stfs f16, FP_16(r3)
114	stfs f17, FP_17(r3)
115	stfs f18, FP_18(r3)
116	stfs f19, FP_19(r3)
117	stfs f20, FP_20(r3)
118	stfs f21, FP_21(r3)
119	stfs f22, FP_22(r3)
120	stfs f23, FP_23(r3)
121	stfs f24, FP_24(r3)
122	stfs f25, FP_25(r3)
123	stfs f26, FP_26(r3)
124	stfs f27, FP_27(r3)
125	stfs f28, FP_28(r3)
126	stfs f29, FP_29(r3)
127	stfs f30, FP_30(r3)
128	stfs f31, FP_31(r3)
129	mffs f2
130	stfs f2, FP_FPSCR(r3)
131	#endif
132	#endif
133	blr
134
135	/*
136	* _CPU_Context_restore_fp_context
137	*
138	* This routine is responsible for restoring the FP context
139	* at *fp_context_ptr. If the point to load the FP context
140	* from is changed then the pointer is modified by this routine.
141	*
142	* Sometimes a macro implementation of this is in cpu.h which dereferences
143	* the ** and a similarly named routine in this file is passed something
144	* like a (Context_Control_fp *). The general rule on making this decision
145	* is to avoid writing assembly language.
146	*/
147
148	ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
149	PUBLIC_PROC (_CPU_Context_restore_fp)
150	PROC (_CPU_Context_restore_fp):
151	#if (PPC_HAS_FPU == 1)
152	lwz r3, 0(r3)
153	#if (PPC_HAS_DOUBLE == 1)
154	lfd f2, FP_FPSCR(r3)
155	mtfsf 255, f2
156	lfd f0, FP_0(r3)
157	lfd f1, FP_1(r3)
158	lfd f2, FP_2(r3)
159	lfd f3, FP_3(r3)
160	lfd f4, FP_4(r3)
161	lfd f5, FP_5(r3)
162	lfd f6, FP_6(r3)
163	lfd f7, FP_7(r3)
164	lfd f8, FP_8(r3)
165	lfd f9, FP_9(r3)
166	lfd f10, FP_10(r3)
167	lfd f11, FP_11(r3)
168	lfd f12, FP_12(r3)
169	lfd f13, FP_13(r3)
170	lfd f14, FP_14(r3)
171	lfd f15, FP_15(r3)
172	lfd f16, FP_16(r3)
173	lfd f17, FP_17(r3)
174	lfd f18, FP_18(r3)
175	lfd f19, FP_19(r3)
176	lfd f20, FP_20(r3)
177	lfd f21, FP_21(r3)
178	lfd f22, FP_22(r3)
179	lfd f23, FP_23(r3)
180	lfd f24, FP_24(r3)
181	lfd f25, FP_25(r3)
182	lfd f26, FP_26(r3)
183	lfd f27, FP_27(r3)
184	lfd f28, FP_28(r3)
185	lfd f29, FP_29(r3)
186	lfd f30, FP_30(r3)
187	lfd f31, FP_31(r3)
188	#else
189	lfs f2, FP_FPSCR(r3)
190	mtfsf 255, f2
191	lfs f0, FP_0(r3)
192	lfs f1, FP_1(r3)
193	lfs f2, FP_2(r3)
194	lfs f3, FP_3(r3)
195	lfs f4, FP_4(r3)
196	lfs f5, FP_5(r3)
197	lfs f6, FP_6(r3)
198	lfs f7, FP_7(r3)
199	lfs f8, FP_8(r3)
200	lfs f9, FP_9(r3)
201	lfs f10, FP_10(r3)
202	lfs f11, FP_11(r3)
203	lfs f12, FP_12(r3)
204	lfs f13, FP_13(r3)
205	lfs f14, FP_14(r3)
206	lfs f15, FP_15(r3)
207	lfs f16, FP_16(r3)
208	lfs f17, FP_17(r3)
209	lfs f18, FP_18(r3)
210	lfs f19, FP_19(r3)
211	lfs f20, FP_20(r3)
212	lfs f21, FP_21(r3)
213	lfs f22, FP_22(r3)
214	lfs f23, FP_23(r3)
215	lfs f24, FP_24(r3)
216	lfs f25, FP_25(r3)
217	lfs f26, FP_26(r3)
218	lfs f27, FP_27(r3)
219	lfs f28, FP_28(r3)
220	lfs f29, FP_29(r3)
221	lfs f30, FP_30(r3)
222	lfs f31, FP_31(r3)
223	#endif
224	#endif
225	blr
226
227
228	/* _CPU_Context_switch
229	*
230	* This routine performs a normal non-FP context switch.
231	*/
232	ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
233	PUBLIC_PROC (_CPU_Context_switch)
234	PROC (_CPU_Context_switch):
235	sync
236	isync
237	#if (PPC_CACHE_ALIGNMENT == 4) /* No cache */
238	stw r1, GP_1(r3)
239	lwz r1, GP_1(r4)
240	stw r2, GP_2(r3)
241	lwz r2, GP_2(r4)
242	#if (PPC_USE_MULTIPLE == 1)
243	stmw r13, GP_13(r3)
244	lmw r13, GP_13(r4)
245	#else
246	stw r13, GP_13(r3)
247	lwz r13, GP_13(r4)
248	stw r14, GP_14(r3)
249	lwz r14, GP_14(r4)
250	stw r15, GP_15(r3)
251	lwz r15, GP_15(r4)
252	stw r16, GP_16(r3)
253	lwz r16, GP_16(r4)
254	stw r17, GP_17(r3)
255	lwz r17, GP_17(r4)
256	stw r18, GP_18(r3)
257	lwz r18, GP_18(r4)
258	stw r19, GP_19(r3)
259	lwz r19, GP_19(r4)
260	stw r20, GP_20(r3)
261	lwz r20, GP_20(r4)
262	stw r21, GP_21(r3)
263	lwz r21, GP_21(r4)
264	stw r22, GP_22(r3)
265	lwz r22, GP_22(r4)
266	stw r23, GP_23(r3)
267	lwz r23, GP_23(r4)
268	stw r24, GP_24(r3)
269	lwz r24, GP_24(r4)
270	stw r25, GP_25(r3)
271	lwz r25, GP_25(r4)
272	stw r26, GP_26(r3)
273	lwz r26, GP_26(r4)
274	stw r27, GP_27(r3)
275	lwz r27, GP_27(r4)
276	stw r28, GP_28(r3)
277	lwz r28, GP_28(r4)
278	stw r29, GP_29(r3)
279	lwz r29, GP_29(r4)
280	stw r30, GP_30(r3)
281	lwz r30, GP_30(r4)
282	stw r31, GP_31(r3)
283	lwz r31, GP_31(r4)
284	#endif
285	mfcr r5
286	stw r5, GP_CR(r3)
287	lwz r5, GP_CR(r4)
288	mflr r6
289	mtcrf 255, r5
290	stw r6, GP_PC(r3)
291	lwz r6, GP_PC(r4)
292	mfmsr r7
293	mtlr r6
294	stw r7, GP_MSR(r3)
295	lwz r7, GP_MSR(r4)
296	mtmsr r7
297	#endif
298	#if (PPC_CACHE_ALIGNMENT == 16)
299	/* This assumes that all the registers are in the given order */
300	li r5, 16
301	addi r3,r3,-4
302	#if ( PPC_USE_DATA_CACHE )
303	dcbz r5, r3
304	#endif
305	stw r1, GP_1+4(r3)
306	stw r2, GP_2+4(r3)
307	#if (PPC_USE_MULTIPLE == 1)
308	addi r3, r3, GP_14+4
309	#if ( PPC_USE_DATA_CACHE )
310	dcbz r5, r3
311	#endif
312
313	addi r3, r3, GP_18-GP_14
314	#if ( PPC_USE_DATA_CACHE )
315	dcbz r5, r3
316	#endif
317	addi r3, r3, GP_22-GP_18
318	#if ( PPC_USE_DATA_CACHE )
319	dcbz r5, r3
320	#endif
321	addi r3, r3, GP_26-GP_22
322	#if ( PPC_USE_DATA_CACHE )
323	dcbz r5, r3
324	#endif
325	stmw r13, GP_13-GP_26(r3)
326	#else
327	stw r13, GP_13+4(r3)
328	stwu r14, GP_14+4(r3)
329	#if ( PPC_USE_DATA_CACHE )
330	dcbz r5, r3
331	#endif
332	stw r15, GP_15-GP_14(r3)
333	stw r16, GP_16-GP_14(r3)
334	stw r17, GP_17-GP_14(r3)
335	stwu r18, GP_18-GP_14(r3)
336	#if ( PPC_USE_DATA_CACHE )
337	dcbz r5, r3
338	#endif
339	stw r19, GP_19-GP_18(r3)
340	stw r20, GP_20-GP_18(r3)
341	stw r21, GP_21-GP_18(r3)
342	stwu r22, GP_22-GP_18(r3)
343	#if ( PPC_USE_DATA_CACHE )
344	dcbz r5, r3
345	#endif
346	stw r23, GP_23-GP_22(r3)
347	stw r24, GP_24-GP_22(r3)
348	stw r25, GP_25-GP_22(r3)
349	stwu r26, GP_26-GP_22(r3)
350	#if ( PPC_USE_DATA_CACHE )
351	dcbz r5, r3
352	#endif
353	stw r27, GP_27-GP_26(r3)
354	stw r28, GP_28-GP_26(r3)
355	stw r29, GP_29-GP_26(r3)
356	stw r30, GP_30-GP_26(r3)
357	stw r31, GP_31-GP_26(r3)
358	#endif
359	#if ( PPC_USE_DATA_CACHE )
360	dcbt r0, r4
361	#endif
362	mfcr r6
363	stw r6, GP_CR-GP_26(r3)
364	mflr r7
365	stw r7, GP_PC-GP_26(r3)
366	mfmsr r8
367	stw r8, GP_MSR-GP_26(r3)
368
369	#if ( PPC_USE_DATA_CACHE )
370	dcbt r5, r4
371	#endif
372	lwz r1, GP_1(r4)
373	lwz r2, GP_2(r4)
374	#if (PPC_USE_MULTIPLE == 1)
375	addi r4, r4, GP_15
376	#if ( PPC_USE_DATA_CACHE )
377	dcbt r5, r4
378	#endif
379	addi r4, r4, GP_19-GP_15
380	#if ( PPC_USE_DATA_CACHE )
381	dcbt r5, r4
382	#endif
383	addi r4, r4, GP_23-GP_19
384	#if ( PPC_USE_DATA_CACHE )
385	dcbt r5, r4
386	#endif
387	addi r4, r4, GP_27-GP_23
388	#if ( PPC_USE_DATA_CACHE )
389	dcbt r5, r4
390	#endif
391	lmw r13, GP_13-GP_27(r4)
392	#else
393	lwz r13, GP_13(r4)
394	lwz r14, GP_14(r4)
395	lwzu r15, GP_15(r4)
396	#if ( PPC_USE_DATA_CACHE )
397	dcbt r5, r4
398	#endif
399	lwz r16, GP_16-GP_15(r4)
400	lwz r17, GP_17-GP_15(r4)
401	lwz r18, GP_18-GP_15(r4)
402	lwzu r19, GP_19-GP_15(r4)
403	#if ( PPC_USE_DATA_CACHE )
404	dcbt r5, r4
405	#endif
406	lwz r20, GP_20-GP_19(r4)
407	lwz r21, GP_21-GP_19(r4)
408	lwz r22, GP_22-GP_19(r4)
409	lwzu r23, GP_23-GP_19(r4)
410	#if ( PPC_USE_DATA_CACHE )
411	dcbt r5, r4
412	#endif
413	lwz r24, GP_24-GP_23(r4)
414	lwz r25, GP_25-GP_23(r4)
415	lwz r26, GP_26-GP_23(r4)
416	lwzu r27, GP_27-GP_23(r4)
417	#if ( PPC_USE_DATA_CACHE )
418	dcbt r5, r4
419	#endif
420	lwz r28, GP_28-GP_27(r4)
421	lwz r29, GP_29-GP_27(r4)
422	lwz r30, GP_30-GP_27(r4)
423	lwz r31, GP_31-GP_27(r4)
424	#endif
425	lwz r6, GP_CR-GP_27(r4)
426	lwz r7, GP_PC-GP_27(r4)
427	lwz r8, GP_MSR-GP_27(r4)
428	mtcrf 255, r6
429	mtlr r7
430	mtmsr r8
431	#endif
432	#if (PPC_CACHE_ALIGNMENT == 32)
433	/* This assumes that all the registers are in the given order */
434	li r5, 32
435	addi r3,r3,-4
436	#if ( PPC_USE_DATA_CACHE )
437	dcbz r5, r3
438	#endif
439	stw r1, GP_1+4(r3)
440	stw r2, GP_2+4(r3)
441	#if (PPC_USE_MULTIPLE == 1)
442	addi r3, r3, GP_18+4
443	#if ( PPC_USE_DATA_CACHE )
444	dcbz r5, r3
445	#endif
446	stmw r13, GP_13-GP_18(r3)
447	#else
448	stw r13, GP_13+4(r3)
449	stw r14, GP_14+4(r3)
450	stw r15, GP_15+4(r3)
451	stw r16, GP_16+4(r3)
452	stw r17, GP_17+4(r3)
453	stwu r18, GP_18+4(r3)
454	#if ( PPC_USE_DATA_CACHE )
455	dcbz r5, r3
456	#endif
457	stw r19, GP_19-GP_18(r3)
458	stw r20, GP_20-GP_18(r3)
459	stw r21, GP_21-GP_18(r3)
460	stw r22, GP_22-GP_18(r3)
461	stw r23, GP_23-GP_18(r3)
462	stw r24, GP_24-GP_18(r3)
463	stw r25, GP_25-GP_18(r3)
464	stw r26, GP_26-GP_18(r3)
465	stw r27, GP_27-GP_18(r3)
466	stw r28, GP_28-GP_18(r3)
467	stw r29, GP_29-GP_18(r3)
468	stw r30, GP_30-GP_18(r3)
469	stw r31, GP_31-GP_18(r3)
470	#endif
471	#if ( PPC_USE_DATA_CACHE )
472	dcbt r0, r4
473	#endif
474	mfcr r6
475	stw r6, GP_CR-GP_18(r3)
476	mflr r7
477	stw r7, GP_PC-GP_18(r3)
478	mfmsr r8
479	stw r8, GP_MSR-GP_18(r3)
480
481	#if ( PPC_USE_DATA_CACHE )
482	dcbt r5, r4
483	#endif
484	lwz r1, GP_1(r4)
485	lwz r2, GP_2(r4)
486	#if (PPC_USE_MULTIPLE == 1)
487	addi r4, r4, GP_19
488	#if ( PPC_USE_DATA_CACHE )
489	dcbt r5, r4
490	#endif
491	lmw r13, GP_13-GP_19(r4)
492	#else
493	lwz r13, GP_13(r4)
494	lwz r14, GP_14(r4)
495	lwz r15, GP_15(r4)
496	lwz r16, GP_16(r4)
497	lwz r17, GP_17(r4)
498	lwz r18, GP_18(r4)
499	lwzu r19, GP_19(r4)
500	#if ( PPC_USE_DATA_CACHE )
501	dcbt r5, r4
502	#endif
503	lwz r20, GP_20-GP_19(r4)
504	lwz r21, GP_21-GP_19(r4)
505	lwz r22, GP_22-GP_19(r4)
506	lwz r23, GP_23-GP_19(r4)
507	lwz r24, GP_24-GP_19(r4)
508	lwz r25, GP_25-GP_19(r4)
509	lwz r26, GP_26-GP_19(r4)
510	lwz r27, GP_27-GP_19(r4)
511	lwz r28, GP_28-GP_19(r4)
512	lwz r29, GP_29-GP_19(r4)
513	lwz r30, GP_30-GP_19(r4)
514	lwz r31, GP_31-GP_19(r4)
515	#endif
516	lwz r6, GP_CR-GP_19(r4)
517	lwz r7, GP_PC-GP_19(r4)
518	lwz r8, GP_MSR-GP_19(r4)
519	mtcrf 255, r6
520	mtlr r7
521	mtmsr r8
522	#endif
523	blr
524
525	/*
526	* _CPU_Context_restore
527	*
528	* This routine is generallu used only to restart self in an
529	* efficient manner. It may simply be a label in _CPU_Context_switch.
530	*
531	* NOTE: May be unnecessary to reload some registers.
532	*/
533	/*
534	* ACB: Don't worry about cache optimisation here - this is not THAT critical.
535	*/
536	ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
537	PUBLIC_PROC (_CPU_Context_restore)
538	PROC (_CPU_Context_restore):
539	lwz r5, GP_CR(r3)
540	lwz r6, GP_PC(r3)
541	lwz r7, GP_MSR(r3)
542	mtcrf 255, r5
543	mtlr r6
544	mtmsr r7
545	lwz r1, GP_1(r3)
546	lwz r2, GP_2(r3)
547	#if (PPC_USE_MULTIPLE == 1)
548	lmw r13, GP_13(r3)
549	#else
550	lwz r13, GP_13(r3)
551	lwz r14, GP_14(r3)
552	lwz r15, GP_15(r3)
553	lwz r16, GP_16(r3)
554	lwz r17, GP_17(r3)
555	lwz r18, GP_18(r3)
556	lwz r19, GP_19(r3)
557	lwz r20, GP_20(r3)
558	lwz r21, GP_21(r3)
559	lwz r22, GP_22(r3)
560	lwz r23, GP_23(r3)
561	lwz r24, GP_24(r3)
562	lwz r25, GP_25(r3)
563	lwz r26, GP_26(r3)
564	lwz r27, GP_27(r3)
565	lwz r28, GP_28(r3)
566	lwz r29, GP_29(r3)
567	lwz r30, GP_30(r3)
568	lwz r31, GP_31(r3)
569	#endif
570
571	blr
572
573	/* Individual interrupt prologues look like this:
574	* #if (PPC_ABI == PPC_ABI_POWEROPEN \|\| PPC_ABI == PPC_ABI_GCC27)
575	* #if (PPC_HAS_FPU)
576	* stwu r1, -(204 + 188 + IP_END)(r1)
577	* #else
578	* stwu r1, -(20*4 + IP_END)(r1)
579	* #endif
580	* #else
581	* stwu r1, -(IP_END)(r1)
582	* #endif
583	* stw r0, IP_0(r1)
584	*
585	* li r0, vectornum
586	* b PROC (_ISR_Handler{,C})
587	*/
588
589	/* void __ISR_Handler()
590	*
591	* This routine provides the RTEMS interrupt management.
592	* The vector number is in r0. R0 has already been stacked.
593	*
594	*/
595	ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
596	PUBLIC_PROC (_ISR_Handler)
597	PROC (_ISR_Handler):
598	#define LABEL(x) x
599	/* XXX ??
600	#define MTSAVE(x) mtspr sprg0, x
601	#define MFSAVE(x) mfspr x, sprg0
602	*/
603	#define MTPC(x) mtspr srr0, x
604	#define MFPC(x) mfspr x, srr0
605	#define MTMSR(x) mtspr srr1, x
606	#define MFMSR(x) mfspr x, srr1
607
608	#include "irq_stub.S"
609	rfi
610
611	#if (PPC_HAS_RFCI == 1)
612	/* void __ISR_HandlerC()
613	*
614	* This routine provides the RTEMS interrupt management.
615	* For critical interrupts
616	*
617	*/
618	ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
619	PUBLIC_PROC (_ISR_HandlerC)
620	PROC (_ISR_HandlerC):
621	#undef LABEL
622	#undef MTSAVE
623	#undef MFSAVE
624	#undef MTPC
625	#undef MFPC
626	#undef MTMSR
627	#undef MFMSR
628	#define LABEL(x) x##_C
629	/* XXX??
630	#define MTSAVE(x) mtspr sprg1, x
631	#define MFSAVE(x) mfspr x, sprg1
632	*/
633	#define MTPC(x) mtspr srr2, x
634	#define MFPC(x) mfspr x, srr2
635	#define MTMSR(x) mtspr srr3, x
636	#define MFMSR(x) mfspr x, srr3
637	#include "irq_stub.S"
638	rfci
639	#endif
640
641	/* PowerOpen descriptors for indirect function calls.
642	*/
643
644	#if (PPC_ABI == PPC_ABI_POWEROPEN)
645	DESCRIPTOR (_CPU_Context_save_fp)
646	DESCRIPTOR (_CPU_Context_restore_fp)
647	DESCRIPTOR (_CPU_Context_switch)
648	DESCRIPTOR (_CPU_Context_restore)
649	DESCRIPTOR (_ISR_Handler)
650	#if (PPC_HAS_RFCI == 1)
651	DESCRIPTOR (_ISR_HandlerC)
652	#endif
653	#endif

Note: See TracBrowser for help on using the repository browser.

Download in other formats:

Original Format