| 1 | |
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| 2 | /* cpu_asm.s 1.1 - 95/12/04 |
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| 3 | * |
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| 4 | * This file contains the assembly code for the PowerPC implementation |
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| 5 | * of RTEMS. |
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| 6 | * |
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| 7 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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| 8 | * |
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| 9 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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| 10 | * |
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| 11 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 12 | * without any express or implied warranty: |
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| 13 | * permission to use, copy, modify, and distribute this file |
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| 14 | * for any purpose is hereby granted without fee, provided that |
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| 15 | * the above copyright notice and this notice appears in all |
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| 16 | * copies, and that the name of i-cubed limited not be used in |
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| 17 | * advertising or publicity pertaining to distribution of the |
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| 18 | * software without specific, written prior permission. |
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| 19 | * i-cubed limited makes no representations about the suitability |
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| 20 | * of this software for any purpose. |
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| 21 | * |
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| 22 | * Derived from c/src/exec/cpu/no_cpu/cpu_asm.c: |
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| 23 | * |
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| 24 | * COPYRIGHT (c) 1989-1997. |
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| 25 | * On-Line Applications Research Corporation (OAR). |
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| 26 | * |
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| 27 | * The license and distribution terms for this file may in |
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| 28 | * the file LICENSE in this distribution or at |
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| 29 | * http://www.rtems.com/license/LICENSE. |
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| 30 | * |
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| 31 | * $Id$ |
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| 32 | */ |
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| 33 | |
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| 34 | /* |
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| 35 | * FIXME: This file is bsp-dependent. |
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| 36 | */ |
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| 37 | #include <bspopts.h> |
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| 38 | |
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| 39 | #include <rtems/asm.h> |
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| 40 | #include <rtems/score/ppc_offs.h> |
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| 41 | |
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| 42 | BEGIN_CODE |
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| 43 | /* |
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| 44 | * _CPU_Context_save_fp_context |
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| 45 | * |
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| 46 | * This routine is responsible for saving the FP context |
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| 47 | * at *fp_context_ptr. If the point to load the FP context |
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| 48 | * from is changed then the pointer is modified by this routine. |
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| 49 | * |
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| 50 | * Sometimes a macro implementation of this is in cpu.h which dereferences |
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| 51 | * the ** and a similarly named routine in this file is passed something |
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| 52 | * like a (Context_Control_fp *). The general rule on making this decision |
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| 53 | * is to avoid writing assembly language. |
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| 54 | */ |
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| 55 | |
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| 56 | ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) |
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| 57 | PUBLIC_PROC (_CPU_Context_save_fp) |
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| 58 | PROC (_CPU_Context_save_fp): |
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| 59 | #if (PPC_HAS_FPU == 1) |
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| 60 | lwz r3, 0(r3) |
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| 61 | #if (PPC_HAS_DOUBLE == 1) |
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| 62 | stfd f0, FP_0(r3) |
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| 63 | stfd f1, FP_1(r3) |
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| 64 | stfd f2, FP_2(r3) |
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| 65 | stfd f3, FP_3(r3) |
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| 66 | stfd f4, FP_4(r3) |
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| 67 | stfd f5, FP_5(r3) |
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| 68 | stfd f6, FP_6(r3) |
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| 69 | stfd f7, FP_7(r3) |
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| 70 | stfd f8, FP_8(r3) |
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| 71 | stfd f9, FP_9(r3) |
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| 72 | stfd f10, FP_10(r3) |
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| 73 | stfd f11, FP_11(r3) |
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| 74 | stfd f12, FP_12(r3) |
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| 75 | stfd f13, FP_13(r3) |
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| 76 | stfd f14, FP_14(r3) |
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| 77 | stfd f15, FP_15(r3) |
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| 78 | stfd f16, FP_16(r3) |
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| 79 | stfd f17, FP_17(r3) |
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| 80 | stfd f18, FP_18(r3) |
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| 81 | stfd f19, FP_19(r3) |
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| 82 | stfd f20, FP_20(r3) |
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| 83 | stfd f21, FP_21(r3) |
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| 84 | stfd f22, FP_22(r3) |
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| 85 | stfd f23, FP_23(r3) |
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| 86 | stfd f24, FP_24(r3) |
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| 87 | stfd f25, FP_25(r3) |
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| 88 | stfd f26, FP_26(r3) |
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| 89 | stfd f27, FP_27(r3) |
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| 90 | stfd f28, FP_28(r3) |
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| 91 | stfd f29, FP_29(r3) |
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| 92 | stfd f30, FP_30(r3) |
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| 93 | stfd f31, FP_31(r3) |
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| 94 | mffs f2 |
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| 95 | stfd f2, FP_FPSCR(r3) |
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| 96 | #else |
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| 97 | stfs f0, FP_0(r3) |
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| 98 | stfs f1, FP_1(r3) |
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| 99 | stfs f2, FP_2(r3) |
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| 100 | stfs f3, FP_3(r3) |
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| 101 | stfs f4, FP_4(r3) |
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| 102 | stfs f5, FP_5(r3) |
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| 103 | stfs f6, FP_6(r3) |
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| 104 | stfs f7, FP_7(r3) |
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| 105 | stfs f8, FP_8(r3) |
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| 106 | stfs f9, FP_9(r3) |
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| 107 | stfs f10, FP_10(r3) |
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| 108 | stfs f11, FP_11(r3) |
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| 109 | stfs f12, FP_12(r3) |
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| 110 | stfs f13, FP_13(r3) |
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| 111 | stfs f14, FP_14(r3) |
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| 112 | stfs f15, FP_15(r3) |
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| 113 | stfs f16, FP_16(r3) |
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| 114 | stfs f17, FP_17(r3) |
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| 115 | stfs f18, FP_18(r3) |
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| 116 | stfs f19, FP_19(r3) |
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| 117 | stfs f20, FP_20(r3) |
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| 118 | stfs f21, FP_21(r3) |
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| 119 | stfs f22, FP_22(r3) |
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| 120 | stfs f23, FP_23(r3) |
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| 121 | stfs f24, FP_24(r3) |
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| 122 | stfs f25, FP_25(r3) |
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| 123 | stfs f26, FP_26(r3) |
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| 124 | stfs f27, FP_27(r3) |
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| 125 | stfs f28, FP_28(r3) |
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| 126 | stfs f29, FP_29(r3) |
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| 127 | stfs f30, FP_30(r3) |
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| 128 | stfs f31, FP_31(r3) |
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| 129 | mffs f2 |
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| 130 | stfs f2, FP_FPSCR(r3) |
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| 131 | #endif |
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| 132 | #endif |
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| 133 | blr |
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| 134 | |
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| 135 | /* |
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| 136 | * _CPU_Context_restore_fp_context |
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| 137 | * |
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| 138 | * This routine is responsible for restoring the FP context |
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| 139 | * at *fp_context_ptr. If the point to load the FP context |
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| 140 | * from is changed then the pointer is modified by this routine. |
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| 141 | * |
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| 142 | * Sometimes a macro implementation of this is in cpu.h which dereferences |
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| 143 | * the ** and a similarly named routine in this file is passed something |
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| 144 | * like a (Context_Control_fp *). The general rule on making this decision |
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| 145 | * is to avoid writing assembly language. |
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| 146 | */ |
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| 147 | |
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| 148 | ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) |
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| 149 | PUBLIC_PROC (_CPU_Context_restore_fp) |
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| 150 | PROC (_CPU_Context_restore_fp): |
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| 151 | #if (PPC_HAS_FPU == 1) |
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| 152 | lwz r3, 0(r3) |
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| 153 | #if (PPC_HAS_DOUBLE == 1) |
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| 154 | lfd f2, FP_FPSCR(r3) |
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| 155 | mtfsf 255, f2 |
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| 156 | lfd f0, FP_0(r3) |
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| 157 | lfd f1, FP_1(r3) |
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| 158 | lfd f2, FP_2(r3) |
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| 159 | lfd f3, FP_3(r3) |
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| 160 | lfd f4, FP_4(r3) |
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| 161 | lfd f5, FP_5(r3) |
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| 162 | lfd f6, FP_6(r3) |
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| 163 | lfd f7, FP_7(r3) |
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| 164 | lfd f8, FP_8(r3) |
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| 165 | lfd f9, FP_9(r3) |
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| 166 | lfd f10, FP_10(r3) |
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| 167 | lfd f11, FP_11(r3) |
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| 168 | lfd f12, FP_12(r3) |
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| 169 | lfd f13, FP_13(r3) |
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| 170 | lfd f14, FP_14(r3) |
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| 171 | lfd f15, FP_15(r3) |
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| 172 | lfd f16, FP_16(r3) |
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| 173 | lfd f17, FP_17(r3) |
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| 174 | lfd f18, FP_18(r3) |
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| 175 | lfd f19, FP_19(r3) |
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| 176 | lfd f20, FP_20(r3) |
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| 177 | lfd f21, FP_21(r3) |
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| 178 | lfd f22, FP_22(r3) |
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| 179 | lfd f23, FP_23(r3) |
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| 180 | lfd f24, FP_24(r3) |
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| 181 | lfd f25, FP_25(r3) |
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| 182 | lfd f26, FP_26(r3) |
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| 183 | lfd f27, FP_27(r3) |
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| 184 | lfd f28, FP_28(r3) |
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| 185 | lfd f29, FP_29(r3) |
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| 186 | lfd f30, FP_30(r3) |
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| 187 | lfd f31, FP_31(r3) |
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| 188 | #else |
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| 189 | lfs f2, FP_FPSCR(r3) |
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| 190 | mtfsf 255, f2 |
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| 191 | lfs f0, FP_0(r3) |
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| 192 | lfs f1, FP_1(r3) |
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| 193 | lfs f2, FP_2(r3) |
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| 194 | lfs f3, FP_3(r3) |
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| 195 | lfs f4, FP_4(r3) |
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| 196 | lfs f5, FP_5(r3) |
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| 197 | lfs f6, FP_6(r3) |
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| 198 | lfs f7, FP_7(r3) |
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| 199 | lfs f8, FP_8(r3) |
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| 200 | lfs f9, FP_9(r3) |
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| 201 | lfs f10, FP_10(r3) |
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| 202 | lfs f11, FP_11(r3) |
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| 203 | lfs f12, FP_12(r3) |
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| 204 | lfs f13, FP_13(r3) |
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| 205 | lfs f14, FP_14(r3) |
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| 206 | lfs f15, FP_15(r3) |
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| 207 | lfs f16, FP_16(r3) |
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| 208 | lfs f17, FP_17(r3) |
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| 209 | lfs f18, FP_18(r3) |
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| 210 | lfs f19, FP_19(r3) |
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| 211 | lfs f20, FP_20(r3) |
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| 212 | lfs f21, FP_21(r3) |
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| 213 | lfs f22, FP_22(r3) |
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| 214 | lfs f23, FP_23(r3) |
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| 215 | lfs f24, FP_24(r3) |
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| 216 | lfs f25, FP_25(r3) |
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| 217 | lfs f26, FP_26(r3) |
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| 218 | lfs f27, FP_27(r3) |
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| 219 | lfs f28, FP_28(r3) |
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| 220 | lfs f29, FP_29(r3) |
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| 221 | lfs f30, FP_30(r3) |
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| 222 | lfs f31, FP_31(r3) |
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| 223 | #endif |
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| 224 | #endif |
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| 225 | blr |
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| 226 | |
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| 227 | /* _CPU_Context_switch |
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| 228 | * |
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| 229 | * This routine performs a normal non-FP context switch. |
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| 230 | */ |
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| 231 | ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) |
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| 232 | PUBLIC_PROC (_CPU_Context_switch) |
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| 233 | PROC (_CPU_Context_switch): |
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| 234 | sync |
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| 235 | isync |
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| 236 | #if (PPC_CACHE_ALIGNMENT == 4) /* No cache */ |
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| 237 | stw r1, GP_1(r3) |
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| 238 | lwz r1, GP_1(r4) |
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| 239 | stw r2, GP_2(r3) |
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| 240 | lwz r2, GP_2(r4) |
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| 241 | #if (PPC_USE_MULTIPLE == 1) |
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| 242 | stmw r13, GP_13(r3) |
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| 243 | lmw r13, GP_13(r4) |
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| 244 | #else |
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| 245 | stw r13, GP_13(r3) |
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| 246 | lwz r13, GP_13(r4) |
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| 247 | stw r14, GP_14(r3) |
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| 248 | lwz r14, GP_14(r4) |
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| 249 | stw r15, GP_15(r3) |
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| 250 | lwz r15, GP_15(r4) |
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| 251 | stw r16, GP_16(r3) |
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| 252 | lwz r16, GP_16(r4) |
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| 253 | stw r17, GP_17(r3) |
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| 254 | lwz r17, GP_17(r4) |
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| 255 | stw r18, GP_18(r3) |
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| 256 | lwz r18, GP_18(r4) |
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| 257 | stw r19, GP_19(r3) |
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| 258 | lwz r19, GP_19(r4) |
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| 259 | stw r20, GP_20(r3) |
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| 260 | lwz r20, GP_20(r4) |
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| 261 | stw r21, GP_21(r3) |
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| 262 | lwz r21, GP_21(r4) |
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| 263 | stw r22, GP_22(r3) |
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| 264 | lwz r22, GP_22(r4) |
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| 265 | stw r23, GP_23(r3) |
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| 266 | lwz r23, GP_23(r4) |
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| 267 | stw r24, GP_24(r3) |
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| 268 | lwz r24, GP_24(r4) |
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| 269 | stw r25, GP_25(r3) |
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| 270 | lwz r25, GP_25(r4) |
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| 271 | stw r26, GP_26(r3) |
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| 272 | lwz r26, GP_26(r4) |
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| 273 | stw r27, GP_27(r3) |
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| 274 | lwz r27, GP_27(r4) |
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| 275 | stw r28, GP_28(r3) |
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| 276 | lwz r28, GP_28(r4) |
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| 277 | stw r29, GP_29(r3) |
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| 278 | lwz r29, GP_29(r4) |
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| 279 | stw r30, GP_30(r3) |
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| 280 | lwz r30, GP_30(r4) |
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| 281 | stw r31, GP_31(r3) |
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| 282 | lwz r31, GP_31(r4) |
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| 283 | #endif |
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| 284 | mfcr r5 |
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| 285 | stw r5, GP_CR(r3) |
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| 286 | lwz r5, GP_CR(r4) |
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| 287 | mflr r6 |
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| 288 | mtcrf 255, r5 |
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| 289 | stw r6, GP_PC(r3) |
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| 290 | lwz r6, GP_PC(r4) |
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| 291 | mfmsr r7 |
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| 292 | mtlr r6 |
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| 293 | stw r7, GP_MSR(r3) |
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| 294 | lwz r7, GP_MSR(r4) |
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| 295 | mtmsr r7 |
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| 296 | #endif |
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| 297 | #if (PPC_CACHE_ALIGNMENT == 16) |
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| 298 | /* This assumes that all the registers are in the given order */ |
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| 299 | li r5, 16 |
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| 300 | addi r3,r3,-4 |
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| 301 | #if ( PPC_USE_DATA_CACHE ) |
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| 302 | dcbz r5, r3 |
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| 303 | #endif |
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| 304 | stw r1, GP_1+4(r3) |
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| 305 | stw r2, GP_2+4(r3) |
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| 306 | #if (PPC_USE_MULTIPLE == 1) |
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| 307 | addi r3, r3, GP_14+4 |
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| 308 | #if ( PPC_USE_DATA_CACHE ) |
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| 309 | dcbz r5, r3 |
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| 310 | #endif |
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| 311 | |
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| 312 | addi r3, r3, GP_18-GP_14 |
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| 313 | #if ( PPC_USE_DATA_CACHE ) |
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| 314 | dcbz r5, r3 |
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| 315 | #endif |
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| 316 | addi r3, r3, GP_22-GP_18 |
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| 317 | #if ( PPC_USE_DATA_CACHE ) |
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| 318 | dcbz r5, r3 |
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| 319 | #endif |
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| 320 | addi r3, r3, GP_26-GP_22 |
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| 321 | #if ( PPC_USE_DATA_CACHE ) |
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| 322 | dcbz r5, r3 |
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| 323 | #endif |
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| 324 | stmw r13, GP_13-GP_26(r3) |
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| 325 | #else |
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| 326 | stw r13, GP_13+4(r3) |
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| 327 | stwu r14, GP_14+4(r3) |
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| 328 | #if ( PPC_USE_DATA_CACHE ) |
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| 329 | dcbz r5, r3 |
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| 330 | #endif |
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| 331 | stw r15, GP_15-GP_14(r3) |
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| 332 | stw r16, GP_16-GP_14(r3) |
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| 333 | stw r17, GP_17-GP_14(r3) |
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| 334 | stwu r18, GP_18-GP_14(r3) |
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| 335 | #if ( PPC_USE_DATA_CACHE ) |
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| 336 | dcbz r5, r3 |
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| 337 | #endif |
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| 338 | stw r19, GP_19-GP_18(r3) |
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| 339 | stw r20, GP_20-GP_18(r3) |
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| 340 | stw r21, GP_21-GP_18(r3) |
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| 341 | stwu r22, GP_22-GP_18(r3) |
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| 342 | #if ( PPC_USE_DATA_CACHE ) |
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| 343 | dcbz r5, r3 |
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| 344 | #endif |
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| 345 | stw r23, GP_23-GP_22(r3) |
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| 346 | stw r24, GP_24-GP_22(r3) |
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| 347 | stw r25, GP_25-GP_22(r3) |
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| 348 | stwu r26, GP_26-GP_22(r3) |
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| 349 | #if ( PPC_USE_DATA_CACHE ) |
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| 350 | dcbz r5, r3 |
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| 351 | #endif |
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| 352 | stw r27, GP_27-GP_26(r3) |
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| 353 | stw r28, GP_28-GP_26(r3) |
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| 354 | stw r29, GP_29-GP_26(r3) |
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| 355 | stw r30, GP_30-GP_26(r3) |
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| 356 | stw r31, GP_31-GP_26(r3) |
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| 357 | #endif |
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| 358 | #if ( PPC_USE_DATA_CACHE ) |
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| 359 | dcbt r0, r4 |
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| 360 | #endif |
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| 361 | mfcr r6 |
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| 362 | stw r6, GP_CR-GP_26(r3) |
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| 363 | mflr r7 |
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| 364 | stw r7, GP_PC-GP_26(r3) |
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| 365 | mfmsr r8 |
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| 366 | stw r8, GP_MSR-GP_26(r3) |
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| 367 | |
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| 368 | #if ( PPC_USE_DATA_CACHE ) |
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| 369 | dcbt r5, r4 |
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| 370 | #endif |
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| 371 | lwz r1, GP_1(r4) |
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| 372 | lwz r2, GP_2(r4) |
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| 373 | #if (PPC_USE_MULTIPLE == 1) |
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| 374 | addi r4, r4, GP_15 |
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| 375 | #if ( PPC_USE_DATA_CACHE ) |
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| 376 | dcbt r5, r4 |
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| 377 | #endif |
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| 378 | addi r4, r4, GP_19-GP_15 |
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| 379 | #if ( PPC_USE_DATA_CACHE ) |
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| 380 | dcbt r5, r4 |
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| 381 | #endif |
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| 382 | addi r4, r4, GP_23-GP_19 |
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| 383 | #if ( PPC_USE_DATA_CACHE ) |
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| 384 | dcbt r5, r4 |
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| 385 | #endif |
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| 386 | addi r4, r4, GP_27-GP_23 |
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| 387 | #if ( PPC_USE_DATA_CACHE ) |
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| 388 | dcbt r5, r4 |
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| 389 | #endif |
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| 390 | lmw r13, GP_13-GP_27(r4) |
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| 391 | #else |
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| 392 | lwz r13, GP_13(r4) |
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| 393 | lwz r14, GP_14(r4) |
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| 394 | lwzu r15, GP_15(r4) |
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| 395 | #if ( PPC_USE_DATA_CACHE ) |
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| 396 | dcbt r5, r4 |
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| 397 | #endif |
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| 398 | lwz r16, GP_16-GP_15(r4) |
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| 399 | lwz r17, GP_17-GP_15(r4) |
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| 400 | lwz r18, GP_18-GP_15(r4) |
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| 401 | lwzu r19, GP_19-GP_15(r4) |
|---|
| 402 | #if ( PPC_USE_DATA_CACHE ) |
|---|
| 403 | dcbt r5, r4 |
|---|
| 404 | #endif |
|---|
| 405 | lwz r20, GP_20-GP_19(r4) |
|---|
| 406 | lwz r21, GP_21-GP_19(r4) |
|---|
| 407 | lwz r22, GP_22-GP_19(r4) |
|---|
| 408 | lwzu r23, GP_23-GP_19(r4) |
|---|
| 409 | #if ( PPC_USE_DATA_CACHE ) |
|---|
| 410 | dcbt r5, r4 |
|---|
| 411 | #endif |
|---|
| 412 | lwz r24, GP_24-GP_23(r4) |
|---|
| 413 | lwz r25, GP_25-GP_23(r4) |
|---|
| 414 | lwz r26, GP_26-GP_23(r4) |
|---|
| 415 | lwzu r27, GP_27-GP_23(r4) |
|---|
| 416 | #if ( PPC_USE_DATA_CACHE ) |
|---|
| 417 | dcbt r5, r4 |
|---|
| 418 | #endif |
|---|
| 419 | lwz r28, GP_28-GP_27(r4) |
|---|
| 420 | lwz r29, GP_29-GP_27(r4) |
|---|
| 421 | lwz r30, GP_30-GP_27(r4) |
|---|
| 422 | lwz r31, GP_31-GP_27(r4) |
|---|
| 423 | #endif |
|---|
| 424 | lwz r6, GP_CR-GP_27(r4) |
|---|
| 425 | lwz r7, GP_PC-GP_27(r4) |
|---|
| 426 | lwz r8, GP_MSR-GP_27(r4) |
|---|
| 427 | mtcrf 255, r6 |
|---|
| 428 | mtlr r7 |
|---|
| 429 | mtmsr r8 |
|---|
| 430 | #endif |
|---|
| 431 | #if (PPC_CACHE_ALIGNMENT == 32) |
|---|
| 432 | /* This assumes that all the registers are in the given order */ |
|---|
| 433 | li r5, 32 |
|---|
| 434 | addi r3,r3,-4 |
|---|
| 435 | #if ( PPC_USE_DATA_CACHE ) |
|---|
| 436 | dcbz r5, r3 |
|---|
| 437 | #endif |
|---|
| 438 | stw r1, GP_1+4(r3) |
|---|
| 439 | stw r2, GP_2+4(r3) |
|---|
| 440 | #if (PPC_USE_MULTIPLE == 1) |
|---|
| 441 | addi r3, r3, GP_18+4 |
|---|
| 442 | #if ( PPC_USE_DATA_CACHE ) |
|---|
| 443 | dcbz r5, r3 |
|---|
| 444 | #endif |
|---|
| 445 | stmw r13, GP_13-GP_18(r3) |
|---|
| 446 | #else |
|---|
| 447 | stw r13, GP_13+4(r3) |
|---|
| 448 | stw r14, GP_14+4(r3) |
|---|
| 449 | stw r15, GP_15+4(r3) |
|---|
| 450 | stw r16, GP_16+4(r3) |
|---|
| 451 | stw r17, GP_17+4(r3) |
|---|
| 452 | stwu r18, GP_18+4(r3) |
|---|
| 453 | #if ( PPC_USE_DATA_CACHE ) |
|---|
| 454 | dcbz r5, r3 |
|---|
| 455 | #endif |
|---|
| 456 | stw r19, GP_19-GP_18(r3) |
|---|
| 457 | stw r20, GP_20-GP_18(r3) |
|---|
| 458 | stw r21, GP_21-GP_18(r3) |
|---|
| 459 | stw r22, GP_22-GP_18(r3) |
|---|
| 460 | stw r23, GP_23-GP_18(r3) |
|---|
| 461 | stw r24, GP_24-GP_18(r3) |
|---|
| 462 | stw r25, GP_25-GP_18(r3) |
|---|
| 463 | stw r26, GP_26-GP_18(r3) |
|---|
| 464 | stw r27, GP_27-GP_18(r3) |
|---|
| 465 | stw r28, GP_28-GP_18(r3) |
|---|
| 466 | stw r29, GP_29-GP_18(r3) |
|---|
| 467 | stw r30, GP_30-GP_18(r3) |
|---|
| 468 | stw r31, GP_31-GP_18(r3) |
|---|
| 469 | #endif |
|---|
| 470 | #if ( PPC_USE_DATA_CACHE ) |
|---|
| 471 | dcbt r0, r4 |
|---|
| 472 | #endif |
|---|
| 473 | mfcr r6 |
|---|
| 474 | stw r6, GP_CR-GP_18(r3) |
|---|
| 475 | mflr r7 |
|---|
| 476 | stw r7, GP_PC-GP_18(r3) |
|---|
| 477 | mfmsr r8 |
|---|
| 478 | stw r8, GP_MSR-GP_18(r3) |
|---|
| 479 | |
|---|
| 480 | #if ( PPC_USE_DATA_CACHE ) |
|---|
| 481 | dcbt r5, r4 |
|---|
| 482 | #endif |
|---|
| 483 | lwz r1, GP_1(r4) |
|---|
| 484 | lwz r2, GP_2(r4) |
|---|
| 485 | #if (PPC_USE_MULTIPLE == 1) |
|---|
| 486 | addi r4, r4, GP_19 |
|---|
| 487 | #if ( PPC_USE_DATA_CACHE ) |
|---|
| 488 | dcbt r5, r4 |
|---|
| 489 | #endif |
|---|
| 490 | lmw r13, GP_13-GP_19(r4) |
|---|
| 491 | #else |
|---|
| 492 | lwz r13, GP_13(r4) |
|---|
| 493 | lwz r14, GP_14(r4) |
|---|
| 494 | lwz r15, GP_15(r4) |
|---|
| 495 | lwz r16, GP_16(r4) |
|---|
| 496 | lwz r17, GP_17(r4) |
|---|
| 497 | lwz r18, GP_18(r4) |
|---|
| 498 | lwzu r19, GP_19(r4) |
|---|
| 499 | #if ( PPC_USE_DATA_CACHE ) |
|---|
| 500 | dcbt r5, r4 |
|---|
| 501 | #endif |
|---|
| 502 | lwz r20, GP_20-GP_19(r4) |
|---|
| 503 | lwz r21, GP_21-GP_19(r4) |
|---|
| 504 | lwz r22, GP_22-GP_19(r4) |
|---|
| 505 | lwz r23, GP_23-GP_19(r4) |
|---|
| 506 | lwz r24, GP_24-GP_19(r4) |
|---|
| 507 | lwz r25, GP_25-GP_19(r4) |
|---|
| 508 | lwz r26, GP_26-GP_19(r4) |
|---|
| 509 | lwz r27, GP_27-GP_19(r4) |
|---|
| 510 | lwz r28, GP_28-GP_19(r4) |
|---|
| 511 | lwz r29, GP_29-GP_19(r4) |
|---|
| 512 | lwz r30, GP_30-GP_19(r4) |
|---|
| 513 | lwz r31, GP_31-GP_19(r4) |
|---|
| 514 | #endif |
|---|
| 515 | lwz r6, GP_CR-GP_19(r4) |
|---|
| 516 | lwz r7, GP_PC-GP_19(r4) |
|---|
| 517 | lwz r8, GP_MSR-GP_19(r4) |
|---|
| 518 | mtcrf 255, r6 |
|---|
| 519 | mtlr r7 |
|---|
| 520 | mtmsr r8 |
|---|
| 521 | #endif |
|---|
| 522 | blr |
|---|
| 523 | |
|---|
| 524 | /* |
|---|
| 525 | * _CPU_Context_restore |
|---|
| 526 | * |
|---|
| 527 | * This routine is generallu used only to restart self in an |
|---|
| 528 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
|---|
| 529 | * |
|---|
| 530 | * NOTE: May be unnecessary to reload some registers. |
|---|
| 531 | */ |
|---|
| 532 | /* |
|---|
| 533 | * ACB: Don't worry about cache optimisation here - this is not THAT critical. |
|---|
| 534 | */ |
|---|
| 535 | ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) |
|---|
| 536 | PUBLIC_PROC (_CPU_Context_restore) |
|---|
| 537 | PROC (_CPU_Context_restore): |
|---|
| 538 | lwz r5, GP_CR(r3) |
|---|
| 539 | lwz r6, GP_PC(r3) |
|---|
| 540 | lwz r7, GP_MSR(r3) |
|---|
| 541 | mtcrf 255, r5 |
|---|
| 542 | mtlr r6 |
|---|
| 543 | mtmsr r7 |
|---|
| 544 | lwz r1, GP_1(r3) |
|---|
| 545 | lwz r2, GP_2(r3) |
|---|
| 546 | #if (PPC_USE_MULTIPLE == 1) |
|---|
| 547 | lmw r13, GP_13(r3) |
|---|
| 548 | #else |
|---|
| 549 | lwz r13, GP_13(r3) |
|---|
| 550 | lwz r14, GP_14(r3) |
|---|
| 551 | lwz r15, GP_15(r3) |
|---|
| 552 | lwz r16, GP_16(r3) |
|---|
| 553 | lwz r17, GP_17(r3) |
|---|
| 554 | lwz r18, GP_18(r3) |
|---|
| 555 | lwz r19, GP_19(r3) |
|---|
| 556 | lwz r20, GP_20(r3) |
|---|
| 557 | lwz r21, GP_21(r3) |
|---|
| 558 | lwz r22, GP_22(r3) |
|---|
| 559 | lwz r23, GP_23(r3) |
|---|
| 560 | lwz r24, GP_24(r3) |
|---|
| 561 | lwz r25, GP_25(r3) |
|---|
| 562 | lwz r26, GP_26(r3) |
|---|
| 563 | lwz r27, GP_27(r3) |
|---|
| 564 | lwz r28, GP_28(r3) |
|---|
| 565 | lwz r29, GP_29(r3) |
|---|
| 566 | lwz r30, GP_30(r3) |
|---|
| 567 | lwz r31, GP_31(r3) |
|---|
| 568 | #endif |
|---|
| 569 | |
|---|
| 570 | blr |
|---|
| 571 | |
|---|
| 572 | /* Individual interrupt prologues look like this: |
|---|
| 573 | * stwu r1, -(IP_END)(r1) |
|---|
| 574 | * stw r0, IP_0(r1) |
|---|
| 575 | * |
|---|
| 576 | * li r0, vectornum |
|---|
| 577 | * b PROC (_ISR_Handler{,C}) |
|---|
| 578 | */ |
|---|
| 579 | |
|---|
| 580 | /* void __ISR_Handler() |
|---|
| 581 | * |
|---|
| 582 | * This routine provides the RTEMS interrupt management. |
|---|
| 583 | * The vector number is in r0. R0 has already been stacked. |
|---|
| 584 | * |
|---|
| 585 | */ |
|---|
| 586 | ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) |
|---|
| 587 | PUBLIC_PROC (_ISR_Handler) |
|---|
| 588 | PROC (_ISR_Handler): |
|---|
| 589 | #define LABEL(x) x |
|---|
| 590 | /* XXX ?? |
|---|
| 591 | #define MTSAVE(x) mtspr sprg0, x |
|---|
| 592 | #define MFSAVE(x) mfspr x, sprg0 |
|---|
| 593 | */ |
|---|
| 594 | #define MTPC(x) mtspr srr0, x |
|---|
| 595 | #define MFPC(x) mfspr x, srr0 |
|---|
| 596 | #define MTMSR(x) mtspr srr1, x |
|---|
| 597 | #define MFMSR(x) mfspr x, srr1 |
|---|
| 598 | |
|---|
| 599 | #include "irq_stub.S" |
|---|
| 600 | rfi |
|---|
| 601 | |
|---|
| 602 | #if (PPC_HAS_RFCI == 1) |
|---|
| 603 | /* void __ISR_HandlerC() |
|---|
| 604 | * |
|---|
| 605 | * This routine provides the RTEMS interrupt management. |
|---|
| 606 | * For critical interrupts |
|---|
| 607 | * |
|---|
| 608 | */ |
|---|
| 609 | ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) |
|---|
| 610 | PUBLIC_PROC (_ISR_HandlerC) |
|---|
| 611 | PROC (_ISR_HandlerC): |
|---|
| 612 | #undef LABEL |
|---|
| 613 | #undef MTSAVE |
|---|
| 614 | #undef MFSAVE |
|---|
| 615 | #undef MTPC |
|---|
| 616 | #undef MFPC |
|---|
| 617 | #undef MTMSR |
|---|
| 618 | #undef MFMSR |
|---|
| 619 | #define LABEL(x) x##_C |
|---|
| 620 | /* XXX?? |
|---|
| 621 | #define MTSAVE(x) mtspr sprg1, x |
|---|
| 622 | #define MFSAVE(x) mfspr x, sprg1 |
|---|
| 623 | */ |
|---|
| 624 | #define MTPC(x) mtspr srr2, x |
|---|
| 625 | #define MFPC(x) mfspr x, srr2 |
|---|
| 626 | #define MTMSR(x) mtspr srr3, x |
|---|
| 627 | #define MFMSR(x) mfspr x, srr3 |
|---|
| 628 | #include "irq_stub.S" |
|---|
| 629 | rfci |
|---|
| 630 | #endif |
|---|
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