source: rtems/c/src/lib/libbsp/powerpc/support/old_exception_processing/cpu.h @ 5e67b98

4.104.114.84.95
Last change on this file since 5e67b98 was 5e67b98, checked in by Joel Sherrill <joel.sherrill@…>, on Jan 3, 2001 at 4:45:52 PM

2001-01-03 Joel Sherrill <joel@…>

  • new_exception_processing/cpu.h, old_exception_processing/cpu.c: old_exception_processing/cpu.h, Added _CPU_Initialize_vectors(). In particular, spurious vector initialization had to be moved on old exception processing model.
  • Property mode set to 100644
File size: 38.7 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the PowerPC
4 *  processor.
5 *
6 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
7 *
8 *  COPYRIGHT (c) 1995 by i-cubed ltd.
9 *
10 *  To anyone who acknowledges that this file is provided "AS IS"
11 *  without any express or implied warranty:
12 *      permission to use, copy, modify, and distribute this file
13 *      for any purpose is hereby granted without fee, provided that
14 *      the above copyright notice and this notice appears in all
15 *      copies, and that the name of i-cubed limited not be used in
16 *      advertising or publicity pertaining to distribution of the
17 *      software without specific, written prior permission.
18 *      i-cubed limited makes no representations about the suitability
19 *      of this software for any purpose.
20 *
21 *  Derived from c/src/exec/cpu/no_cpu/cpu.h:
22 *
23 *  COPYRIGHT (c) 1989-1997.
24 *  On-Line Applications Research Corporation (OAR).
25 *  Copyright assigned to U.S. Government, 1994.
26 *
27 *  The license and distribution terms for this file may in
28 *  the file LICENSE in this distribution or at
29 *  http://www.OARcorp.com/rtems/license.html.
30 *
31 *  $Id$
32 */
33
34#ifndef __CPU_h
35#define __CPU_h
36
37#ifdef __cplusplus
38extern "C" {
39#endif
40
41#include <rtems/score/ppc.h>               /* pick up machine definitions */
42#ifndef ASM
43struct CPU_Interrupt_frame;
44typedef void ( *ppc_isr_entry )( int, struct CPU_Interrupt_frame * );
45
46#include <rtems/score/ppctypes.h>
47#endif
48
49/* conditional compilation parameters */
50
51/*
52 *  Should the calls to _Thread_Enable_dispatch be inlined?
53 *
54 *  If TRUE, then they are inlined.
55 *  If FALSE, then a subroutine call is made.
56 *
57 *  Basically this is an example of the classic trade-off of size
58 *  versus speed.  Inlining the call (TRUE) typically increases the
59 *  size of RTEMS while speeding up the enabling of dispatching.
60 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
61 *  only be 0 or 1 unless you are in an interrupt handler and that
62 *  interrupt handler invokes the executive.]  When not inlined
63 *  something calls _Thread_Enable_dispatch which in turns calls
64 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
65 *  one subroutine call is avoided entirely.]
66 */
67
68#define CPU_INLINE_ENABLE_DISPATCH       FALSE
69
70/*
71 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
72 *  be unrolled one time?  In unrolled each iteration of the loop examines
73 *  two "nodes" on the chain being searched.  Otherwise, only one node
74 *  is examined per iteration.
75 *
76 *  If TRUE, then the loops are unrolled.
77 *  If FALSE, then the loops are not unrolled.
78 *
79 *  The primary factor in making this decision is the cost of disabling
80 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
81 *  body of the loop.  On some CPUs, the flash is more expensive than
82 *  one iteration of the loop body.  In this case, it might be desirable
83 *  to unroll the loop.  It is important to note that on some CPUs, this
84 *  code is the longest interrupt disable period in RTEMS.  So it is
85 *  necessary to strike a balance when setting this parameter.
86 */
87
88#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
89
90/*
91 *  Does RTEMS manage a dedicated interrupt stack in software?
92 *
93 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
94 *  If FALSE, nothing is done.
95 *
96 *  If the CPU supports a dedicated interrupt stack in hardware,
97 *  then it is generally the responsibility of the BSP to allocate it
98 *  and set it up.
99 *
100 *  If the CPU does not support a dedicated interrupt stack, then
101 *  the porter has two options: (1) execute interrupts on the
102 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
103 *  interrupt stack.
104 *
105 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
106 *
107 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
108 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
109 *  possible that both are FALSE for a particular CPU.  Although it
110 *  is unclear what that would imply about the interrupt processing
111 *  procedure on that CPU.
112 */
113
114#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
115
116/*
117 *  Does this CPU have hardware support for a dedicated interrupt stack?
118 *
119 *  If TRUE, then it must be installed during initialization.
120 *  If FALSE, then no installation is performed.
121 *
122 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
123 *
124 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
125 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
126 *  possible that both are FALSE for a particular CPU.  Although it
127 *  is unclear what that would imply about the interrupt processing
128 *  procedure on that CPU.
129 */
130
131/*
132 *  ACB: This is a lie, but it gets us a handle on a call to set up
133 *  a variable derived from the top of the interrupt stack.
134 */
135
136#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
137
138/*
139 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
140 *
141 *  If TRUE, then the memory is allocated during initialization.
142 *  If FALSE, then the memory is allocated during initialization.
143 *
144 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
145 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
146 */
147
148#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
149
150/*
151 *  Does the RTEMS invoke the user's ISR with the vector number and
152 *  a pointer to the saved interrupt frame (1) or just the vector
153 *  number (0)?
154 */
155
156#define CPU_ISR_PASSES_FRAME_POINTER 1
157
158/*
159 *  Does the CPU have hardware floating point?
160 *
161 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
162 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
163 *
164 *  If there is a FP coprocessor such as the i387 or mc68881, then
165 *  the answer is TRUE.
166 *
167 *  The macro name "PPC_HAS_FPU" should be made CPU specific.
168 *  It indicates whether or not this CPU model has FP support.  For
169 *  example, it would be possible to have an i386_nofp CPU model
170 *  which set this to false to indicate that you have an i386 without
171 *  an i387 and wish to leave floating point support out of RTEMS.
172 */
173
174#if ( PPC_HAS_FPU == 1 )
175#define CPU_HARDWARE_FP     TRUE
176#else
177#define CPU_HARDWARE_FP     FALSE
178#endif
179
180/*
181 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
182 *
183 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
184 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
185 *
186 *  So far, the only CPU in which this option has been used is the
187 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
188 *  floating point registers to perform integer multiplies.  If
189 *  a function which you would not think utilize the FP unit DOES,
190 *  then one can not easily predict which tasks will use the FP hardware.
191 *  In this case, this option should be TRUE.
192 *
193 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
194 */
195
196#define CPU_ALL_TASKS_ARE_FP     FALSE
197
198/*
199 *  Should the IDLE task have a floating point context?
200 *
201 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
202 *  and it has a floating point context which is switched in and out.
203 *  If FALSE, then the IDLE task does not have a floating point context.
204 *
205 *  Setting this to TRUE negatively impacts the time required to preempt
206 *  the IDLE task from an interrupt because the floating point context
207 *  must be saved as part of the preemption.
208 */
209
210#define CPU_IDLE_TASK_IS_FP      FALSE
211
212/*
213 *  Should the saving of the floating point registers be deferred
214 *  until a context switch is made to another different floating point
215 *  task?
216 *
217 *  If TRUE, then the floating point context will not be stored until
218 *  necessary.  It will remain in the floating point registers and not
219 *  disturned until another floating point task is switched to.
220 *
221 *  If FALSE, then the floating point context is saved when a floating
222 *  point task is switched out and restored when the next floating point
223 *  task is restored.  The state of the floating point registers between
224 *  those two operations is not specified.
225 *
226 *  If the floating point context does NOT have to be saved as part of
227 *  interrupt dispatching, then it should be safe to set this to TRUE.
228 *
229 *  Setting this flag to TRUE results in using a different algorithm
230 *  for deciding when to save and restore the floating point context.
231 *  The deferred FP switch algorithm minimizes the number of times
232 *  the FP context is saved and restored.  The FP context is not saved
233 *  until a context switch is made to another, different FP task.
234 *  Thus in a system with only one FP task, the FP context will never
235 *  be saved or restored.
236 */
237/*
238 *  ACB Note:  This could make debugging tricky..
239 */
240
241#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
242
243/*
244 *  Does this port provide a CPU dependent IDLE task implementation?
245 *
246 *  If TRUE, then the routine _CPU_Thread_Idle_body
247 *  must be provided and is the default IDLE thread body instead of
248 *  _CPU_Thread_Idle_body.
249 *
250 *  If FALSE, then use the generic IDLE thread body if the BSP does
251 *  not provide one.
252 *
253 *  This is intended to allow for supporting processors which have
254 *  a low power or idle mode.  When the IDLE thread is executed, then
255 *  the CPU can be powered down.
256 *
257 *  The order of precedence for selecting the IDLE thread body is:
258 *
259 *    1.  BSP provided
260 *    2.  CPU dependent (if provided)
261 *    3.  generic (if no BSP and no CPU dependent)
262 */
263
264#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
265
266/*
267 *  Does the stack grow up (toward higher addresses) or down
268 *  (toward lower addresses)?
269 *
270 *  If TRUE, then the grows upward.
271 *  If FALSE, then the grows toward smaller addresses.
272 */
273
274#define CPU_STACK_GROWS_UP               FALSE
275
276/*
277 *  The following is the variable attribute used to force alignment
278 *  of critical RTEMS structures.  On some processors it may make
279 *  sense to have these aligned on tighter boundaries than
280 *  the minimum requirements of the compiler in order to have as
281 *  much of the critical data area as possible in a cache line.
282 *
283 *  The placement of this macro in the declaration of the variables
284 *  is based on the syntactically requirements of the GNU C
285 *  "__attribute__" extension.  For example with GNU C, use
286 *  the following to force a structures to a 32 byte boundary.
287 *
288 *      __attribute__ ((aligned (32)))
289 *
290 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
291 *         To benefit from using this, the data must be heavily
292 *         used so it will stay in the cache and used frequently enough
293 *         in the executive to justify turning this on.
294 */
295
296#define CPU_STRUCTURE_ALIGNMENT \
297  __attribute__ ((aligned (PPC_CACHE_ALIGNMENT)))
298
299/*
300 *  Define what is required to specify how the network to host conversion
301 *  routines are handled.
302 */
303
304#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
305#define CPU_BIG_ENDIAN                           TRUE
306#define CPU_LITTLE_ENDIAN                        FALSE
307
308/*
309 *  The following defines the number of bits actually used in the
310 *  interrupt field of the task mode.  How those bits map to the
311 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
312 *
313 *  The interrupt level is bit mapped for the PowerPC family. The
314 *  bits are set to 0 to indicate that a particular exception source
315 *  enabled and 1 if it is disabled.  This keeps with RTEMS convention
316 *  that interrupt level 0 means all sources are enabled.
317 *
318 *  The bits are assigned to correspond to enable bits in the MSR.
319 */
320
321#define PPC_INTERRUPT_LEVEL_ME   0x01
322#define PPC_INTERRUPT_LEVEL_EE   0x02
323#define PPC_INTERRUPT_LEVEL_CE   0x04
324
325/* XXX should these be maskable? */
326#if 0
327#define PPC_INTERRUPT_LEVEL_DE   0x08
328#define PPC_INTERRUPT_LEVEL_BE   0x10
329#define PPC_INTERRUPT_LEVEL_SE   0x20
330#endif
331
332#define CPU_MODES_INTERRUPT_MASK   0x00000007
333
334/*
335 *  Processor defined structures
336 *
337 *  Examples structures include the descriptor tables from the i386
338 *  and the processor control structure on the i960ca.
339 */
340
341/* may need to put some structures here.  */
342
343/*
344 * Contexts
345 *
346 *  Generally there are 2 types of context to save.
347 *     1. Interrupt registers to save
348 *     2. Task level registers to save
349 *
350 *  This means we have the following 3 context items:
351 *     1. task level context stuff::  Context_Control
352 *     2. floating point task stuff:: Context_Control_fp
353 *     3. special interrupt level context :: Context_Control_interrupt
354 *
355 *  On some processors, it is cost-effective to save only the callee
356 *  preserved registers during a task context switch.  This means
357 *  that the ISR code needs to save those registers which do not
358 *  persist across function calls.  It is not mandatory to make this
359 *  distinctions between the caller/callee saves registers for the
360 *  purpose of minimizing context saved during task switch and on interrupts.
361 *  If the cost of saving extra registers is minimal, simplicity is the
362 *  choice.  Save the same context on interrupt entry as for tasks in
363 *  this case.
364 *
365 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
366 *  care should be used in designing the context area.
367 *
368 *  On some CPUs with hardware floating point support, the Context_Control_fp
369 *  structure will not be used or it simply consist of an array of a
370 *  fixed number of bytes.   This is done when the floating point context
371 *  is dumped by a "FP save context" type instruction and the format
372 *  is not really defined by the CPU.  In this case, there is no need
373 *  to figure out the exact format -- only the size.  Of course, although
374 *  this is enough information for RTEMS, it is probably not enough for
375 *  a debugger such as gdb.  But that is another problem.
376 */
377
378typedef struct {
379    unsigned32 gpr1;    /* Stack pointer for all */
380    unsigned32 gpr2;    /* TOC in PowerOpen, reserved SVR4, section ptr EABI + */
381    unsigned32 gpr13;   /* First non volatile PowerOpen, section ptr SVR4/EABI */
382    unsigned32 gpr14;   /* Non volatile for all */
383    unsigned32 gpr15;   /* Non volatile for all */
384    unsigned32 gpr16;   /* Non volatile for all */
385    unsigned32 gpr17;   /* Non volatile for all */
386    unsigned32 gpr18;   /* Non volatile for all */
387    unsigned32 gpr19;   /* Non volatile for all */
388    unsigned32 gpr20;   /* Non volatile for all */
389    unsigned32 gpr21;   /* Non volatile for all */
390    unsigned32 gpr22;   /* Non volatile for all */
391    unsigned32 gpr23;   /* Non volatile for all */
392    unsigned32 gpr24;   /* Non volatile for all */
393    unsigned32 gpr25;   /* Non volatile for all */
394    unsigned32 gpr26;   /* Non volatile for all */
395    unsigned32 gpr27;   /* Non volatile for all */
396    unsigned32 gpr28;   /* Non volatile for all */
397    unsigned32 gpr29;   /* Non volatile for all */
398    unsigned32 gpr30;   /* Non volatile for all */
399    unsigned32 gpr31;   /* Non volatile for all */
400    unsigned32 cr;      /* PART of the CR is non volatile for all */
401    unsigned32 pc;      /* Program counter/Link register */
402    unsigned32 msr;     /* Initial interrupt level */
403} Context_Control;
404
405typedef struct {
406    /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over
407     * procedure calls.  However, this would mean that the interrupt
408     * frame had to hold f0-f13, and the fpscr.  And as the majority
409     * of tasks will not have an FP context, we will save the whole
410     * context here.
411     */
412#if (PPC_HAS_DOUBLE == 1)
413    double      f[32];
414    double      fpscr;
415#else
416    float       f[32];
417    float       fpscr;
418#endif
419} Context_Control_fp;
420
421typedef struct CPU_Interrupt_frame {
422    unsigned32 stacklink;       /* Ensure this is a real frame (also reg1 save) */
423#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
424    unsigned32 dummy[13];       /* Used by callees: PowerOpen ABI */
425#else
426    unsigned32 dummy[1];        /* Used by callees: SVR4/EABI */
427#endif
428    /* This is what is left out of the primary contexts */
429    unsigned32 gpr0;
430    unsigned32 gpr2;            /* play safe */
431    unsigned32 gpr3;
432    unsigned32 gpr4;
433    unsigned32 gpr5;
434    unsigned32 gpr6;
435    unsigned32 gpr7;
436    unsigned32 gpr8;
437    unsigned32 gpr9;
438    unsigned32 gpr10;
439    unsigned32 gpr11;
440    unsigned32 gpr12;
441    unsigned32 gpr13;   /* Play safe */
442    unsigned32 gpr28;   /* For internal use by the IRQ handler */
443    unsigned32 gpr29;   /* For internal use by the IRQ handler */
444    unsigned32 gpr30;   /* For internal use by the IRQ handler */
445    unsigned32 gpr31;   /* For internal use by the IRQ handler */
446    unsigned32 cr;      /* Bits of this are volatile, so no-one may save */
447    unsigned32 ctr;
448    unsigned32 xer;
449    unsigned32 lr;
450    unsigned32 pc;
451    unsigned32 msr;
452    unsigned32 pad[3];
453} CPU_Interrupt_frame;
454
455
456/*
457 *  The following table contains the information required to configure
458 *  the PowerPC processor specific parameters.
459 */
460
461typedef struct {
462  void       (*pretasking_hook)( void );
463  void       (*predriver_hook)( void );
464  void       (*postdriver_hook)( void );
465  void       (*idle_task)( void );
466  boolean      do_zero_of_workspace;
467  unsigned32   idle_task_stack_size;
468  unsigned32   interrupt_stack_size;
469  unsigned32   extra_mpci_receive_server_stack;
470  void *     (*stack_allocate_hook)( unsigned32 );
471  void       (*stack_free_hook)( void* );
472  /* end of fields required on all CPUs */
473
474  unsigned32   clicks_per_usec;        /* Timer clicks per microsecond */
475  void       (*spurious_handler)(unsigned32 vector, CPU_Interrupt_frame *);
476  boolean      exceptions_in_RAM;     /* TRUE if in RAM */
477
478#if (defined(ppc403) || defined(mpc860) || defined(mpc821))
479  unsigned32   serial_per_sec;         /* Serial clocks per second */
480  boolean      serial_external_clock;
481  boolean      serial_xon_xoff;
482  boolean      serial_cts_rts;
483  unsigned32   serial_rate;
484  unsigned32   timer_average_overhead; /* Average overhead of timer in ticks */
485  unsigned32   timer_least_valid;      /* Least valid number from timer      */
486  boolean      timer_internal_clock;   /* TRUE, when timer runs with CPU clk */
487#endif
488
489#if (defined(mpc860) || defined(mpc821))
490  unsigned32   clock_speed;            /* Speed of CPU in Hz */
491#endif
492}   rtems_cpu_table;
493
494/*
495 *  Macros to access required entires in the CPU Table are in
496 *  the file rtems/system.h.
497 */
498
499/*
500 *  Macros to access PowerPC specific additions to the CPU Table
501 */
502
503#define rtems_cpu_configuration_get_clicks_per_usec() \
504   (_CPU_Table.clicks_per_usec)
505
506#define rtems_cpu_configuration_get_spurious_handler() \
507   (_CPU_Table.spurious_handler)
508
509#define rtems_cpu_configuration_get_exceptions_in_ram() \
510   (_CPU_Table.exceptions_in_RAM)
511
512#if (defined(ppc403) || defined(mpc860) || defined(mpc821))
513
514#define rtems_cpu_configuration_get_serial_per_sec() \
515   (_CPU_Table.serial_per_sec)
516
517#define rtems_cpu_configuration_get_serial_external_clock() \
518   (_CPU_Table.serial_external_clock)
519
520#define rtems_cpu_configuration_get_serial_xon_xoff() \
521   (_CPU_Table.serial_xon_xoff)
522
523#define rtems_cpu_configuration_get_serial_cts_rts() \
524   (_CPU_Table.serial_cts_rts)
525
526#define rtems_cpu_configuration_get_serial_rate() \
527   (_CPU_Table.serial_rate)
528
529#define rtems_cpu_configuration_get_timer_average_overhead() \
530   (_CPU_Table.timer_average_overhead)
531
532#define rtems_cpu_configuration_get_timer_least_valid() \
533   (_CPU_Table.timer_least_valid)
534
535#define rtems_cpu_configuration_get_timer_internal_clock() \
536   (_CPU_Table.timer_internal_clock)
537
538#endif
539
540#if (defined(mpc860) || defined(mpc821))
541#define rtems_cpu_configuration_get_clock_speed() \
542   (_CPU_Table.clock_speed)
543#endif
544
545
546/*
547 *  The following type defines an entry in the PPC's trap table.
548 *
549 *  NOTE: The instructions chosen are RTEMS dependent although one is
550 *        obligated to use two of the four instructions to perform a
551 *        long jump.  The other instructions load one register with the
552 *        trap type (a.k.a. vector) and another with the psr.
553 */
554 
555typedef struct {
556  unsigned32   stwu_r1;                       /* stwu  %r1, -(??+IP_END)(%1)*/
557  unsigned32   stw_r0;                        /* stw   %r0, IP_0(%r1)       */
558  unsigned32   li_r0_IRQ;                     /* li    %r0, _IRQ            */
559  unsigned32   b_Handler;                     /* b     PROC (_ISR_Handler)  */
560} CPU_Trap_table_entry;
561
562/*
563 *  This variable is optional.  It is used on CPUs on which it is difficult
564 *  to generate an "uninitialized" FP context.  It is filled in by
565 *  _CPU_Initialize and copied into the task's FP context area during
566 *  _CPU_Context_Initialize.
567 */
568
569/* EXTERN Context_Control_fp  _CPU_Null_fp_context; */
570
571/*
572 *  On some CPUs, RTEMS supports a software managed interrupt stack.
573 *  This stack is allocated by the Interrupt Manager and the switch
574 *  is performed in _ISR_Handler.  These variables contain pointers
575 *  to the lowest and highest addresses in the chunk of memory allocated
576 *  for the interrupt stack.  Since it is unknown whether the stack
577 *  grows up or down (in general), this give the CPU dependent
578 *  code the option of picking the version it wants to use.
579 *
580 *  NOTE: These two variables are required if the macro
581 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
582 */
583
584SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
585SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
586
587/*
588 *  With some compilation systems, it is difficult if not impossible to
589 *  call a high-level language routine from assembly language.  This
590 *  is especially true of commercial Ada compilers and name mangling
591 *  C++ ones.  This variable can be optionally defined by the CPU porter
592 *  and contains the address of the routine _Thread_Dispatch.  This
593 *  can make it easier to invoke that routine at the end of the interrupt
594 *  sequence (if a dispatch is necessary).
595 */
596
597/* EXTERN void           (*_CPU_Thread_dispatch_pointer)(); */
598
599/*
600 *  Nothing prevents the porter from declaring more CPU specific variables.
601 */
602
603
604SCORE_EXTERN struct {
605  unsigned32 volatile* Nest_level;
606  unsigned32 volatile* Disable_level;
607  void *Vector_table;
608  void *Stack;
609#if (PPC_ABI == PPC_ABI_POWEROPEN)
610  unsigned32 Dispatch_r2;
611#else
612  unsigned32 Default_r2;
613#if (PPC_ABI != PPC_ABI_GCC27)
614  unsigned32 Default_r13;
615#endif
616#endif
617  volatile boolean *Switch_necessary;
618  boolean *Signal;
619
620  unsigned32 msr_initial;
621} _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT;
622
623/*
624 *  The size of the floating point context area.  On some CPUs this
625 *  will not be a "sizeof" because the format of the floating point
626 *  area is not defined -- only the size is.  This is usually on
627 *  CPUs with a "floating point save context" instruction.
628 */
629
630#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
631
632/*
633 * (Optional) # of bytes for libmisc/stackchk to check
634 * If not specifed, then it defaults to something reasonable
635 * for most architectures.
636 */
637
638#define CPU_STACK_CHECK_SIZE    (128)
639
640/*
641 *  Amount of extra stack (above minimum stack size) required by
642 *  MPCI receive server thread.  Remember that in a multiprocessor
643 *  system this thread must exist and be able to process all directives.
644 */
645
646#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
647
648/*
649 *  This defines the number of entries in the ISR_Vector_table managed
650 *  by RTEMS.
651 */
652
653#define CPU_INTERRUPT_NUMBER_OF_VECTORS     (PPC_INTERRUPT_MAX)
654#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (PPC_INTERRUPT_MAX - 1)
655
656/*
657 *  Should be large enough to run all RTEMS tests.  This insures
658 *  that a "reasonable" small application should not have any problems.
659 */
660
661#define CPU_STACK_MINIMUM_SIZE          (1024*8)
662
663/*
664 *  CPU's worst alignment requirement for data types on a byte boundary.  This
665 *  alignment does not take into account the requirements for the stack.
666 */
667
668#define CPU_ALIGNMENT              (PPC_ALIGNMENT)
669
670/*
671 *  This number corresponds to the byte alignment requirement for the
672 *  heap handler.  This alignment requirement may be stricter than that
673 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
674 *  common for the heap to follow the same alignment requirement as
675 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
676 *  then this should be set to CPU_ALIGNMENT.
677 *
678 *  NOTE:  This does not have to be a power of 2.  It does have to
679 *         be greater or equal to than CPU_ALIGNMENT.
680 */
681
682#define CPU_HEAP_ALIGNMENT         (PPC_ALIGNMENT)
683
684/*
685 *  This number corresponds to the byte alignment requirement for memory
686 *  buffers allocated by the partition manager.  This alignment requirement
687 *  may be stricter than that for the data types alignment specified by
688 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
689 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
690 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
691 *
692 *  NOTE:  This does not have to be a power of 2.  It does have to
693 *         be greater or equal to than CPU_ALIGNMENT.
694 */
695
696#define CPU_PARTITION_ALIGNMENT    (PPC_ALIGNMENT)
697
698/*
699 *  This number corresponds to the byte alignment requirement for the
700 *  stack.  This alignment requirement may be stricter than that for the
701 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
702 *  is strict enough for the stack, then this should be set to 0.
703 *
704 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
705 */
706
707#define CPU_STACK_ALIGNMENT        (PPC_STACK_ALIGNMENT)
708
709/*
710 *  ISR handler macros
711 */
712
713void _CPU_Initialize_vectors(void);
714
715/*
716 *  Disable all interrupts for an RTEMS critical section.  The previous
717 *  level is returned in _isr_cookie.
718 */
719
720#define loc_string(a,b) a " (" #b ")\n"
721
722#define _CPU_MSR_Value( _msr_value ) \
723  do { \
724    _msr_value = 0; \
725    asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
726  } while (0)
727
728#define _CPU_MSR_SET( _msr_value ) \
729{ asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
730
731#if 0
732#define _CPU_ISR_Disable( _isr_cookie ) \
733  { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \
734    _isr_cookie = 0; \
735    asm volatile (
736        "mfmsr %0" : \
737        "=r" ((_isr_cookie)) : \
738        "0" ((_isr_cookie)) \
739    ); \
740    asm volatile (
741        "andc %1,%0,%1" : \
742        "=r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
743        "0" ((_isr_cookie)), "1" ((_disable_mask)) \
744    ); \
745    asm volatile (
746        "mtmsr %1" : \
747        "=r" ((_disable_mask)) : \
748        "0" ((_disable_mask)) \
749    ); \
750  }
751#endif
752
753#define _CPU_ISR_Disable( _isr_cookie ) \
754  { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \
755    _isr_cookie = 0; \
756    asm volatile ( \
757        "mfmsr %0; andc %1,%0,%1; mtmsr %1" : \
758        "=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
759        "0" ((_isr_cookie)), "1" ((_disable_mask)) \
760        ); \
761  }
762
763
764#define _CPU_Data_Cache_Block_Flush( _address ) \
765  do { register void *__address = (_address); \
766       register unsigned32 _zero = 0; \
767       asm volatile ( "dcbf %0,%1" : \
768                      "=r" (_zero), "=r" (__address) : \
769                      "0" (_zero), "1" (__address) \
770       ); \
771  } while (0)
772
773#define _CPU_Data_Cache_Block_Invalidate( _address ) \
774  do { register void *__address = (_address); \
775       register unsigned32 _zero = 0; \
776       asm volatile ( "dcbi %0,%1" : \
777                      "=r" (_zero), "=r" (__address) : \
778                      "0" (_zero), "1" (__address) \
779       ); \
780  } while (0)
781
782
783/*
784 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
785 *  This indicates the end of an RTEMS critical section.  The parameter
786 *  _isr_cookie is not modified.
787 */
788
789#define _CPU_ISR_Enable( _isr_cookie )  \
790  { \
791     asm volatile ( "mtmsr %0" : \
792                   "=r" ((_isr_cookie)) : \
793                   "0" ((_isr_cookie))); \
794  }
795
796/*
797 *  This temporarily restores the interrupt to _isr_cookie before immediately
798 *  disabling them again.  This is used to divide long RTEMS critical
799 *  sections into two or more parts.  The parameter _isr_cookie is not
800 *  modified.
801 *
802 *  NOTE:  The version being used is not very optimized but it does
803 *         not trip a problem in gcc where the disable mask does not
804 *         get loaded.  Check this for future (post 10/97 gcc versions.
805 */
806
807#define _CPU_ISR_Flash( _isr_cookie ) \
808  { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \
809    asm volatile ( \
810      "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \
811      "=r" ((_isr_cookie)), "=r" ((_disable_mask)) : \
812      "0" ((_isr_cookie)), "1" ((_disable_mask)) \
813    ); \
814  }
815
816/*
817 *  Map interrupt level in task mode onto the hardware that the CPU
818 *  actually provides.  Currently, interrupt levels which do not
819 *  map onto the CPU in a generic fashion are undefined.  Someday,
820 *  it would be nice if these were "mapped" by the application
821 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
822 *  8 - 255 would be available for bsp/application specific meaning.
823 *  This could be used to manage a programmable interrupt controller
824 *  via the rtems_task_mode directive.
825 */
826
827unsigned32 _CPU_ISR_Calculate_level(
828  unsigned32 new_level
829);
830
831void _CPU_ISR_Set_level(
832  unsigned32 new_level
833);
834 
835unsigned32 _CPU_ISR_Get_level( void );
836
837void _CPU_ISR_install_raw_handler(
838  unsigned32  vector,
839  proc_ptr    new_handler,
840  proc_ptr   *old_handler
841);
842
843/* end of ISR handler macros */
844
845/*
846 *  Simple spin delay in microsecond units for device drivers.
847 *  This is very dependent on the clock speed of the target.
848 */
849
850#define CPU_Get_timebase_low( _value ) \
851    asm volatile( "mftb  %0" : "=r" (_value) )
852
853#define delay( _microseconds ) \
854  do { \
855    unsigned32 start, ticks, now; \
856    CPU_Get_timebase_low( start ) ; \
857    ticks = (_microseconds) * _CPU_Table.clicks_per_usec; \
858    do \
859      CPU_Get_timebase_low( now ) ; \
860    while (now - start < ticks); \
861  } while (0)
862
863#define delay_in_bus_cycles( _cycles ) \
864  do { \
865    unsigned32 start, now; \
866    CPU_Get_timebase_low( start ); \
867    do \
868      CPU_Get_timebase_low( now ); \
869    while (now - start < (_cycles)); \
870  } while (0)
871
872
873
874/* Context handler macros */
875
876/*
877 *  Initialize the context to a state suitable for starting a
878 *  task after a context restore operation.  Generally, this
879 *  involves:
880 *
881 *     - setting a starting address
882 *     - preparing the stack
883 *     - preparing the stack and frame pointers
884 *     - setting the proper interrupt level in the context
885 *     - initializing the floating point context
886 *
887 *  This routine generally does not set any unnecessary register
888 *  in the context.  The state of the "general data" registers is
889 *  undefined at task start time.
890 *
891 *  NOTE:  Implemented as a subroutine for the SPARC port.
892 */
893
894void _CPU_Context_Initialize(
895  Context_Control  *the_context,
896  unsigned32       *stack_base,
897  unsigned32        size,
898  unsigned32        new_level,
899  void             *entry_point,
900  boolean           is_fp
901);
902
903/*
904 *  This routine is responsible for somehow restarting the currently
905 *  executing task.  If you are lucky, then all that is necessary
906 *  is restoring the context.  Otherwise, there will need to be
907 *  a special assembly routine which does something special in this
908 *  case.  Context_Restore should work most of the time.  It will
909 *  not work if restarting self conflicts with the stack frame
910 *  assumptions of restoring a context.
911 */
912
913#define _CPU_Context_Restart_self( _the_context ) \
914   _CPU_Context_restore( (_the_context) );
915
916/*
917 *  The purpose of this macro is to allow the initial pointer into
918 *  a floating point context area (used to save the floating point
919 *  context) to be at an arbitrary place in the floating point
920 *  context area.
921 *
922 *  This is necessary because some FP units are designed to have
923 *  their context saved as a stack which grows into lower addresses.
924 *  Other FP units can be saved by simply moving registers into offsets
925 *  from the base of the context area.  Finally some FP units provide
926 *  a "dump context" instruction which could fill in from high to low
927 *  or low to high based on the whim of the CPU designers.
928 */
929
930#define _CPU_Context_Fp_start( _base, _offset ) \
931   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
932
933/*
934 *  This routine initializes the FP context area passed to it to.
935 *  There are a few standard ways in which to initialize the
936 *  floating point context.  The code included for this macro assumes
937 *  that this is a CPU in which a "initial" FP context was saved into
938 *  _CPU_Null_fp_context and it simply copies it to the destination
939 *  context passed to it.
940 *
941 *  Other models include (1) not doing anything, and (2) putting
942 *  a "null FP status word" in the correct place in the FP context.
943 */
944
945#define _CPU_Context_Initialize_fp( _destination ) \
946  { \
947   ((Context_Control_fp *) *((void **) _destination))->fpscr = PPC_INIT_FPSCR; \
948  }
949
950/* end of Context handler macros */
951
952/* Fatal Error manager macros */
953
954/*
955 *  This routine copies _error into a known place -- typically a stack
956 *  location or a register, optionally disables interrupts, and
957 *  halts/stops the CPU.
958 */
959
960#define _CPU_Fatal_halt( _error ) \
961  _CPU_Fatal_error(_error)
962
963/* end of Fatal Error manager macros */
964
965/* Bitfield handler macros */
966
967/*
968 *  This routine sets _output to the bit number of the first bit
969 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
970 *  This type may be either 16 or 32 bits wide although only the 16
971 *  least significant bits will be used.
972 *
973 *  There are a number of variables in using a "find first bit" type
974 *  instruction.
975 *
976 *    (1) What happens when run on a value of zero?
977 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
978 *    (3) The numbering may be zero or one based.
979 *    (4) The "find first bit" instruction may search from MSB or LSB.
980 *
981 *  RTEMS guarantees that (1) will never happen so it is not a concern.
982 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
983 *  _CPU_Priority_Bits_index().  These three form a set of routines
984 *  which must logically operate together.  Bits in the _value are
985 *  set and cleared based on masks built by _CPU_Priority_mask().
986 *  The basic major and minor values calculated by _Priority_Major()
987 *  and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index()
988 *  to properly range between the values returned by the "find first bit"
989 *  instruction.  This makes it possible for _Priority_Get_highest() to
990 *  calculate the major and directly index into the minor table.
991 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
992 *  is the first bit found.
993 *
994 *  This entire "find first bit" and mapping process depends heavily
995 *  on the manner in which a priority is broken into a major and minor
996 *  components with the major being the 4 MSB of a priority and minor
997 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
998 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
999 *  to the lowest priority.
1000 *
1001 *  If your CPU does not have a "find first bit" instruction, then
1002 *  there are ways to make do without it.  Here are a handful of ways
1003 *  to implement this in software:
1004 *
1005 *    - a series of 16 bit test instructions
1006 *    - a "binary search using if's"
1007 *    - _number = 0
1008 *      if _value > 0x00ff
1009 *        _value >>=8
1010 *        _number = 8;
1011 *
1012 *      if _value > 0x0000f
1013 *        _value >=8
1014 *        _number += 4
1015 *
1016 *      _number += bit_set_table[ _value ]
1017 *
1018 *    where bit_set_table[ 16 ] has values which indicate the first
1019 *      bit set
1020 */
1021
1022#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
1023  { \
1024    asm volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \
1025                  "1" ((_value))); \
1026  }
1027
1028/* end of Bitfield handler macros */
1029
1030/*
1031 *  This routine builds the mask which corresponds to the bit fields
1032 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
1033 *  for that routine.
1034 */
1035
1036#define _CPU_Priority_Mask( _bit_number ) \
1037  ( 0x80000000 >> (_bit_number) )
1038
1039/*
1040 *  This routine translates the bit numbers returned by
1041 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
1042 *  a major or minor component of a priority.  See the discussion
1043 *  for that routine.
1044 */
1045
1046#define _CPU_Priority_bits_index( _priority ) \
1047  (_priority)
1048
1049/* end of Priority handler macros */
1050
1051/* variables */
1052
1053extern const unsigned32 _CPU_msrs[4];
1054
1055/* functions */
1056
1057/*
1058 *  _CPU_Initialize
1059 *
1060 *  This routine performs CPU dependent initialization.
1061 */
1062
1063void _CPU_Initialize(
1064  rtems_cpu_table  *cpu_table,
1065  void            (*thread_dispatch)
1066);
1067
1068/*
1069 *  _CPU_ISR_install_vector
1070 *
1071 *  This routine installs an interrupt vector.
1072 */
1073
1074void _CPU_ISR_install_vector(
1075  unsigned32  vector,
1076  proc_ptr    new_handler,
1077  proc_ptr   *old_handler
1078);
1079
1080/*
1081 *  _CPU_Install_interrupt_stack
1082 *
1083 *  This routine installs the hardware interrupt stack pointer.
1084 *
1085 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
1086 *         is TRUE.
1087 */
1088
1089void _CPU_Install_interrupt_stack( void );
1090
1091/*
1092 *  _CPU_Context_switch
1093 *
1094 *  This routine switches from the run context to the heir context.
1095 */
1096
1097void _CPU_Context_switch(
1098  Context_Control  *run,
1099  Context_Control  *heir
1100);
1101
1102/*
1103 *  _CPU_Context_restore
1104 *
1105 *  This routine is generallu used only to restart self in an
1106 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
1107 *
1108 *  NOTE: May be unnecessary to reload some registers.
1109 */
1110
1111void _CPU_Context_restore(
1112  Context_Control *new_context
1113);
1114
1115/*
1116 *  _CPU_Context_save_fp
1117 *
1118 *  This routine saves the floating point context passed to it.
1119 */
1120
1121void _CPU_Context_save_fp(
1122  void **fp_context_ptr
1123);
1124
1125/*
1126 *  _CPU_Context_restore_fp
1127 *
1128 *  This routine restores the floating point context passed to it.
1129 */
1130
1131void _CPU_Context_restore_fp(
1132  void **fp_context_ptr
1133);
1134
1135void _CPU_Fatal_error(
1136  unsigned32 _error
1137);
1138
1139/*  The following routine swaps the endian format of an unsigned int.
1140 *  It must be static because it is referenced indirectly.
1141 *
1142 *  This version will work on any processor, but if there is a better
1143 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1144 *
1145 *     swap least significant two bytes with 16-bit rotate
1146 *     swap upper and lower 16-bits
1147 *     swap most significant two bytes with 16-bit rotate
1148 *
1149 *  Some CPUs have special instructions which swap a 32-bit quantity in
1150 *  a single instruction (e.g. i486).  It is probably best to avoid
1151 *  an "endian swapping control bit" in the CPU.  One good reason is
1152 *  that interrupts would probably have to be disabled to insure that
1153 *  an interrupt does not try to access the same "chunk" with the wrong
1154 *  endian.  Another good reason is that on some CPUs, the endian bit
1155 *  endianness for ALL fetches -- both code and data -- so the code
1156 *  will be fetched incorrectly.
1157 */
1158 
1159static inline unsigned int CPU_swap_u32(
1160  unsigned int value
1161)
1162{
1163  unsigned32 swapped;
1164 
1165  asm volatile("rlwimi %0,%1,8,24,31;"
1166               "rlwimi %0,%1,24,16,23;"
1167               "rlwimi %0,%1,8,8,15;"
1168               "rlwimi %0,%1,24,0,7;" :
1169               "=&r" ((swapped)) : "r" ((value)));
1170
1171  return( swapped );
1172}
1173
1174#define CPU_swap_u16( value ) \
1175  (((value&0xff) << 8) | ((value >> 8)&0xff))
1176
1177/*
1178 *  Routines to access the decrementer register
1179 */
1180
1181#define PPC_Set_decrementer( _clicks ) \
1182  do { \
1183    asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
1184  } while (0)
1185
1186/*
1187 *  Routines to access the time base register
1188 */
1189
1190static inline unsigned64 PPC_Get_timebase_register( void )
1191{
1192  unsigned32 tbr_low;
1193  unsigned32 tbr_high;
1194  unsigned32 tbr_high_old;
1195  unsigned64 tbr;
1196
1197  do {
1198    asm volatile( "mftbu %0" : "=r" (tbr_high_old));
1199    asm volatile( "mftb  %0" : "=r" (tbr_low));
1200    asm volatile( "mftbu %0" : "=r" (tbr_high));
1201  } while ( tbr_high_old != tbr_high );
1202
1203  tbr = tbr_high;
1204  tbr <<= 32;
1205  tbr |= tbr_low;
1206  return tbr;
1207}
1208
1209#ifdef __cplusplus
1210}
1211#endif
1212
1213#endif
Note: See TracBrowser for help on using the repository browser.