[acc25ee] | 1 | /* cpu.h |
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| 2 | * |
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| 3 | * This include file contains information pertaining to the PowerPC |
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| 4 | * processor. |
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| 5 | * |
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| 6 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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| 7 | * |
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| 8 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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| 9 | * |
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| 10 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 11 | * without any express or implied warranty: |
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| 12 | * permission to use, copy, modify, and distribute this file |
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| 13 | * for any purpose is hereby granted without fee, provided that |
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| 14 | * the above copyright notice and this notice appears in all |
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| 15 | * copies, and that the name of i-cubed limited not be used in |
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| 16 | * advertising or publicity pertaining to distribution of the |
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| 17 | * software without specific, written prior permission. |
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| 18 | * i-cubed limited makes no representations about the suitability |
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| 19 | * of this software for any purpose. |
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| 20 | * |
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| 21 | * Derived from c/src/exec/cpu/no_cpu/cpu.h: |
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| 22 | * |
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| 23 | * COPYRIGHT (c) 1989-1997. |
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| 24 | * On-Line Applications Research Corporation (OAR). |
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| 25 | * |
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| 26 | * The license and distribution terms for this file may in |
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| 27 | * the file LICENSE in this distribution or at |
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| 28 | * http://www.OARcorp.com/rtems/license.html. |
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| 29 | * |
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| 30 | * $Id$ |
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| 31 | */ |
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| 32 | |
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| 33 | #ifndef __CPU_h |
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| 34 | #define __CPU_h |
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| 35 | |
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| 36 | #ifdef __cplusplus |
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| 37 | extern "C" { |
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| 38 | #endif |
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| 39 | |
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| 40 | #include <rtems/score/ppc.h> /* pick up machine definitions */ |
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| 41 | #ifndef ASM |
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| 42 | struct CPU_Interrupt_frame; |
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| 43 | typedef void ( *ppc_isr_entry )( int, struct CPU_Interrupt_frame * ); |
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| 44 | |
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| 45 | #include <rtems/score/ppctypes.h> |
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| 46 | #endif |
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| 47 | |
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| 48 | /* conditional compilation parameters */ |
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| 49 | |
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| 50 | /* |
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| 51 | * Should the calls to _Thread_Enable_dispatch be inlined? |
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| 52 | * |
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| 53 | * If TRUE, then they are inlined. |
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| 54 | * If FALSE, then a subroutine call is made. |
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| 55 | * |
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| 56 | * Basically this is an example of the classic trade-off of size |
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| 57 | * versus speed. Inlining the call (TRUE) typically increases the |
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| 58 | * size of RTEMS while speeding up the enabling of dispatching. |
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| 59 | * [NOTE: In general, the _Thread_Dispatch_disable_level will |
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| 60 | * only be 0 or 1 unless you are in an interrupt handler and that |
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| 61 | * interrupt handler invokes the executive.] When not inlined |
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| 62 | * something calls _Thread_Enable_dispatch which in turns calls |
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| 63 | * _Thread_Dispatch. If the enable dispatch is inlined, then |
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| 64 | * one subroutine call is avoided entirely.] |
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| 65 | */ |
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| 66 | |
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| 67 | #define CPU_INLINE_ENABLE_DISPATCH FALSE |
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| 68 | |
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| 69 | /* |
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| 70 | * Should the body of the search loops in _Thread_queue_Enqueue_priority |
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| 71 | * be unrolled one time? In unrolled each iteration of the loop examines |
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| 72 | * two "nodes" on the chain being searched. Otherwise, only one node |
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| 73 | * is examined per iteration. |
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| 74 | * |
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| 75 | * If TRUE, then the loops are unrolled. |
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| 76 | * If FALSE, then the loops are not unrolled. |
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| 77 | * |
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| 78 | * The primary factor in making this decision is the cost of disabling |
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| 79 | * and enabling interrupts (_ISR_Flash) versus the cost of rest of the |
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| 80 | * body of the loop. On some CPUs, the flash is more expensive than |
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| 81 | * one iteration of the loop body. In this case, it might be desirable |
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| 82 | * to unroll the loop. It is important to note that on some CPUs, this |
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| 83 | * code is the longest interrupt disable period in RTEMS. So it is |
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| 84 | * necessary to strike a balance when setting this parameter. |
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| 85 | */ |
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| 86 | |
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| 87 | #define CPU_UNROLL_ENQUEUE_PRIORITY FALSE |
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| 88 | |
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| 89 | /* |
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| 90 | * Does RTEMS manage a dedicated interrupt stack in software? |
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| 91 | * |
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[8bc62aeb] | 92 | * If TRUE, then a stack is allocated in _ISR_Handler_initialization. |
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[acc25ee] | 93 | * If FALSE, nothing is done. |
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| 94 | * |
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| 95 | * If the CPU supports a dedicated interrupt stack in hardware, |
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| 96 | * then it is generally the responsibility of the BSP to allocate it |
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| 97 | * and set it up. |
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| 98 | * |
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| 99 | * If the CPU does not support a dedicated interrupt stack, then |
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| 100 | * the porter has two options: (1) execute interrupts on the |
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| 101 | * stack of the interrupted task, and (2) have RTEMS manage a dedicated |
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| 102 | * interrupt stack. |
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| 103 | * |
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| 104 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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| 105 | * |
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| 106 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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| 107 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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| 108 | * possible that both are FALSE for a particular CPU. Although it |
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| 109 | * is unclear what that would imply about the interrupt processing |
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| 110 | * procedure on that CPU. |
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| 111 | */ |
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| 112 | |
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| 113 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE |
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| 114 | |
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| 115 | /* |
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| 116 | * Does this CPU have hardware support for a dedicated interrupt stack? |
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| 117 | * |
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| 118 | * If TRUE, then it must be installed during initialization. |
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| 119 | * If FALSE, then no installation is performed. |
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| 120 | * |
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| 121 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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| 122 | * |
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| 123 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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| 124 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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| 125 | * possible that both are FALSE for a particular CPU. Although it |
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| 126 | * is unclear what that would imply about the interrupt processing |
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| 127 | * procedure on that CPU. |
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| 128 | */ |
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| 129 | |
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| 130 | /* |
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| 131 | * ACB: This is a lie, but it gets us a handle on a call to set up |
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| 132 | * a variable derived from the top of the interrupt stack. |
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| 133 | */ |
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| 134 | |
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| 135 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE |
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| 136 | |
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| 137 | /* |
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| 138 | * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? |
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| 139 | * |
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| 140 | * If TRUE, then the memory is allocated during initialization. |
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| 141 | * If FALSE, then the memory is allocated during initialization. |
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| 142 | * |
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| 143 | * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE |
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| 144 | * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. |
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| 145 | */ |
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| 146 | |
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| 147 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
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| 148 | |
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| 149 | /* |
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| 150 | * Does the RTEMS invoke the user's ISR with the vector number and |
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| 151 | * a pointer to the saved interrupt frame (1) or just the vector |
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| 152 | * number (0)? |
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| 153 | */ |
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| 154 | |
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| 155 | #define CPU_ISR_PASSES_FRAME_POINTER 1 |
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| 156 | |
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| 157 | /* |
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| 158 | * Does the CPU have hardware floating point? |
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| 159 | * |
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| 160 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. |
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| 161 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. |
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| 162 | * |
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| 163 | * If there is a FP coprocessor such as the i387 or mc68881, then |
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| 164 | * the answer is TRUE. |
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| 165 | * |
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| 166 | * The macro name "PPC_HAS_FPU" should be made CPU specific. |
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| 167 | * It indicates whether or not this CPU model has FP support. For |
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| 168 | * example, it would be possible to have an i386_nofp CPU model |
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| 169 | * which set this to false to indicate that you have an i386 without |
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| 170 | * an i387 and wish to leave floating point support out of RTEMS. |
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| 171 | */ |
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| 172 | |
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| 173 | #if ( PPC_HAS_FPU == 1 ) |
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| 174 | #define CPU_HARDWARE_FP TRUE |
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| 175 | #else |
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| 176 | #define CPU_HARDWARE_FP FALSE |
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| 177 | #endif |
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| 178 | |
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| 179 | /* |
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| 180 | * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? |
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| 181 | * |
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| 182 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. |
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| 183 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. |
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| 184 | * |
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| 185 | * So far, the only CPU in which this option has been used is the |
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| 186 | * HP PA-RISC. The HP C compiler and gcc both implicitly use the |
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| 187 | * floating point registers to perform integer multiplies. If |
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| 188 | * a function which you would not think utilize the FP unit DOES, |
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| 189 | * then one can not easily predict which tasks will use the FP hardware. |
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| 190 | * In this case, this option should be TRUE. |
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| 191 | * |
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| 192 | * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. |
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| 193 | */ |
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| 194 | |
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| 195 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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| 196 | |
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| 197 | /* |
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| 198 | * Should the IDLE task have a floating point context? |
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| 199 | * |
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| 200 | * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task |
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| 201 | * and it has a floating point context which is switched in and out. |
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| 202 | * If FALSE, then the IDLE task does not have a floating point context. |
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| 203 | * |
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| 204 | * Setting this to TRUE negatively impacts the time required to preempt |
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| 205 | * the IDLE task from an interrupt because the floating point context |
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| 206 | * must be saved as part of the preemption. |
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| 207 | */ |
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| 208 | |
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| 209 | #define CPU_IDLE_TASK_IS_FP FALSE |
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| 210 | |
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| 211 | /* |
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| 212 | * Should the saving of the floating point registers be deferred |
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| 213 | * until a context switch is made to another different floating point |
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| 214 | * task? |
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| 215 | * |
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| 216 | * If TRUE, then the floating point context will not be stored until |
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| 217 | * necessary. It will remain in the floating point registers and not |
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| 218 | * disturned until another floating point task is switched to. |
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| 219 | * |
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| 220 | * If FALSE, then the floating point context is saved when a floating |
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| 221 | * point task is switched out and restored when the next floating point |
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| 222 | * task is restored. The state of the floating point registers between |
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| 223 | * those two operations is not specified. |
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| 224 | * |
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| 225 | * If the floating point context does NOT have to be saved as part of |
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| 226 | * interrupt dispatching, then it should be safe to set this to TRUE. |
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| 227 | * |
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| 228 | * Setting this flag to TRUE results in using a different algorithm |
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| 229 | * for deciding when to save and restore the floating point context. |
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| 230 | * The deferred FP switch algorithm minimizes the number of times |
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| 231 | * the FP context is saved and restored. The FP context is not saved |
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| 232 | * until a context switch is made to another, different FP task. |
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| 233 | * Thus in a system with only one FP task, the FP context will never |
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| 234 | * be saved or restored. |
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| 235 | */ |
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| 236 | /* |
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| 237 | * ACB Note: This could make debugging tricky.. |
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| 238 | */ |
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| 239 | |
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| 240 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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| 241 | |
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| 242 | /* |
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| 243 | * Does this port provide a CPU dependent IDLE task implementation? |
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| 244 | * |
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| 245 | * If TRUE, then the routine _CPU_Thread_Idle_body |
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| 246 | * must be provided and is the default IDLE thread body instead of |
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| 247 | * _CPU_Thread_Idle_body. |
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| 248 | * |
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| 249 | * If FALSE, then use the generic IDLE thread body if the BSP does |
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| 250 | * not provide one. |
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| 251 | * |
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| 252 | * This is intended to allow for supporting processors which have |
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| 253 | * a low power or idle mode. When the IDLE thread is executed, then |
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| 254 | * the CPU can be powered down. |
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| 255 | * |
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| 256 | * The order of precedence for selecting the IDLE thread body is: |
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| 257 | * |
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| 258 | * 1. BSP provided |
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| 259 | * 2. CPU dependent (if provided) |
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| 260 | * 3. generic (if no BSP and no CPU dependent) |
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| 261 | */ |
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| 262 | |
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| 263 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
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| 264 | |
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| 265 | /* |
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| 266 | * Does the stack grow up (toward higher addresses) or down |
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| 267 | * (toward lower addresses)? |
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| 268 | * |
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| 269 | * If TRUE, then the grows upward. |
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| 270 | * If FALSE, then the grows toward smaller addresses. |
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| 271 | */ |
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| 272 | |
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| 273 | #define CPU_STACK_GROWS_UP FALSE |
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| 274 | |
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| 275 | /* |
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| 276 | * The following is the variable attribute used to force alignment |
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| 277 | * of critical RTEMS structures. On some processors it may make |
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| 278 | * sense to have these aligned on tighter boundaries than |
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| 279 | * the minimum requirements of the compiler in order to have as |
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| 280 | * much of the critical data area as possible in a cache line. |
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| 281 | * |
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| 282 | * The placement of this macro in the declaration of the variables |
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| 283 | * is based on the syntactically requirements of the GNU C |
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| 284 | * "__attribute__" extension. For example with GNU C, use |
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| 285 | * the following to force a structures to a 32 byte boundary. |
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| 286 | * |
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| 287 | * __attribute__ ((aligned (32))) |
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| 288 | * |
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| 289 | * NOTE: Currently only the Priority Bit Map table uses this feature. |
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| 290 | * To benefit from using this, the data must be heavily |
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| 291 | * used so it will stay in the cache and used frequently enough |
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| 292 | * in the executive to justify turning this on. |
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| 293 | */ |
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| 294 | |
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| 295 | #define CPU_STRUCTURE_ALIGNMENT \ |
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| 296 | __attribute__ ((aligned (PPC_CACHE_ALIGNMENT))) |
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| 297 | |
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| 298 | /* |
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| 299 | * Define what is required to specify how the network to host conversion |
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| 300 | * routines are handled. |
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| 301 | */ |
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| 302 | |
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| 303 | #define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE |
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| 304 | #define CPU_BIG_ENDIAN TRUE |
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| 305 | #define CPU_LITTLE_ENDIAN FALSE |
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| 306 | |
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| 307 | /* |
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| 308 | * The following defines the number of bits actually used in the |
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| 309 | * interrupt field of the task mode. How those bits map to the |
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| 310 | * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). |
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| 311 | * |
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| 312 | * The interrupt level is bit mapped for the PowerPC family. The |
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| 313 | * bits are set to 0 to indicate that a particular exception source |
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| 314 | * enabled and 1 if it is disabled. This keeps with RTEMS convention |
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| 315 | * that interrupt level 0 means all sources are enabled. |
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| 316 | * |
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| 317 | * The bits are assigned to correspond to enable bits in the MSR. |
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| 318 | */ |
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| 319 | |
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| 320 | #define PPC_INTERRUPT_LEVEL_ME 0x01 |
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| 321 | #define PPC_INTERRUPT_LEVEL_EE 0x02 |
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| 322 | #define PPC_INTERRUPT_LEVEL_CE 0x04 |
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| 323 | |
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| 324 | /* XXX should these be maskable? */ |
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| 325 | #if 0 |
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| 326 | #define PPC_INTERRUPT_LEVEL_DE 0x08 |
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| 327 | #define PPC_INTERRUPT_LEVEL_BE 0x10 |
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| 328 | #define PPC_INTERRUPT_LEVEL_SE 0x20 |
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| 329 | #endif |
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| 330 | |
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| 331 | #define CPU_MODES_INTERRUPT_MASK 0x00000007 |
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| 332 | |
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| 333 | /* |
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| 334 | * Processor defined structures |
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| 335 | * |
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| 336 | * Examples structures include the descriptor tables from the i386 |
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| 337 | * and the processor control structure on the i960ca. |
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| 338 | */ |
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| 339 | |
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| 340 | /* may need to put some structures here. */ |
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| 341 | |
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| 342 | /* |
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| 343 | * Contexts |
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| 344 | * |
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| 345 | * Generally there are 2 types of context to save. |
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| 346 | * 1. Interrupt registers to save |
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| 347 | * 2. Task level registers to save |
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| 348 | * |
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| 349 | * This means we have the following 3 context items: |
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| 350 | * 1. task level context stuff:: Context_Control |
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| 351 | * 2. floating point task stuff:: Context_Control_fp |
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| 352 | * 3. special interrupt level context :: Context_Control_interrupt |
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| 353 | * |
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| 354 | * On some processors, it is cost-effective to save only the callee |
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| 355 | * preserved registers during a task context switch. This means |
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| 356 | * that the ISR code needs to save those registers which do not |
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| 357 | * persist across function calls. It is not mandatory to make this |
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| 358 | * distinctions between the caller/callee saves registers for the |
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| 359 | * purpose of minimizing context saved during task switch and on interrupts. |
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| 360 | * If the cost of saving extra registers is minimal, simplicity is the |
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| 361 | * choice. Save the same context on interrupt entry as for tasks in |
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| 362 | * this case. |
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| 363 | * |
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| 364 | * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then |
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| 365 | * care should be used in designing the context area. |
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| 366 | * |
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| 367 | * On some CPUs with hardware floating point support, the Context_Control_fp |
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| 368 | * structure will not be used or it simply consist of an array of a |
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| 369 | * fixed number of bytes. This is done when the floating point context |
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| 370 | * is dumped by a "FP save context" type instruction and the format |
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| 371 | * is not really defined by the CPU. In this case, there is no need |
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| 372 | * to figure out the exact format -- only the size. Of course, although |
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| 373 | * this is enough information for RTEMS, it is probably not enough for |
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| 374 | * a debugger such as gdb. But that is another problem. |
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| 375 | */ |
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| 376 | |
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| 377 | typedef struct { |
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| 378 | unsigned32 gpr1; /* Stack pointer for all */ |
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| 379 | unsigned32 gpr2; /* TOC in PowerOpen, reserved SVR4, section ptr EABI + */ |
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| 380 | unsigned32 gpr13; /* First non volatile PowerOpen, section ptr SVR4/EABI */ |
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| 381 | unsigned32 gpr14; /* Non volatile for all */ |
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| 382 | unsigned32 gpr15; /* Non volatile for all */ |
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| 383 | unsigned32 gpr16; /* Non volatile for all */ |
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| 384 | unsigned32 gpr17; /* Non volatile for all */ |
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| 385 | unsigned32 gpr18; /* Non volatile for all */ |
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| 386 | unsigned32 gpr19; /* Non volatile for all */ |
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| 387 | unsigned32 gpr20; /* Non volatile for all */ |
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| 388 | unsigned32 gpr21; /* Non volatile for all */ |
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| 389 | unsigned32 gpr22; /* Non volatile for all */ |
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| 390 | unsigned32 gpr23; /* Non volatile for all */ |
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| 391 | unsigned32 gpr24; /* Non volatile for all */ |
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| 392 | unsigned32 gpr25; /* Non volatile for all */ |
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| 393 | unsigned32 gpr26; /* Non volatile for all */ |
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| 394 | unsigned32 gpr27; /* Non volatile for all */ |
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| 395 | unsigned32 gpr28; /* Non volatile for all */ |
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| 396 | unsigned32 gpr29; /* Non volatile for all */ |
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| 397 | unsigned32 gpr30; /* Non volatile for all */ |
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| 398 | unsigned32 gpr31; /* Non volatile for all */ |
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| 399 | unsigned32 cr; /* PART of the CR is non volatile for all */ |
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| 400 | unsigned32 pc; /* Program counter/Link register */ |
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| 401 | unsigned32 msr; /* Initial interrupt level */ |
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| 402 | } Context_Control; |
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| 403 | |
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| 404 | typedef struct { |
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| 405 | /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over |
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| 406 | * procedure calls. However, this would mean that the interrupt |
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| 407 | * frame had to hold f0-f13, and the fpscr. And as the majority |
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| 408 | * of tasks will not have an FP context, we will save the whole |
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| 409 | * context here. |
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| 410 | */ |
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| 411 | #if (PPC_HAS_DOUBLE == 1) |
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| 412 | double f[32]; |
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| 413 | double fpscr; |
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| 414 | #else |
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| 415 | float f[32]; |
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| 416 | float fpscr; |
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| 417 | #endif |
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| 418 | } Context_Control_fp; |
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| 419 | |
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| 420 | typedef struct CPU_Interrupt_frame { |
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| 421 | unsigned32 stacklink; /* Ensure this is a real frame (also reg1 save) */ |
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| 422 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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| 423 | unsigned32 dummy[13]; /* Used by callees: PowerOpen ABI */ |
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| 424 | #else |
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| 425 | unsigned32 dummy[1]; /* Used by callees: SVR4/EABI */ |
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| 426 | #endif |
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| 427 | /* This is what is left out of the primary contexts */ |
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| 428 | unsigned32 gpr0; |
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| 429 | unsigned32 gpr2; /* play safe */ |
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| 430 | unsigned32 gpr3; |
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| 431 | unsigned32 gpr4; |
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| 432 | unsigned32 gpr5; |
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| 433 | unsigned32 gpr6; |
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| 434 | unsigned32 gpr7; |
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| 435 | unsigned32 gpr8; |
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| 436 | unsigned32 gpr9; |
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| 437 | unsigned32 gpr10; |
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| 438 | unsigned32 gpr11; |
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| 439 | unsigned32 gpr12; |
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| 440 | unsigned32 gpr13; /* Play safe */ |
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| 441 | unsigned32 gpr28; /* For internal use by the IRQ handler */ |
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| 442 | unsigned32 gpr29; /* For internal use by the IRQ handler */ |
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| 443 | unsigned32 gpr30; /* For internal use by the IRQ handler */ |
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| 444 | unsigned32 gpr31; /* For internal use by the IRQ handler */ |
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| 445 | unsigned32 cr; /* Bits of this are volatile, so no-one may save */ |
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| 446 | unsigned32 ctr; |
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| 447 | unsigned32 xer; |
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| 448 | unsigned32 lr; |
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| 449 | unsigned32 pc; |
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| 450 | unsigned32 msr; |
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| 451 | unsigned32 pad[3]; |
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| 452 | } CPU_Interrupt_frame; |
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| 453 | |
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| 454 | |
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| 455 | /* |
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| 456 | * The following table contains the information required to configure |
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| 457 | * the PowerPC processor specific parameters. |
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| 458 | */ |
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| 459 | |
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| 460 | typedef struct { |
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| 461 | void (*pretasking_hook)( void ); |
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| 462 | void (*predriver_hook)( void ); |
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| 463 | void (*postdriver_hook)( void ); |
---|
| 464 | void (*idle_task)( void ); |
---|
| 465 | boolean do_zero_of_workspace; |
---|
| 466 | unsigned32 idle_task_stack_size; |
---|
| 467 | unsigned32 interrupt_stack_size; |
---|
| 468 | unsigned32 extra_mpci_receive_server_stack; |
---|
| 469 | void * (*stack_allocate_hook)( unsigned32 ); |
---|
| 470 | void (*stack_free_hook)( void* ); |
---|
| 471 | /* end of fields required on all CPUs */ |
---|
| 472 | |
---|
| 473 | unsigned32 clicks_per_usec; /* Timer clicks per microsecond */ |
---|
| 474 | void (*spurious_handler)(unsigned32 vector, CPU_Interrupt_frame *); |
---|
| 475 | boolean exceptions_in_RAM; /* TRUE if in RAM */ |
---|
| 476 | |
---|
[e9ae97fb] | 477 | #if (defined(ppc403) || defined(ppc405) || defined(mpc860) || defined(mpc821)) |
---|
[acc25ee] | 478 | unsigned32 serial_per_sec; /* Serial clocks per second */ |
---|
| 479 | boolean serial_external_clock; |
---|
| 480 | boolean serial_xon_xoff; |
---|
| 481 | boolean serial_cts_rts; |
---|
| 482 | unsigned32 serial_rate; |
---|
| 483 | unsigned32 timer_average_overhead; /* Average overhead of timer in ticks */ |
---|
| 484 | unsigned32 timer_least_valid; /* Least valid number from timer */ |
---|
| 485 | boolean timer_internal_clock; /* TRUE, when timer runs with CPU clk */ |
---|
| 486 | #endif |
---|
| 487 | |
---|
| 488 | #if (defined(mpc860) || defined(mpc821)) |
---|
| 489 | unsigned32 clock_speed; /* Speed of CPU in Hz */ |
---|
| 490 | #endif |
---|
| 491 | } rtems_cpu_table; |
---|
| 492 | |
---|
| 493 | /* |
---|
| 494 | * Macros to access required entires in the CPU Table are in |
---|
| 495 | * the file rtems/system.h. |
---|
| 496 | */ |
---|
| 497 | |
---|
| 498 | /* |
---|
| 499 | * Macros to access PowerPC specific additions to the CPU Table |
---|
| 500 | */ |
---|
| 501 | |
---|
| 502 | #define rtems_cpu_configuration_get_clicks_per_usec() \ |
---|
| 503 | (_CPU_Table.clicks_per_usec) |
---|
| 504 | |
---|
| 505 | #define rtems_cpu_configuration_get_spurious_handler() \ |
---|
| 506 | (_CPU_Table.spurious_handler) |
---|
| 507 | |
---|
| 508 | #define rtems_cpu_configuration_get_exceptions_in_ram() \ |
---|
| 509 | (_CPU_Table.exceptions_in_RAM) |
---|
| 510 | |
---|
[e9ae97fb] | 511 | #if (defined(ppc403) || defined(ppc405) || defined(mpc860) || defined(mpc821)) |
---|
[acc25ee] | 512 | |
---|
| 513 | #define rtems_cpu_configuration_get_serial_per_sec() \ |
---|
| 514 | (_CPU_Table.serial_per_sec) |
---|
| 515 | |
---|
| 516 | #define rtems_cpu_configuration_get_serial_external_clock() \ |
---|
| 517 | (_CPU_Table.serial_external_clock) |
---|
| 518 | |
---|
| 519 | #define rtems_cpu_configuration_get_serial_xon_xoff() \ |
---|
| 520 | (_CPU_Table.serial_xon_xoff) |
---|
| 521 | |
---|
| 522 | #define rtems_cpu_configuration_get_serial_cts_rts() \ |
---|
| 523 | (_CPU_Table.serial_cts_rts) |
---|
| 524 | |
---|
| 525 | #define rtems_cpu_configuration_get_serial_rate() \ |
---|
| 526 | (_CPU_Table.serial_rate) |
---|
| 527 | |
---|
| 528 | #define rtems_cpu_configuration_get_timer_average_overhead() \ |
---|
| 529 | (_CPU_Table.timer_average_overhead) |
---|
| 530 | |
---|
| 531 | #define rtems_cpu_configuration_get_timer_least_valid() \ |
---|
| 532 | (_CPU_Table.timer_least_valid) |
---|
| 533 | |
---|
| 534 | #define rtems_cpu_configuration_get_timer_internal_clock() \ |
---|
| 535 | (_CPU_Table.timer_internal_clock) |
---|
| 536 | |
---|
| 537 | #endif |
---|
| 538 | |
---|
| 539 | #if (defined(mpc860) || defined(mpc821)) |
---|
| 540 | #define rtems_cpu_configuration_get_clock_speed() \ |
---|
| 541 | (_CPU_Table.clock_speed) |
---|
| 542 | #endif |
---|
| 543 | |
---|
| 544 | |
---|
| 545 | /* |
---|
| 546 | * The following type defines an entry in the PPC's trap table. |
---|
| 547 | * |
---|
| 548 | * NOTE: The instructions chosen are RTEMS dependent although one is |
---|
| 549 | * obligated to use two of the four instructions to perform a |
---|
| 550 | * long jump. The other instructions load one register with the |
---|
| 551 | * trap type (a.k.a. vector) and another with the psr. |
---|
| 552 | */ |
---|
| 553 | |
---|
| 554 | typedef struct { |
---|
| 555 | unsigned32 stwu_r1; /* stwu %r1, -(??+IP_END)(%1)*/ |
---|
| 556 | unsigned32 stw_r0; /* stw %r0, IP_0(%r1) */ |
---|
| 557 | unsigned32 li_r0_IRQ; /* li %r0, _IRQ */ |
---|
| 558 | unsigned32 b_Handler; /* b PROC (_ISR_Handler) */ |
---|
| 559 | } CPU_Trap_table_entry; |
---|
| 560 | |
---|
| 561 | /* |
---|
| 562 | * This variable is optional. It is used on CPUs on which it is difficult |
---|
| 563 | * to generate an "uninitialized" FP context. It is filled in by |
---|
| 564 | * _CPU_Initialize and copied into the task's FP context area during |
---|
| 565 | * _CPU_Context_Initialize. |
---|
| 566 | */ |
---|
| 567 | |
---|
| 568 | /* EXTERN Context_Control_fp _CPU_Null_fp_context; */ |
---|
| 569 | |
---|
| 570 | /* |
---|
| 571 | * On some CPUs, RTEMS supports a software managed interrupt stack. |
---|
| 572 | * This stack is allocated by the Interrupt Manager and the switch |
---|
| 573 | * is performed in _ISR_Handler. These variables contain pointers |
---|
| 574 | * to the lowest and highest addresses in the chunk of memory allocated |
---|
| 575 | * for the interrupt stack. Since it is unknown whether the stack |
---|
| 576 | * grows up or down (in general), this give the CPU dependent |
---|
| 577 | * code the option of picking the version it wants to use. |
---|
| 578 | * |
---|
| 579 | * NOTE: These two variables are required if the macro |
---|
| 580 | * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. |
---|
| 581 | */ |
---|
| 582 | |
---|
| 583 | SCORE_EXTERN void *_CPU_Interrupt_stack_low; |
---|
| 584 | SCORE_EXTERN void *_CPU_Interrupt_stack_high; |
---|
| 585 | |
---|
| 586 | /* |
---|
| 587 | * With some compilation systems, it is difficult if not impossible to |
---|
| 588 | * call a high-level language routine from assembly language. This |
---|
| 589 | * is especially true of commercial Ada compilers and name mangling |
---|
| 590 | * C++ ones. This variable can be optionally defined by the CPU porter |
---|
| 591 | * and contains the address of the routine _Thread_Dispatch. This |
---|
| 592 | * can make it easier to invoke that routine at the end of the interrupt |
---|
| 593 | * sequence (if a dispatch is necessary). |
---|
| 594 | */ |
---|
| 595 | |
---|
| 596 | /* EXTERN void (*_CPU_Thread_dispatch_pointer)(); */ |
---|
| 597 | |
---|
| 598 | /* |
---|
| 599 | * Nothing prevents the porter from declaring more CPU specific variables. |
---|
| 600 | */ |
---|
| 601 | |
---|
| 602 | |
---|
| 603 | SCORE_EXTERN struct { |
---|
[a982e0c6] | 604 | unsigned32 volatile* Nest_level; |
---|
| 605 | unsigned32 volatile* Disable_level; |
---|
[acc25ee] | 606 | void *Vector_table; |
---|
| 607 | void *Stack; |
---|
| 608 | #if (PPC_ABI == PPC_ABI_POWEROPEN) |
---|
| 609 | unsigned32 Dispatch_r2; |
---|
| 610 | #else |
---|
| 611 | unsigned32 Default_r2; |
---|
| 612 | #if (PPC_ABI != PPC_ABI_GCC27) |
---|
| 613 | unsigned32 Default_r13; |
---|
| 614 | #endif |
---|
| 615 | #endif |
---|
| 616 | volatile boolean *Switch_necessary; |
---|
| 617 | boolean *Signal; |
---|
| 618 | |
---|
| 619 | unsigned32 msr_initial; |
---|
| 620 | } _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT; |
---|
| 621 | |
---|
| 622 | /* |
---|
| 623 | * The size of the floating point context area. On some CPUs this |
---|
| 624 | * will not be a "sizeof" because the format of the floating point |
---|
| 625 | * area is not defined -- only the size is. This is usually on |
---|
| 626 | * CPUs with a "floating point save context" instruction. |
---|
| 627 | */ |
---|
| 628 | |
---|
| 629 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
---|
| 630 | |
---|
| 631 | /* |
---|
| 632 | * (Optional) # of bytes for libmisc/stackchk to check |
---|
| 633 | * If not specifed, then it defaults to something reasonable |
---|
| 634 | * for most architectures. |
---|
| 635 | */ |
---|
| 636 | |
---|
| 637 | #define CPU_STACK_CHECK_SIZE (128) |
---|
| 638 | |
---|
| 639 | /* |
---|
| 640 | * Amount of extra stack (above minimum stack size) required by |
---|
| 641 | * MPCI receive server thread. Remember that in a multiprocessor |
---|
| 642 | * system this thread must exist and be able to process all directives. |
---|
| 643 | */ |
---|
| 644 | |
---|
| 645 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
---|
| 646 | |
---|
| 647 | /* |
---|
| 648 | * This defines the number of entries in the ISR_Vector_table managed |
---|
| 649 | * by RTEMS. |
---|
| 650 | */ |
---|
| 651 | |
---|
| 652 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS (PPC_INTERRUPT_MAX) |
---|
| 653 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (PPC_INTERRUPT_MAX - 1) |
---|
| 654 | |
---|
| 655 | /* |
---|
| 656 | * Should be large enough to run all RTEMS tests. This insures |
---|
| 657 | * that a "reasonable" small application should not have any problems. |
---|
| 658 | */ |
---|
| 659 | |
---|
| 660 | #define CPU_STACK_MINIMUM_SIZE (1024*8) |
---|
| 661 | |
---|
| 662 | /* |
---|
| 663 | * CPU's worst alignment requirement for data types on a byte boundary. This |
---|
| 664 | * alignment does not take into account the requirements for the stack. |
---|
| 665 | */ |
---|
| 666 | |
---|
| 667 | #define CPU_ALIGNMENT (PPC_ALIGNMENT) |
---|
| 668 | |
---|
| 669 | /* |
---|
| 670 | * This number corresponds to the byte alignment requirement for the |
---|
| 671 | * heap handler. This alignment requirement may be stricter than that |
---|
| 672 | * for the data types alignment specified by CPU_ALIGNMENT. It is |
---|
| 673 | * common for the heap to follow the same alignment requirement as |
---|
| 674 | * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, |
---|
| 675 | * then this should be set to CPU_ALIGNMENT. |
---|
| 676 | * |
---|
| 677 | * NOTE: This does not have to be a power of 2. It does have to |
---|
| 678 | * be greater or equal to than CPU_ALIGNMENT. |
---|
| 679 | */ |
---|
| 680 | |
---|
| 681 | #define CPU_HEAP_ALIGNMENT (PPC_ALIGNMENT) |
---|
| 682 | |
---|
| 683 | /* |
---|
| 684 | * This number corresponds to the byte alignment requirement for memory |
---|
| 685 | * buffers allocated by the partition manager. This alignment requirement |
---|
| 686 | * may be stricter than that for the data types alignment specified by |
---|
| 687 | * CPU_ALIGNMENT. It is common for the partition to follow the same |
---|
| 688 | * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict |
---|
| 689 | * enough for the partition, then this should be set to CPU_ALIGNMENT. |
---|
| 690 | * |
---|
| 691 | * NOTE: This does not have to be a power of 2. It does have to |
---|
| 692 | * be greater or equal to than CPU_ALIGNMENT. |
---|
| 693 | */ |
---|
| 694 | |
---|
| 695 | #define CPU_PARTITION_ALIGNMENT (PPC_ALIGNMENT) |
---|
| 696 | |
---|
| 697 | /* |
---|
| 698 | * This number corresponds to the byte alignment requirement for the |
---|
| 699 | * stack. This alignment requirement may be stricter than that for the |
---|
| 700 | * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT |
---|
| 701 | * is strict enough for the stack, then this should be set to 0. |
---|
| 702 | * |
---|
| 703 | * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. |
---|
| 704 | */ |
---|
| 705 | |
---|
| 706 | #define CPU_STACK_ALIGNMENT (PPC_STACK_ALIGNMENT) |
---|
| 707 | |
---|
[5e67b98] | 708 | /* |
---|
| 709 | * ISR handler macros |
---|
| 710 | */ |
---|
| 711 | |
---|
| 712 | void _CPU_Initialize_vectors(void); |
---|
[acc25ee] | 713 | |
---|
| 714 | /* |
---|
| 715 | * Disable all interrupts for an RTEMS critical section. The previous |
---|
| 716 | * level is returned in _isr_cookie. |
---|
| 717 | */ |
---|
| 718 | |
---|
| 719 | #define loc_string(a,b) a " (" #b ")\n" |
---|
| 720 | |
---|
| 721 | #define _CPU_MSR_Value( _msr_value ) \ |
---|
| 722 | do { \ |
---|
| 723 | _msr_value = 0; \ |
---|
| 724 | asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \ |
---|
| 725 | } while (0) |
---|
| 726 | |
---|
| 727 | #define _CPU_MSR_SET( _msr_value ) \ |
---|
| 728 | { asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); } |
---|
| 729 | |
---|
| 730 | #if 0 |
---|
| 731 | #define _CPU_ISR_Disable( _isr_cookie ) \ |
---|
| 732 | { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \ |
---|
| 733 | _isr_cookie = 0; \ |
---|
| 734 | asm volatile ( |
---|
| 735 | "mfmsr %0" : \ |
---|
| 736 | "=r" ((_isr_cookie)) : \ |
---|
| 737 | "0" ((_isr_cookie)) \ |
---|
| 738 | ); \ |
---|
| 739 | asm volatile ( |
---|
| 740 | "andc %1,%0,%1" : \ |
---|
| 741 | "=r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \ |
---|
| 742 | "0" ((_isr_cookie)), "1" ((_disable_mask)) \ |
---|
| 743 | ); \ |
---|
| 744 | asm volatile ( |
---|
| 745 | "mtmsr %1" : \ |
---|
| 746 | "=r" ((_disable_mask)) : \ |
---|
| 747 | "0" ((_disable_mask)) \ |
---|
| 748 | ); \ |
---|
| 749 | } |
---|
| 750 | #endif |
---|
| 751 | |
---|
| 752 | #define _CPU_ISR_Disable( _isr_cookie ) \ |
---|
| 753 | { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \ |
---|
| 754 | _isr_cookie = 0; \ |
---|
| 755 | asm volatile ( \ |
---|
| 756 | "mfmsr %0; andc %1,%0,%1; mtmsr %1" : \ |
---|
| 757 | "=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \ |
---|
| 758 | "0" ((_isr_cookie)), "1" ((_disable_mask)) \ |
---|
| 759 | ); \ |
---|
| 760 | } |
---|
| 761 | |
---|
| 762 | |
---|
| 763 | #define _CPU_Data_Cache_Block_Flush( _address ) \ |
---|
| 764 | do { register void *__address = (_address); \ |
---|
| 765 | register unsigned32 _zero = 0; \ |
---|
| 766 | asm volatile ( "dcbf %0,%1" : \ |
---|
| 767 | "=r" (_zero), "=r" (__address) : \ |
---|
| 768 | "0" (_zero), "1" (__address) \ |
---|
| 769 | ); \ |
---|
| 770 | } while (0) |
---|
| 771 | |
---|
[8ef3818] | 772 | #define _CPU_Data_Cache_Block_Invalidate( _address ) \ |
---|
| 773 | do { register void *__address = (_address); \ |
---|
| 774 | register unsigned32 _zero = 0; \ |
---|
| 775 | asm volatile ( "dcbi %0,%1" : \ |
---|
| 776 | "=r" (_zero), "=r" (__address) : \ |
---|
| 777 | "0" (_zero), "1" (__address) \ |
---|
| 778 | ); \ |
---|
| 779 | } while (0) |
---|
| 780 | |
---|
[acc25ee] | 781 | |
---|
| 782 | /* |
---|
| 783 | * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |
---|
| 784 | * This indicates the end of an RTEMS critical section. The parameter |
---|
| 785 | * _isr_cookie is not modified. |
---|
| 786 | */ |
---|
| 787 | |
---|
| 788 | #define _CPU_ISR_Enable( _isr_cookie ) \ |
---|
| 789 | { \ |
---|
| 790 | asm volatile ( "mtmsr %0" : \ |
---|
| 791 | "=r" ((_isr_cookie)) : \ |
---|
| 792 | "0" ((_isr_cookie))); \ |
---|
| 793 | } |
---|
| 794 | |
---|
| 795 | /* |
---|
| 796 | * This temporarily restores the interrupt to _isr_cookie before immediately |
---|
| 797 | * disabling them again. This is used to divide long RTEMS critical |
---|
| 798 | * sections into two or more parts. The parameter _isr_cookie is not |
---|
| 799 | * modified. |
---|
| 800 | * |
---|
| 801 | * NOTE: The version being used is not very optimized but it does |
---|
| 802 | * not trip a problem in gcc where the disable mask does not |
---|
| 803 | * get loaded. Check this for future (post 10/97 gcc versions. |
---|
| 804 | */ |
---|
| 805 | |
---|
| 806 | #define _CPU_ISR_Flash( _isr_cookie ) \ |
---|
| 807 | { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \ |
---|
| 808 | asm volatile ( \ |
---|
| 809 | "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \ |
---|
| 810 | "=r" ((_isr_cookie)), "=r" ((_disable_mask)) : \ |
---|
| 811 | "0" ((_isr_cookie)), "1" ((_disable_mask)) \ |
---|
| 812 | ); \ |
---|
| 813 | } |
---|
| 814 | |
---|
| 815 | /* |
---|
| 816 | * Map interrupt level in task mode onto the hardware that the CPU |
---|
| 817 | * actually provides. Currently, interrupt levels which do not |
---|
| 818 | * map onto the CPU in a generic fashion are undefined. Someday, |
---|
| 819 | * it would be nice if these were "mapped" by the application |
---|
| 820 | * via a callout. For example, m68k has 8 levels 0 - 7, levels |
---|
| 821 | * 8 - 255 would be available for bsp/application specific meaning. |
---|
| 822 | * This could be used to manage a programmable interrupt controller |
---|
| 823 | * via the rtems_task_mode directive. |
---|
| 824 | */ |
---|
| 825 | |
---|
| 826 | unsigned32 _CPU_ISR_Calculate_level( |
---|
| 827 | unsigned32 new_level |
---|
| 828 | ); |
---|
| 829 | |
---|
| 830 | void _CPU_ISR_Set_level( |
---|
| 831 | unsigned32 new_level |
---|
| 832 | ); |
---|
| 833 | |
---|
| 834 | unsigned32 _CPU_ISR_Get_level( void ); |
---|
| 835 | |
---|
| 836 | void _CPU_ISR_install_raw_handler( |
---|
| 837 | unsigned32 vector, |
---|
| 838 | proc_ptr new_handler, |
---|
| 839 | proc_ptr *old_handler |
---|
| 840 | ); |
---|
| 841 | |
---|
| 842 | /* end of ISR handler macros */ |
---|
| 843 | |
---|
| 844 | /* |
---|
| 845 | * Simple spin delay in microsecond units for device drivers. |
---|
| 846 | * This is very dependent on the clock speed of the target. |
---|
| 847 | */ |
---|
| 848 | |
---|
| 849 | #define CPU_Get_timebase_low( _value ) \ |
---|
| 850 | asm volatile( "mftb %0" : "=r" (_value) ) |
---|
| 851 | |
---|
[152790a] | 852 | #define rtems_bsp_delay( _microseconds ) \ |
---|
[acc25ee] | 853 | do { \ |
---|
| 854 | unsigned32 start, ticks, now; \ |
---|
| 855 | CPU_Get_timebase_low( start ) ; \ |
---|
| 856 | ticks = (_microseconds) * _CPU_Table.clicks_per_usec; \ |
---|
| 857 | do \ |
---|
| 858 | CPU_Get_timebase_low( now ) ; \ |
---|
| 859 | while (now - start < ticks); \ |
---|
| 860 | } while (0) |
---|
| 861 | |
---|
[152790a] | 862 | #define rtems_bsp_delay_in_bus_cycles( _cycles ) \ |
---|
[acc25ee] | 863 | do { \ |
---|
| 864 | unsigned32 start, now; \ |
---|
| 865 | CPU_Get_timebase_low( start ); \ |
---|
| 866 | do \ |
---|
| 867 | CPU_Get_timebase_low( now ); \ |
---|
| 868 | while (now - start < (_cycles)); \ |
---|
| 869 | } while (0) |
---|
| 870 | |
---|
| 871 | |
---|
| 872 | |
---|
| 873 | /* Context handler macros */ |
---|
| 874 | |
---|
| 875 | /* |
---|
| 876 | * Initialize the context to a state suitable for starting a |
---|
| 877 | * task after a context restore operation. Generally, this |
---|
| 878 | * involves: |
---|
| 879 | * |
---|
| 880 | * - setting a starting address |
---|
| 881 | * - preparing the stack |
---|
| 882 | * - preparing the stack and frame pointers |
---|
| 883 | * - setting the proper interrupt level in the context |
---|
| 884 | * - initializing the floating point context |
---|
| 885 | * |
---|
| 886 | * This routine generally does not set any unnecessary register |
---|
| 887 | * in the context. The state of the "general data" registers is |
---|
| 888 | * undefined at task start time. |
---|
| 889 | * |
---|
| 890 | * NOTE: Implemented as a subroutine for the SPARC port. |
---|
| 891 | */ |
---|
| 892 | |
---|
| 893 | void _CPU_Context_Initialize( |
---|
| 894 | Context_Control *the_context, |
---|
| 895 | unsigned32 *stack_base, |
---|
| 896 | unsigned32 size, |
---|
| 897 | unsigned32 new_level, |
---|
| 898 | void *entry_point, |
---|
| 899 | boolean is_fp |
---|
| 900 | ); |
---|
| 901 | |
---|
| 902 | /* |
---|
| 903 | * This routine is responsible for somehow restarting the currently |
---|
| 904 | * executing task. If you are lucky, then all that is necessary |
---|
| 905 | * is restoring the context. Otherwise, there will need to be |
---|
| 906 | * a special assembly routine which does something special in this |
---|
| 907 | * case. Context_Restore should work most of the time. It will |
---|
| 908 | * not work if restarting self conflicts with the stack frame |
---|
| 909 | * assumptions of restoring a context. |
---|
| 910 | */ |
---|
| 911 | |
---|
| 912 | #define _CPU_Context_Restart_self( _the_context ) \ |
---|
| 913 | _CPU_Context_restore( (_the_context) ); |
---|
| 914 | |
---|
| 915 | /* |
---|
| 916 | * The purpose of this macro is to allow the initial pointer into |
---|
| 917 | * a floating point context area (used to save the floating point |
---|
| 918 | * context) to be at an arbitrary place in the floating point |
---|
| 919 | * context area. |
---|
| 920 | * |
---|
| 921 | * This is necessary because some FP units are designed to have |
---|
| 922 | * their context saved as a stack which grows into lower addresses. |
---|
| 923 | * Other FP units can be saved by simply moving registers into offsets |
---|
| 924 | * from the base of the context area. Finally some FP units provide |
---|
| 925 | * a "dump context" instruction which could fill in from high to low |
---|
| 926 | * or low to high based on the whim of the CPU designers. |
---|
| 927 | */ |
---|
| 928 | |
---|
| 929 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
---|
| 930 | ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
---|
| 931 | |
---|
| 932 | /* |
---|
| 933 | * This routine initializes the FP context area passed to it to. |
---|
| 934 | * There are a few standard ways in which to initialize the |
---|
| 935 | * floating point context. The code included for this macro assumes |
---|
| 936 | * that this is a CPU in which a "initial" FP context was saved into |
---|
| 937 | * _CPU_Null_fp_context and it simply copies it to the destination |
---|
| 938 | * context passed to it. |
---|
| 939 | * |
---|
| 940 | * Other models include (1) not doing anything, and (2) putting |
---|
| 941 | * a "null FP status word" in the correct place in the FP context. |
---|
| 942 | */ |
---|
| 943 | |
---|
| 944 | #define _CPU_Context_Initialize_fp( _destination ) \ |
---|
| 945 | { \ |
---|
| 946 | ((Context_Control_fp *) *((void **) _destination))->fpscr = PPC_INIT_FPSCR; \ |
---|
| 947 | } |
---|
| 948 | |
---|
| 949 | /* end of Context handler macros */ |
---|
| 950 | |
---|
| 951 | /* Fatal Error manager macros */ |
---|
| 952 | |
---|
| 953 | /* |
---|
| 954 | * This routine copies _error into a known place -- typically a stack |
---|
| 955 | * location or a register, optionally disables interrupts, and |
---|
| 956 | * halts/stops the CPU. |
---|
| 957 | */ |
---|
| 958 | |
---|
| 959 | #define _CPU_Fatal_halt( _error ) \ |
---|
| 960 | _CPU_Fatal_error(_error) |
---|
| 961 | |
---|
| 962 | /* end of Fatal Error manager macros */ |
---|
| 963 | |
---|
| 964 | /* Bitfield handler macros */ |
---|
| 965 | |
---|
| 966 | /* |
---|
| 967 | * This routine sets _output to the bit number of the first bit |
---|
| 968 | * set in _value. _value is of CPU dependent type Priority_Bit_map_control. |
---|
| 969 | * This type may be either 16 or 32 bits wide although only the 16 |
---|
| 970 | * least significant bits will be used. |
---|
| 971 | * |
---|
| 972 | * There are a number of variables in using a "find first bit" type |
---|
| 973 | * instruction. |
---|
| 974 | * |
---|
| 975 | * (1) What happens when run on a value of zero? |
---|
| 976 | * (2) Bits may be numbered from MSB to LSB or vice-versa. |
---|
| 977 | * (3) The numbering may be zero or one based. |
---|
| 978 | * (4) The "find first bit" instruction may search from MSB or LSB. |
---|
| 979 | * |
---|
| 980 | * RTEMS guarantees that (1) will never happen so it is not a concern. |
---|
| 981 | * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and |
---|
| 982 | * _CPU_Priority_Bits_index(). These three form a set of routines |
---|
| 983 | * which must logically operate together. Bits in the _value are |
---|
| 984 | * set and cleared based on masks built by _CPU_Priority_mask(). |
---|
| 985 | * The basic major and minor values calculated by _Priority_Major() |
---|
| 986 | * and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index() |
---|
| 987 | * to properly range between the values returned by the "find first bit" |
---|
| 988 | * instruction. This makes it possible for _Priority_Get_highest() to |
---|
| 989 | * calculate the major and directly index into the minor table. |
---|
| 990 | * This mapping is necessary to ensure that 0 (a high priority major/minor) |
---|
| 991 | * is the first bit found. |
---|
| 992 | * |
---|
| 993 | * This entire "find first bit" and mapping process depends heavily |
---|
| 994 | * on the manner in which a priority is broken into a major and minor |
---|
| 995 | * components with the major being the 4 MSB of a priority and minor |
---|
| 996 | * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest |
---|
| 997 | * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next |
---|
| 998 | * to the lowest priority. |
---|
| 999 | * |
---|
| 1000 | * If your CPU does not have a "find first bit" instruction, then |
---|
| 1001 | * there are ways to make do without it. Here are a handful of ways |
---|
| 1002 | * to implement this in software: |
---|
| 1003 | * |
---|
| 1004 | * - a series of 16 bit test instructions |
---|
| 1005 | * - a "binary search using if's" |
---|
| 1006 | * - _number = 0 |
---|
| 1007 | * if _value > 0x00ff |
---|
| 1008 | * _value >>=8 |
---|
| 1009 | * _number = 8; |
---|
| 1010 | * |
---|
| 1011 | * if _value > 0x0000f |
---|
| 1012 | * _value >=8 |
---|
| 1013 | * _number += 4 |
---|
| 1014 | * |
---|
| 1015 | * _number += bit_set_table[ _value ] |
---|
| 1016 | * |
---|
| 1017 | * where bit_set_table[ 16 ] has values which indicate the first |
---|
| 1018 | * bit set |
---|
| 1019 | */ |
---|
| 1020 | |
---|
| 1021 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
---|
| 1022 | { \ |
---|
| 1023 | asm volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \ |
---|
| 1024 | "1" ((_value))); \ |
---|
| 1025 | } |
---|
| 1026 | |
---|
| 1027 | /* end of Bitfield handler macros */ |
---|
| 1028 | |
---|
| 1029 | /* |
---|
| 1030 | * This routine builds the mask which corresponds to the bit fields |
---|
| 1031 | * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion |
---|
| 1032 | * for that routine. |
---|
| 1033 | */ |
---|
| 1034 | |
---|
| 1035 | #define _CPU_Priority_Mask( _bit_number ) \ |
---|
| 1036 | ( 0x80000000 >> (_bit_number) ) |
---|
| 1037 | |
---|
| 1038 | /* |
---|
| 1039 | * This routine translates the bit numbers returned by |
---|
| 1040 | * _CPU_Bitfield_Find_first_bit() into something suitable for use as |
---|
| 1041 | * a major or minor component of a priority. See the discussion |
---|
| 1042 | * for that routine. |
---|
| 1043 | */ |
---|
| 1044 | |
---|
| 1045 | #define _CPU_Priority_bits_index( _priority ) \ |
---|
| 1046 | (_priority) |
---|
| 1047 | |
---|
| 1048 | /* end of Priority handler macros */ |
---|
| 1049 | |
---|
| 1050 | /* variables */ |
---|
| 1051 | |
---|
| 1052 | extern const unsigned32 _CPU_msrs[4]; |
---|
| 1053 | |
---|
| 1054 | /* functions */ |
---|
| 1055 | |
---|
| 1056 | /* |
---|
| 1057 | * _CPU_Initialize |
---|
| 1058 | * |
---|
| 1059 | * This routine performs CPU dependent initialization. |
---|
| 1060 | */ |
---|
| 1061 | |
---|
| 1062 | void _CPU_Initialize( |
---|
| 1063 | rtems_cpu_table *cpu_table, |
---|
| 1064 | void (*thread_dispatch) |
---|
| 1065 | ); |
---|
| 1066 | |
---|
| 1067 | /* |
---|
| 1068 | * _CPU_ISR_install_vector |
---|
| 1069 | * |
---|
| 1070 | * This routine installs an interrupt vector. |
---|
| 1071 | */ |
---|
| 1072 | |
---|
| 1073 | void _CPU_ISR_install_vector( |
---|
| 1074 | unsigned32 vector, |
---|
| 1075 | proc_ptr new_handler, |
---|
| 1076 | proc_ptr *old_handler |
---|
| 1077 | ); |
---|
| 1078 | |
---|
| 1079 | /* |
---|
| 1080 | * _CPU_Install_interrupt_stack |
---|
| 1081 | * |
---|
| 1082 | * This routine installs the hardware interrupt stack pointer. |
---|
| 1083 | * |
---|
| 1084 | * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK |
---|
| 1085 | * is TRUE. |
---|
| 1086 | */ |
---|
| 1087 | |
---|
| 1088 | void _CPU_Install_interrupt_stack( void ); |
---|
| 1089 | |
---|
| 1090 | /* |
---|
| 1091 | * _CPU_Context_switch |
---|
| 1092 | * |
---|
| 1093 | * This routine switches from the run context to the heir context. |
---|
| 1094 | */ |
---|
| 1095 | |
---|
| 1096 | void _CPU_Context_switch( |
---|
| 1097 | Context_Control *run, |
---|
| 1098 | Context_Control *heir |
---|
| 1099 | ); |
---|
| 1100 | |
---|
| 1101 | /* |
---|
| 1102 | * _CPU_Context_restore |
---|
| 1103 | * |
---|
| 1104 | * This routine is generallu used only to restart self in an |
---|
| 1105 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
---|
| 1106 | * |
---|
| 1107 | * NOTE: May be unnecessary to reload some registers. |
---|
| 1108 | */ |
---|
| 1109 | |
---|
| 1110 | void _CPU_Context_restore( |
---|
| 1111 | Context_Control *new_context |
---|
| 1112 | ); |
---|
| 1113 | |
---|
| 1114 | /* |
---|
| 1115 | * _CPU_Context_save_fp |
---|
| 1116 | * |
---|
| 1117 | * This routine saves the floating point context passed to it. |
---|
| 1118 | */ |
---|
| 1119 | |
---|
| 1120 | void _CPU_Context_save_fp( |
---|
| 1121 | void **fp_context_ptr |
---|
| 1122 | ); |
---|
| 1123 | |
---|
| 1124 | /* |
---|
| 1125 | * _CPU_Context_restore_fp |
---|
| 1126 | * |
---|
| 1127 | * This routine restores the floating point context passed to it. |
---|
| 1128 | */ |
---|
| 1129 | |
---|
| 1130 | void _CPU_Context_restore_fp( |
---|
| 1131 | void **fp_context_ptr |
---|
| 1132 | ); |
---|
| 1133 | |
---|
| 1134 | void _CPU_Fatal_error( |
---|
| 1135 | unsigned32 _error |
---|
| 1136 | ); |
---|
| 1137 | |
---|
| 1138 | /* The following routine swaps the endian format of an unsigned int. |
---|
| 1139 | * It must be static because it is referenced indirectly. |
---|
| 1140 | * |
---|
| 1141 | * This version will work on any processor, but if there is a better |
---|
| 1142 | * way for your CPU PLEASE use it. The most common way to do this is to: |
---|
| 1143 | * |
---|
| 1144 | * swap least significant two bytes with 16-bit rotate |
---|
| 1145 | * swap upper and lower 16-bits |
---|
| 1146 | * swap most significant two bytes with 16-bit rotate |
---|
| 1147 | * |
---|
| 1148 | * Some CPUs have special instructions which swap a 32-bit quantity in |
---|
| 1149 | * a single instruction (e.g. i486). It is probably best to avoid |
---|
| 1150 | * an "endian swapping control bit" in the CPU. One good reason is |
---|
| 1151 | * that interrupts would probably have to be disabled to insure that |
---|
| 1152 | * an interrupt does not try to access the same "chunk" with the wrong |
---|
| 1153 | * endian. Another good reason is that on some CPUs, the endian bit |
---|
| 1154 | * endianness for ALL fetches -- both code and data -- so the code |
---|
| 1155 | * will be fetched incorrectly. |
---|
| 1156 | */ |
---|
| 1157 | |
---|
| 1158 | static inline unsigned int CPU_swap_u32( |
---|
| 1159 | unsigned int value |
---|
| 1160 | ) |
---|
| 1161 | { |
---|
| 1162 | unsigned32 swapped; |
---|
| 1163 | |
---|
| 1164 | asm volatile("rlwimi %0,%1,8,24,31;" |
---|
| 1165 | "rlwimi %0,%1,24,16,23;" |
---|
| 1166 | "rlwimi %0,%1,8,8,15;" |
---|
| 1167 | "rlwimi %0,%1,24,0,7;" : |
---|
| 1168 | "=&r" ((swapped)) : "r" ((value))); |
---|
| 1169 | |
---|
| 1170 | return( swapped ); |
---|
| 1171 | } |
---|
| 1172 | |
---|
| 1173 | #define CPU_swap_u16( value ) \ |
---|
| 1174 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
---|
| 1175 | |
---|
| 1176 | /* |
---|
| 1177 | * Routines to access the decrementer register |
---|
| 1178 | */ |
---|
| 1179 | |
---|
| 1180 | #define PPC_Set_decrementer( _clicks ) \ |
---|
| 1181 | do { \ |
---|
| 1182 | asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ |
---|
| 1183 | } while (0) |
---|
| 1184 | |
---|
| 1185 | /* |
---|
| 1186 | * Routines to access the time base register |
---|
| 1187 | */ |
---|
| 1188 | |
---|
| 1189 | static inline unsigned64 PPC_Get_timebase_register( void ) |
---|
| 1190 | { |
---|
| 1191 | unsigned32 tbr_low; |
---|
| 1192 | unsigned32 tbr_high; |
---|
| 1193 | unsigned32 tbr_high_old; |
---|
| 1194 | unsigned64 tbr; |
---|
| 1195 | |
---|
| 1196 | do { |
---|
| 1197 | asm volatile( "mftbu %0" : "=r" (tbr_high_old)); |
---|
| 1198 | asm volatile( "mftb %0" : "=r" (tbr_low)); |
---|
| 1199 | asm volatile( "mftbu %0" : "=r" (tbr_high)); |
---|
| 1200 | } while ( tbr_high_old != tbr_high ); |
---|
| 1201 | |
---|
| 1202 | tbr = tbr_high; |
---|
| 1203 | tbr <<= 32; |
---|
| 1204 | tbr |= tbr_low; |
---|
| 1205 | return tbr; |
---|
| 1206 | } |
---|
| 1207 | |
---|
| 1208 | #ifdef __cplusplus |
---|
| 1209 | } |
---|
| 1210 | #endif |
---|
| 1211 | |
---|
| 1212 | #endif |
---|