source: rtems/c/src/lib/libbsp/powerpc/support/old_exception_processing/cpu.c @ d946f95

4.104.114.84.95
Last change on this file since d946f95 was d946f95, checked in by Ralf Corsepius <ralf.corsepius@…>, on Feb 9, 2005 at 3:59:50 PM

2005-02-09 Ralf Corsepius <ralf.corsepius@…>

  • cpu.c, cpu_asm.S, irq_stub.S, rtems/score/ppc_offs.h: Remove PPC_ABI_GCC27.
  • Property mode set to 100644
File size: 21.0 KB
Line 
1/*
2 *  PowerPC CPU Dependent Source
3 *
4 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
5 *
6 *  COPYRIGHT (c) 1995 by i-cubed ltd.
7 *
8 *  To anyone who acknowledges that this file is provided "AS IS"
9 *  without any express or implied warranty:
10 *      permission to use, copy, modify, and distribute this file
11 *      for any purpose is hereby granted without fee, provided that
12 *      the above copyright notice and this notice appears in all
13 *      copies, and that the name of i-cubed limited not be used in
14 *      advertising or publicity pertaining to distribution of the
15 *      software without specific, written prior permission.
16 *      i-cubed limited makes no representations about the suitability
17 *      of this software for any purpose.
18 *
19 *  Derived from c/src/exec/cpu/no_cpu/cpu.c:
20 *
21 *  COPYRIGHT (c) 1989-1997.
22 *  On-Line Applications Research Corporation (OAR).
23 *
24 *  The license and distribution terms for this file may be found in
25 *  the file LICENSE in this distribution or at
26 *  http://www.rtems.com/license/LICENSE.
27 *
28 *  $Id$
29 */
30
31#include <bsp.h>
32#include <rtems/system.h>
33#include <rtems/score/isr.h>
34#include <rtems/score/context.h>
35#include <rtems/score/thread.h>
36#include <rtems/score/interr.h>
37
38#include <rtems/powerpc/cache.h>
39
40/*
41 *  These are for testing purposes.
42 */
43
44/*  _CPU_Initialize
45 *
46 *  This routine performs processor dependent initialization.
47 *
48 *  INPUT PARAMETERS:
49 *    cpu_table       - CPU table to initialize
50 *    thread_dispatch - address of disptaching routine
51 */
52
53static void ppc_spurious(int, CPU_Interrupt_frame *);
54
55int _CPU_spurious_count = 0;
56int _CPU_last_spurious = 0;
57
58void _CPU_Initialize(
59  rtems_cpu_table  *cpu_table,
60  void      (*thread_dispatch)      /* ignored on this CPU */
61)
62{
63#if (PPC_USE_SPRG)
64  int i;
65#endif
66#if (PPC_ABI != PPC_ABI_POWEROPEN)
67  register uint32_t   r2 = 0;
68  register uint32_t   r13 = 0;
69
70  asm ("mr %0,13" : "=r" ((r13)) : "0" ((r13)));
71  _CPU_IRQ_info.Default_r13 = r13;
72
73  asm ("mr %0,2" : "=r" ((r2)) : "0" ((r2)));
74  _CPU_IRQ_info.Default_r2 = r2;
75#endif
76
77  _CPU_IRQ_info.Nest_level = &_ISR_Nest_level;
78  _CPU_IRQ_info.Disable_level = &_Thread_Dispatch_disable_level;
79  /* fill in _CPU_IRQ_info.Vector_table later */
80#if (PPC_ABI == PPC_ABI_POWEROPEN)
81  _CPU_IRQ_info.Dispatch_r2 = ((uint32_t*)_Thread_Dispatch)[1];
82#endif
83  _CPU_IRQ_info.Switch_necessary = &_Context_Switch_necessary;
84  _CPU_IRQ_info.Signal = &_ISR_Signals_to_thread_executing;
85
86#if (PPC_USE_SPRG)
87  i = (int)&_CPU_IRQ_info;
88  asm volatile("mtspr 0x113, %0" : "=r" (i) : "0" (i)); /* SPRG 3 */
89#endif
90
91  /*
92   * Store Msr Value in the IRQ info structure.
93   */
94   _CPU_MSR_Value(_CPU_IRQ_info.msr_initial);
95
96#if (PPC_USE_SPRG)
97  i = _CPU_IRQ_info.msr_initial;
98  asm volatile("mtspr 0x112, %0" : "=r" (i) : "0" (i)); /* SPRG 2 */
99#endif
100
101  _CPU_Table = *cpu_table;
102}
103
104/*
105 *  _CPU_Initialize_vectors()
106 *
107 *  Support routine to initialize the RTEMS vector table after it is allocated.
108 *
109 *  PowerPC Specific Information:
110 *
111 *  Complete initialization since the table is now allocated.
112 */
113
114void _CPU_Initialize_vectors(void)
115{
116  int i;
117  proc_ptr handler = (proc_ptr)ppc_spurious;
118
119  _CPU_IRQ_info.Vector_table = _ISR_Vector_table;
120
121  if ( _CPU_Table.spurious_handler )
122    handler = (proc_ptr)_CPU_Table.spurious_handler;
123
124  for (i = 0; i < PPC_INTERRUPT_MAX;  i++)
125    _ISR_Vector_table[i] = handler;
126
127}
128
129/*PAGE
130 *
131 *  _CPU_ISR_Calculate_level
132 *
133 *  The PowerPC puts its interrupt enable status in the MSR register
134 *  which also contains things like endianness control.  To be more
135 *  awkward, the layout varies from processor to processor.  This
136 *  is why it was necessary to adopt a scheme which allowed the user
137 *  to specify specifically which interrupt sources were enabled.
138 */
139
140uint32_t   _CPU_ISR_Calculate_level(
141  uint32_t   new_level
142)
143{
144  register uint32_t   new_msr = 0;
145
146  /*
147   *  Set the critical interrupt enable bit
148   */
149
150#if (PPC_HAS_RFCI)
151  if ( !(new_level & PPC_INTERRUPT_LEVEL_CE) )
152    new_msr |= PPC_MSR_CE;
153#endif
154
155  if ( !(new_level & PPC_INTERRUPT_LEVEL_ME) )
156    new_msr |= PPC_MSR_ME;
157
158  if ( !(new_level & PPC_INTERRUPT_LEVEL_EE) )
159    new_msr |= PPC_MSR_EE;
160
161  return new_msr;
162}
163
164/*PAGE
165 *
166 *  _CPU_ISR_Set_level
167 *
168 *  This routine sets the requested level in the MSR.
169 */
170
171void _CPU_ISR_Set_level(
172  uint32_t   new_level
173)
174{
175  register uint32_t   tmp = 0;
176  register uint32_t   new_msr;
177
178  new_msr = _CPU_ISR_Calculate_level( new_level );
179
180  asm volatile (
181    "mfmsr %0; andc %0,%0,%1; and %2, %2, %1; or %0, %0, %2; mtmsr %0" :
182    "=&r" ((tmp)) :
183    "r" ((PPC_MSR_DISABLE_MASK)), "r" ((new_msr)), "0" ((tmp))
184  );
185}
186
187/*PAGE
188 *
189 *  _CPU_ISR_Get_level
190 *
191 *  This routine gets the current interrupt level from the MSR and
192 *  converts it to an RTEMS interrupt level.
193 */
194
195uint32_t   _CPU_ISR_Get_level( void )
196{
197  uint32_t   level = 0;
198  uint32_t   msr;
199
200  asm volatile("mfmsr %0" : "=r" ((msr)));
201
202  msr &= PPC_MSR_DISABLE_MASK;
203
204  /*
205   *  Set the critical interrupt enable bit
206   */
207
208#if (PPC_HAS_RFCI)
209  if ( !(msr & PPC_MSR_CE) )
210    level |= PPC_INTERRUPT_LEVEL_CE;
211#endif
212
213  if ( !(msr & PPC_MSR_ME) )
214    level |= PPC_INTERRUPT_LEVEL_ME;
215
216  if ( !(msr & PPC_MSR_EE) )
217    level |= PPC_INTERRUPT_LEVEL_EE;
218
219  return level;
220}
221
222/*PAGE
223 *
224 *  _CPU_Context_Initialize
225 */
226
227#if (PPC_ABI == PPC_ABI_POWEROPEN)
228#define CPU_MINIMUM_STACK_FRAME_SIZE 56
229#else /* PPC_ABI_SVR4 or PPC_ABI_EABI */
230#define CPU_MINIMUM_STACK_FRAME_SIZE 8
231#endif
232
233void _CPU_Context_Initialize(
234  Context_Control  *the_context,
235  uint32_t         *stack_base,
236  uint32_t          size,
237  uint32_t          new_level,
238  void             *entry_point,
239  boolean           is_fp
240)
241{
242  uint32_t   msr_value;
243  uint32_t   sp;
244
245  sp = (uint32_t)stack_base + size - CPU_MINIMUM_STACK_FRAME_SIZE;
246  *((uint32_t*)sp) = 0;
247  the_context->gpr1 = sp;
248
249  the_context->msr = _CPU_ISR_Calculate_level( new_level );
250
251  /*
252   *  The FP bit of the MSR should only be enabled if this is a floating
253   *  point task.  Unfortunately, the vfprintf_r routine in newlib
254   *  ends up pushing a floating point register regardless of whether or
255   *  not a floating point number is being printed.  Serious restructuring
256   *  of vfprintf.c will be required to avoid this behavior.  At this
257   *  time (7 July 1997), this restructuring is not being done.
258   */
259
260  /*if ( is_fp ) */
261    the_context->msr |= PPC_MSR_FP;
262
263  /*
264   *  Calculate the task's MSR value:
265   *
266   *     + Set the exception prefix bit to point to the exception table
267   *     + Force the RI bit
268   *     + Use the DR and IR bits
269   */
270  _CPU_MSR_Value( msr_value );
271  the_context->msr |= (msr_value & PPC_MSR_EP);
272  the_context->msr |= PPC_MSR_RI;
273  the_context->msr |= msr_value & (PPC_MSR_DR|PPC_MSR_IR);
274
275#if (PPC_ABI == PPC_ABI_POWEROPEN)
276  { uint32_t   *desc = (uint32_t*)entry_point;
277
278    the_context->pc = desc[0];
279    the_context->gpr2 = desc[1];
280  }
281#endif
282
283#if (PPC_ABI == PPC_ABI_SVR4)
284  { unsigned    r13 = 0;
285    asm volatile ("mr %0, 13" : "=r" ((r13)));
286
287    the_context->pc = (uint32_t)entry_point;
288    the_context->gpr13 = r13;
289  }
290#endif
291
292#if (PPC_ABI == PPC_ABI_EABI)
293  { uint32_t    r2 = 0;
294    unsigned    r13 = 0;
295    asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13)));
296
297    the_context->pc = (uint32_t)entry_point;
298    the_context->gpr2 = r2;
299    the_context->gpr13 = r13;
300  }
301#endif
302}
303
304/*  _CPU_ISR_install_vector
305 *
306 *  This kernel routine installs the RTEMS handler for the
307 *  specified vector.
308 *
309 *  Input parameters:
310 *    vector      - interrupt vector number
311 *    old_handler - former ISR for this vector number
312 *    new_handler - replacement ISR for this vector number
313 *
314 *  Output parameters:  NONE
315 *
316 */
317
318void _CPU_ISR_install_vector(
319  uint32_t    vector,
320  proc_ptr    new_handler,
321  proc_ptr   *old_handler
322)
323{
324   proc_ptr   ignored;
325   *old_handler = _ISR_Vector_table[ vector ];
326
327   /*
328    *  If the interrupt vector table is a table of pointer to isr entry
329    *  points, then we need to install the appropriate RTEMS interrupt
330    *  handler for this vector number.
331    */
332
333   /*
334    * Install the wrapper so this ISR can be invoked properly.
335    */
336   if (_CPU_Table.exceptions_in_RAM)
337      _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
338
339   /*
340    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
341    *  be used by the _ISR_Handler so the user gets control.
342    */
343
344    _ISR_Vector_table[ vector ] = new_handler ? (ISR_Handler_entry)new_handler :
345       _CPU_Table.spurious_handler ?
346          (ISR_Handler_entry)_CPU_Table.spurious_handler :
347          (ISR_Handler_entry)ppc_spurious;
348}
349
350/*PAGE
351 *
352 *  _CPU_Install_interrupt_stack
353 */
354
355void _CPU_Install_interrupt_stack( void )
356{
357#if (PPC_ABI == PPC_ABI_POWEROPEN)
358  _CPU_IRQ_info.Stack = _CPU_Interrupt_stack_high - 56;
359#else
360  _CPU_IRQ_info.Stack = _CPU_Interrupt_stack_high - 8;
361#endif
362}
363
364/* Handle a spurious interrupt */
365static void ppc_spurious(int v, CPU_Interrupt_frame *i)
366{
367#if 0
368    printf("Spurious interrupt on vector %d from %08.8x\n",
369           v, i->pc);
370#endif
371#if defined(ppc403) || defined(ppc405)
372    if (v == PPC_IRQ_EXTERNAL)
373        {
374            register int r = 0;
375
376            asm volatile("mtdcr 0x42, %0" :
377                "=&r" ((r)) : "0" ((r))); /* EXIER */
378        }
379    else if (v == PPC_IRQ_PIT)
380        {
381            register int r = 0x08000000;
382
383            asm volatile("mtspr 0x3d8, %0" :
384                "=&r" ((r)) : "0" ((r))); /* TSR */
385        }
386    else if (v == PPC_IRQ_FIT)
387        {
388            register int r = 0x04000000;
389
390            asm volatile("mtspr 0x3d8, %0" :
391                "=&r" ((r)) : "0" ((r))); /* TSR */
392        }
393#endif
394    ++_CPU_spurious_count;
395    _CPU_last_spurious = v;
396}
397
398void _CPU_Fatal_error(uint32_t   _error)
399{
400  asm volatile ("mr 3, %0" : : "r" ((_error)));
401  asm volatile ("tweq 5,5");
402  asm volatile ("li 0,0; mtmsr 0");
403  while (1) ;
404}
405
406#define PPC_SYNCHRONOUS_TRAP_BIT_MASK    0x100
407#define PPC_ASYNCHRONOUS_TRAP( _trap ) (_trap)
408#define PPC_SYNCHRONOUS_TRAP ( _trap ) ((_trap)+PPC_SYNCHRONOUS_TRAP_BIT_MASK)
409#define PPC_REAL_TRAP_NUMBER ( _trap ) ((_trap)%PPC_SYNCHRONOUS_TRAP_BIT_MASK)
410
411const CPU_Trap_table_entry _CPU_Trap_slot_template = {
412
413#if (PPC_ABI == PPC_ABI_POWEROPEN)
414#error " Vector install not tested."
415#if (PPC_HAS_FPU)
416#error " Vector install not tested."
417  0x9421feb0,           /* stwu r1, -(20*4 + 18*8 + IP_END)(r1) */
418#else
419#error " Vector install not tested."
420  0x9421ff40,           /* stwu    r1, -(20*4 + IP_END)(r1)     */
421#endif
422#else
423  0x9421ff90,           /* stwu    r1, -(IP_END)(r1)            */
424#endif
425
426  0x90010008,           /* stw   %r0, IP_0(%r1)                 */
427  0x38000000,           /* li    %r0, PPC_IRQ                   */
428  0x48000002            /* ba    PROC (_ISR_Handler)            */
429};
430
431#if defined(mpc860) || defined(mpc821)
432const CPU_Trap_table_entry _CPU_Trap_slot_template_m860 = {
433  0x7c0803ac,           /* mtlr  %r0                            */
434  0x81210028,           /* lwz   %r9, IP_9(%r1)                 */
435  0x38000000,           /* li    %r0, PPC_IRQ                   */
436  0x48000002            /* b     PROC (_ISR_Handler)            */
437};
438#endif /* mpc860 */
439
440uint32_t    ppc_exception_vector_addr(
441  uint32_t   vector
442);
443
444/*PAGE
445 *
446 *  _CPU_ISR_install_raw_handler
447 *
448 *  This routine installs the specified handler as a "raw" non-executive
449 *  supported trap handler (a.k.a. interrupt service routine).
450 *
451 *  Input Parameters:
452 *    vector      - trap table entry number plus synchronous
453 *                    vs. asynchronous information
454 *    new_handler - address of the handler to be installed
455 *    old_handler - pointer to an address of the handler previously installed
456 *
457 *  Output Parameters: NONE
458 *    *new_handler - address of the handler previously installed
459 *
460 *  NOTE:
461 *
462 *  This routine is based on the SPARC routine _CPU_ISR_install_raw_handler.
463 *  Install a software trap handler as an executive interrupt handler
464 *  (which is desirable since RTEMS takes care of window and register issues),
465 *  then the executive needs to know that the return address is to the trap
466 *  rather than the instruction following the trap.
467 *
468 */
469
470void _CPU_ISR_install_raw_handler(
471  uint32_t    vector,
472  proc_ptr    new_handler,
473  proc_ptr   *old_handler
474)
475{
476  uint32_t               real_vector;
477  CPU_Trap_table_entry  *slot;
478  uint32_t               u32_handler=0;
479
480  /*
481   *  Get the "real" trap number for this vector ignoring the synchronous
482   *  versus asynchronous indicator included with our vector numbers.
483   */
484
485  real_vector = vector;
486
487  /*
488   *  Get the current base address of the trap table and calculate a pointer
489   *  to the slot we are interested in.
490   */
491  slot = (CPU_Trap_table_entry  *)ppc_exception_vector_addr( real_vector );
492
493  /*
494   *  Get the address of the old_handler from the trap table.
495   *
496   *  NOTE: The old_handler returned will be bogus if it does not follow
497   *        the RTEMS model.
498   */
499
500#define HIGH_BITS_MASK   0xFFFFFC00
501#define HIGH_BITS_SHIFT  10
502#define LOW_BITS_MASK    0x000003FF
503
504  if (slot->stwu_r1 == _CPU_Trap_slot_template.stwu_r1) {
505    /*
506     * Set u32_handler = to target address
507     */
508    u32_handler = slot->b_Handler & 0x03fffffc;
509
510    /* IMD FIX: sign extend address fragment... */
511    if (u32_handler & 0x02000000) {
512      u32_handler  |= 0xfc000000;
513    }
514
515    *old_handler =  (proc_ptr) u32_handler;
516  } else
517/* There are two kinds of handlers for the MPC860. One is the 'standard'
518 *  one like above. The other is for the cascaded interrupts from the SIU
519 *  and CPM. Therefore we must check for the alternate one if the standard
520 *  one is not present
521 */
522#if defined(mpc860) || defined(mpc821)
523  if (slot->stwu_r1 == _CPU_Trap_slot_template_m860.stwu_r1) {
524    /*
525     * Set u32_handler = to target address
526     */
527    u32_handler = slot->b_Handler & 0x03fffffc;
528    *old_handler =  (proc_ptr) u32_handler;
529  } else
530#endif /* mpc860 */
531
532    *old_handler = 0;
533
534  /*
535   *  Copy the template to the slot and then fix it.
536   */
537#if defined(mpc860) || defined(mpc821)
538  if (vector >= PPC_IRQ_IRQ0)
539    *slot = _CPU_Trap_slot_template_m860;
540  else
541#endif /* mpc860 */
542  *slot = _CPU_Trap_slot_template;
543
544  u32_handler = (uint32_t) new_handler;
545
546  /*
547   * IMD FIX: insert address fragment only (bits 6..29)
548   *          therefore check for proper address range
549   *          and remove unwanted bits
550   */
551  if ((u32_handler & 0xfc000000) == 0xfc000000) {
552    u32_handler  &= ~0xfc000000;
553  }
554  else if ((u32_handler & 0xfc000000) != 0x00000000) {
555    _Internal_error_Occurred(INTERNAL_ERROR_CORE,
556                             TRUE,
557                             u32_handler);
558  }
559
560  slot->b_Handler |= u32_handler;
561
562  slot->li_r0_IRQ  |= vector;
563
564  _CPU_Data_Cache_Block_Flush( slot );
565}
566
567uint32_t    ppc_exception_vector_addr(
568  uint32_t   vector
569)
570{
571#if (!PPC_HAS_EVPR)
572  uint32_t   Msr;
573#endif
574  uint32_t   Top = 0;
575  uint32_t   Offset = 0x000;
576
577#if (PPC_HAS_EXCEPTION_PREFIX)
578  _CPU_MSR_Value ( Msr );
579  if ( ( Msr & PPC_MSR_EP) != 0 ) /* Vectors at FFFx_xxxx */
580    Top = 0xfff00000;
581#elif (PPC_HAS_EVPR)
582  asm volatile( "mfspr %0,0x3d6" : "=r" (Top)); /* EVPR */
583  Top = Top & 0xffff0000;
584#endif
585
586  switch ( vector ) {
587    case PPC_IRQ_SYSTEM_RESET:   /* on 40x aka PPC_IRQ_CRIT */
588      Offset = 0x00100;
589      break;
590    case PPC_IRQ_MCHECK:
591      Offset = 0x00200;
592      break;
593    case PPC_IRQ_PROTECT:
594      Offset = 0x00300;
595      break;
596    case PPC_IRQ_ISI:
597      Offset = 0x00400;
598      break;
599    case PPC_IRQ_EXTERNAL:
600      Offset = 0x00500;
601      break;
602    case PPC_IRQ_ALIGNMENT:
603      Offset = 0x00600;
604      break;
605    case PPC_IRQ_PROGRAM:
606      Offset = 0x00700;
607      break;
608    case PPC_IRQ_NOFP:
609      Offset = 0x00800;
610      break;
611    case PPC_IRQ_DECREMENTER:
612      Offset = 0x00900;
613      break;
614    case PPC_IRQ_RESERVED_A:
615      Offset = 0x00a00;
616      break;
617    case PPC_IRQ_RESERVED_B:
618      Offset = 0x00b00;
619      break;
620    case PPC_IRQ_SCALL:
621      Offset = 0x00c00;
622      break;
623    case PPC_IRQ_TRACE:
624      Offset = 0x00d00;
625      break;
626    case PPC_IRQ_FP_ASST:
627      Offset = 0x00e00;
628      break;
629
630#if defined(ppc403) || defined(ppc405)
631
632/*  PPC_IRQ_CRIT is the same vector as PPC_IRQ_RESET
633    case PPC_IRQ_CRIT:
634      Offset = 0x00100;
635      break;
636*/
637    case PPC_IRQ_PIT:
638      Offset = 0x01000;
639      break;
640    case PPC_IRQ_FIT:
641      Offset = 0x01010;
642      break;
643    case PPC_IRQ_WATCHDOG:
644      Offset = 0x01020;
645      break;
646    case PPC_IRQ_DEBUG:
647      Offset = 0x02000;
648      break;
649
650#elif defined(ppc601)
651    case PPC_IRQ_TRACE:
652      Offset = 0x02000;
653      break;
654
655#elif defined(ppc603)
656    case PPC_IRQ_TRANS_MISS:
657      Offset = 0x1000;
658      break;
659    case PPC_IRQ_DATA_LOAD:
660      Offset = 0x1100;
661      break;
662    case PPC_IRQ_DATA_STORE:
663      Offset = 0x1200;
664      break;
665    case PPC_IRQ_ADDR_BRK:
666      Offset = 0x1300;
667      break;
668    case PPC_IRQ_SYS_MGT:
669      Offset = 0x1400;
670      break;
671
672#elif defined(ppc603e)
673    case PPC_TLB_INST_MISS:
674      Offset = 0x1000;
675      break;
676    case PPC_TLB_LOAD_MISS:
677      Offset = 0x1100;
678      break;
679    case PPC_TLB_STORE_MISS:
680      Offset = 0x1200;
681      break;
682    case PPC_IRQ_ADDRBRK:
683      Offset = 0x1300;
684      break;
685    case PPC_IRQ_SYS_MGT:
686      Offset = 0x1400;
687      break;
688
689#elif defined(mpc604)
690    case PPC_IRQ_ADDR_BRK:
691      Offset = 0x1300;
692      break;
693    case PPC_IRQ_SYS_MGT:
694      Offset = 0x1400;
695      break;
696
697#elif defined(mpc860) || defined(mpc821)
698    case PPC_IRQ_EMULATE:
699      Offset = 0x1000;
700      break;
701    case PPC_IRQ_INST_MISS:
702      Offset = 0x1100;
703      break;
704    case PPC_IRQ_DATA_MISS:
705      Offset = 0x1200;
706      break;
707    case PPC_IRQ_INST_ERR:
708      Offset = 0x1300;
709      break;
710    case PPC_IRQ_DATA_ERR:
711      Offset = 0x1400;
712      break;
713    case PPC_IRQ_DATA_BPNT:
714      Offset = 0x1c00;
715      break;
716    case PPC_IRQ_INST_BPNT:
717      Offset = 0x1d00;
718      break;
719    case PPC_IRQ_IO_BPNT:
720      Offset = 0x1e00;
721      break;
722    case PPC_IRQ_DEV_PORT:
723      Offset = 0x1f00;
724      break;
725    case PPC_IRQ_IRQ0:
726      Offset = 0x2000;
727      break;
728    case PPC_IRQ_LVL0:
729      Offset = 0x2040;
730      break;
731    case PPC_IRQ_IRQ1:
732      Offset = 0x2080;
733      break;
734    case PPC_IRQ_LVL1:
735      Offset = 0x20c0;
736      break;
737    case PPC_IRQ_IRQ2:
738      Offset = 0x2100;
739      break;
740    case PPC_IRQ_LVL2:
741      Offset = 0x2140;
742      break;
743    case PPC_IRQ_IRQ3:
744      Offset = 0x2180;
745      break;
746    case PPC_IRQ_LVL3:
747      Offset = 0x21c0;
748      break;
749    case PPC_IRQ_IRQ4:
750      Offset = 0x2200;
751      break;
752    case PPC_IRQ_LVL4:
753      Offset = 0x2240;
754      break;
755    case PPC_IRQ_IRQ5:
756      Offset = 0x2280;
757      break;
758    case PPC_IRQ_LVL5:
759      Offset = 0x22c0;
760      break;
761    case PPC_IRQ_IRQ6:
762      Offset = 0x2300;
763      break;
764    case PPC_IRQ_LVL6:
765      Offset = 0x2340;
766      break;
767    case PPC_IRQ_IRQ7:
768      Offset = 0x2380;
769      break;
770    case PPC_IRQ_LVL7:
771      Offset = 0x23c0;
772      break;
773    case PPC_IRQ_CPM_ERROR:
774      Offset = 0x2400;
775      break;
776    case PPC_IRQ_CPM_PC4:
777      Offset = 0x2410;
778      break;
779    case PPC_IRQ_CPM_PC5:
780      Offset = 0x2420;
781      break;
782    case PPC_IRQ_CPM_SMC2:
783      Offset = 0x2430;
784      break;
785    case PPC_IRQ_CPM_SMC1:
786      Offset = 0x2440;
787      break;
788    case PPC_IRQ_CPM_SPI:
789      Offset = 0x2450;
790      break;
791    case PPC_IRQ_CPM_PC6:
792      Offset = 0x2460;
793      break;
794    case PPC_IRQ_CPM_TIMER4:
795      Offset = 0x2470;
796      break;
797    case PPC_IRQ_CPM_RESERVED_8:
798      Offset = 0x2480;
799      break;
800    case PPC_IRQ_CPM_PC7:
801      Offset = 0x2490;
802      break;
803    case PPC_IRQ_CPM_PC8:
804      Offset = 0x24a0;
805      break;
806    case PPC_IRQ_CPM_PC9:
807      Offset = 0x24b0;
808      break;
809    case PPC_IRQ_CPM_TIMER3:
810      Offset = 0x24c0;
811      break;
812    case PPC_IRQ_CPM_RESERVED_D:
813      Offset = 0x24d0;
814      break;
815    case PPC_IRQ_CPM_PC10:
816      Offset = 0x24e0;
817      break;
818    case PPC_IRQ_CPM_PC11:
819      Offset = 0x24f0;
820      break;
821    case PPC_IRQ_CPM_I2C:
822      Offset = 0x2500;
823      break;
824    case PPC_IRQ_CPM_RISC_TIMER:
825      Offset = 0x2510;
826      break;
827    case PPC_IRQ_CPM_TIMER2:
828      Offset = 0x2520;
829      break;
830    case PPC_IRQ_CPM_RESERVED_13:
831      Offset = 0x2530;
832      break;
833    case PPC_IRQ_CPM_IDMA2:
834      Offset = 0x2540;
835      break;
836    case PPC_IRQ_CPM_IDMA1:
837      Offset = 0x2550;
838      break;
839    case PPC_IRQ_CPM_SDMA_ERROR:
840      Offset = 0x2560;
841      break;
842    case PPC_IRQ_CPM_PC12:
843      Offset = 0x2570;
844      break;
845    case PPC_IRQ_CPM_PC13:
846      Offset = 0x2580;
847      break;
848    case PPC_IRQ_CPM_TIMER1:
849      Offset = 0x2590;
850      break;
851    case PPC_IRQ_CPM_PC14:
852      Offset = 0x25a0;
853      break;
854    case PPC_IRQ_CPM_SCC4:
855      Offset = 0x25b0;
856      break;
857    case PPC_IRQ_CPM_SCC3:
858      Offset = 0x25c0;
859      break;
860    case PPC_IRQ_CPM_SCC2:
861      Offset = 0x25d0;
862      break;
863    case PPC_IRQ_CPM_SCC1:
864      Offset = 0x25e0;
865      break;
866    case PPC_IRQ_CPM_PC15:
867      Offset = 0x25f0;
868      break;
869#endif
870
871  }
872  Top += Offset;
873  return Top;
874}
875
876/*PAGE
877 *
878 *  This is the PowerPC specific implementation of the routine which
879 *  returns TRUE if an interrupt is in progress.
880 *
881 *  NOTE: This is the same as the generic version. But since the
882 *        PowerPC is still supporting old and new exception processing
883 *        models and the new exception processing model has a hardware
884 *        way of doing this, we have to provide this capability here
885 *        for symmetry.
886 */
887
888boolean _ISR_Is_in_progress( void )
889{
890  return (_ISR_Nest_level != 0);
891}
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