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source: rtems/c/src/lib/libbsp/powerpc/support/old_exception_processing/cpu.c @ bde9bb5

4.104.114.84.95

Last change on this file since bde9bb5 was 5e67b98, checked in by Joel Sherrill <joel.sherrill@…>, on 01/03/01 at 16:45:52

2001-01-03 Joel Sherrill <joel@…>

new_exception_processing/cpu.h, old_exception_processing/cpu.c: old_exception_processing/cpu.h, Added _CPU_Initialize_vectors(). In particular, spurious vector initialization had to be moved on old exception processing model.

Property mode set to 100644

File size: 20.6 KB

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1	/*
2	* PowerPC CPU Dependent Source
3	*
4	* Author: Andrew Bray <andy@i-cubed.co.uk>
5	*
6	* COPYRIGHT (c) 1995 by i-cubed ltd.
7	*
8	* To anyone who acknowledges that this file is provided "AS IS"
9	* without any express or implied warranty:
10	* permission to use, copy, modify, and distribute this file
11	* for any purpose is hereby granted without fee, provided that
12	* the above copyright notice and this notice appears in all
13	* copies, and that the name of i-cubed limited not be used in
14	* advertising or publicity pertaining to distribution of the
15	* software without specific, written prior permission.
16	* i-cubed limited makes no representations about the suitability
17	* of this software for any purpose.
18	*
19	* Derived from c/src/exec/cpu/no_cpu/cpu.c:
20	*
21	* COPYRIGHT (c) 1989-1997.
22	* On-Line Applications Research Corporation (OAR).
23	* Copyright assigned to U.S. Government, 1994.
24	*
25	* The license and distribution terms for this file may be found in
26	* the file LICENSE in this distribution or at
27	* http://www.OARcorp.com/rtems/license.html.
28	*
29	* $Id$
30	*/
31
32	#include <rtems/system.h>
33	#include <rtems/score/isr.h>
34	#include <rtems/score/context.h>
35	#include <rtems/score/thread.h>
36	#include <rtems/score/interr.h>
37
38	/*
39	* These are for testing purposes.
40	*/
41
42	/* _CPU_Initialize
43	*
44	* This routine performs processor dependent initialization.
45	*
46	* INPUT PARAMETERS:
47	* cpu_table - CPU table to initialize
48	* thread_dispatch - address of disptaching routine
49	*/
50
51	static void ppc_spurious(int, CPU_Interrupt_frame *);
52
53	int _CPU_spurious_count = 0;
54	int _CPU_last_spurious = 0;
55
56	void _CPU_Initialize(
57	rtems_cpu_table *cpu_table,
58	void (thread_dispatch) / ignored on this CPU */
59	)
60	{
61	int i;
62	#if (PPC_ABI != PPC_ABI_POWEROPEN)
63	register unsigned32 r2 = 0;
64	#if (PPC_ABI != PPC_ABI_GCC27)
65	register unsigned32 r13 = 0;
66
67	asm ("mr %0,13" : "=r" ((r13)) : "0" ((r13)));
68	_CPU_IRQ_info.Default_r13 = r13;
69	#endif
70
71	asm ("mr %0,2" : "=r" ((r2)) : "0" ((r2)));
72	_CPU_IRQ_info.Default_r2 = r2;
73	#endif
74
75	_CPU_IRQ_info.Nest_level = &_ISR_Nest_level;
76	_CPU_IRQ_info.Disable_level = &_Thread_Dispatch_disable_level;
77	/* fill in _CPU_IRQ_info.Vector_table later */
78	#if (PPC_ABI == PPC_ABI_POWEROPEN)
79	_CPU_IRQ_info.Dispatch_r2 = ((unsigned32 *)_Thread_Dispatch)[1];
80	#endif
81	_CPU_IRQ_info.Switch_necessary = &_Context_Switch_necessary;
82	_CPU_IRQ_info.Signal = &_ISR_Signals_to_thread_executing;
83
84	#if (PPC_USE_SPRG)
85	i = (int)&_CPU_IRQ_info;
86	asm volatile("mtspr 0x113, %0" : "=r" (i) : "0" (i)); /* SPRG 3 */
87	#endif
88
89	/*
90	* Store Msr Value in the IRQ info structure.
91	*/
92	_CPU_MSR_Value(_CPU_IRQ_info.msr_initial);
93
94	#if (PPC_USE_SPRG)
95	i = _CPU_IRQ_info.msr_initial;
96	asm volatile("mtspr 0x112, %0" : "=r" (i) : "0" (i)); /* SPRG 2 */
97	#endif
98
99	_CPU_Table = *cpu_table;
100	}
101
102	/*
103	* _CPU_Initialize_vectors()
104	*
105	* Support routine to initialize the RTEMS vector table after it is allocated.
106	*
107	* PowerPC Specific Information:
108	*
109	* Complete initialization since the table is now allocated.
110	*/
111
112	void _CPU_Initialize_vectors(void)
113	{
114	int i;
115	proc_ptr handler = (proc_ptr)ppc_spurious;
116
117	_CPU_IRQ_info.Vector_table = _ISR_Vector_table;
118
119	if ( _CPU_Table.spurious_handler )
120	handler = (proc_ptr)_CPU_Table.spurious_handler;
121
122	for (i = 0; i < PPC_INTERRUPT_MAX; i++)
123	_ISR_Vector_table[i] = handler;
124
125	}
126
127	/*PAGE
128	*
129	* _CPU_ISR_Calculate_level
130	*
131	* The PowerPC puts its interrupt enable status in the MSR register
132	* which also contains things like endianness control. To be more
133	* awkward, the layout varies from processor to processor. This
134	* is why it was necessary to adopt a scheme which allowed the user
135	* to specify specifically which interrupt sources were enabled.
136	*/
137
138	unsigned32 _CPU_ISR_Calculate_level(
139	unsigned32 new_level
140	)
141	{
142	register unsigned32 new_msr = 0;
143
144	/*
145	* Set the critical interrupt enable bit
146	*/
147
148	#if (PPC_HAS_RFCI)
149	if ( !(new_level & PPC_INTERRUPT_LEVEL_CE) )
150	new_msr \|= PPC_MSR_CE;
151	#endif
152
153	if ( !(new_level & PPC_INTERRUPT_LEVEL_ME) )
154	new_msr \|= PPC_MSR_ME;
155
156	if ( !(new_level & PPC_INTERRUPT_LEVEL_EE) )
157	new_msr \|= PPC_MSR_EE;
158
159	return new_msr;
160	}
161
162	/*PAGE
163	*
164	* _CPU_ISR_Set_level
165	*
166	* This routine sets the requested level in the MSR.
167	*/
168
169	void _CPU_ISR_Set_level(
170	unsigned32 new_level
171	)
172	{
173	register unsigned32 tmp = 0;
174	register unsigned32 new_msr;
175
176	new_msr = _CPU_ISR_Calculate_level( new_level );
177
178	asm volatile (
179	"mfmsr %0; andc %0,%0,%1; and %2, %2, %1; or %0, %0, %2; mtmsr %0" :
180	"=&r" ((tmp)) :
181	"r" ((PPC_MSR_DISABLE_MASK)), "r" ((new_msr)), "0" ((tmp))
182	);
183	}
184
185	/*PAGE
186	*
187	* _CPU_ISR_Get_level
188	*
189	* This routine gets the current interrupt level from the MSR and
190	* converts it to an RTEMS interrupt level.
191	*/
192
193	unsigned32 _CPU_ISR_Get_level( void )
194	{
195	unsigned32 level = 0;
196	unsigned32 msr;
197
198	asm volatile("mfmsr %0" : "=r" ((msr)));
199
200	msr &= PPC_MSR_DISABLE_MASK;
201
202	/*
203	* Set the critical interrupt enable bit
204	*/
205
206	#if (PPC_HAS_RFCI)
207	if ( !(msr & PPC_MSR_CE) )
208	level \|= PPC_INTERRUPT_LEVEL_CE;
209	#endif
210
211	if ( !(msr & PPC_MSR_ME) )
212	level \|= PPC_INTERRUPT_LEVEL_ME;
213
214	if ( !(msr & PPC_MSR_EE) )
215	level \|= PPC_INTERRUPT_LEVEL_EE;
216
217	return level;
218	}
219
220	/*PAGE
221	*
222	* _CPU_Context_Initialize
223	*/
224
225	#if (PPC_ABI == PPC_ABI_POWEROPEN)
226	#define CPU_MINIMUM_STACK_FRAME_SIZE 56
227	#else /* PPC_ABI_SVR4 or PPC_ABI_EABI */
228	#define CPU_MINIMUM_STACK_FRAME_SIZE 8
229	#endif
230
231	void _CPU_Context_Initialize(
232	Context_Control *the_context,
233	unsigned32 *stack_base,
234	unsigned32 size,
235	unsigned32 new_level,
236	void *entry_point,
237	boolean is_fp
238	)
239	{
240	unsigned32 msr_value;
241	unsigned32 sp;
242
243	sp = (unsigned32)stack_base + size - CPU_MINIMUM_STACK_FRAME_SIZE;
244	((unsigned32 )sp) = 0;
245	the_context->gpr1 = sp;
246
247	the_context->msr = _CPU_ISR_Calculate_level( new_level );
248
249	/*
250	* The FP bit of the MSR should only be enabled if this is a floating
251	* point task. Unfortunately, the vfprintf_r routine in newlib
252	* ends up pushing a floating point register regardless of whether or
253	* not a floating point number is being printed. Serious restructuring
254	* of vfprintf.c will be required to avoid this behavior. At this
255	* time (7 July 1997), this restructuring is not being done.
256	*/
257
258	/if ( is_fp ) /
259	the_context->msr \|= PPC_MSR_FP;
260
261	/*
262	* Calculate the task's MSR value:
263	*
264	* + Set the exception prefix bit to point to the exception table
265	* + Force the RI bit
266	* + Use the DR and IR bits
267	*/
268	_CPU_MSR_Value( msr_value );
269	the_context->msr \|= (msr_value & PPC_MSR_EP);
270	the_context->msr \|= PPC_MSR_RI;
271	the_context->msr \|= msr_value & (PPC_MSR_DR\|PPC_MSR_IR);
272
273	#if (PPC_ABI == PPC_ABI_POWEROPEN)
274	{ unsigned32 desc = (unsigned32 )entry_point;
275
276	the_context->pc = desc[0];
277	the_context->gpr2 = desc[1];
278	}
279	#endif
280
281	#if (PPC_ABI == PPC_ABI_SVR4)
282	{ unsigned r13 = 0;
283	asm volatile ("mr %0, 13" : "=r" ((r13)));
284
285	the_context->pc = (unsigned32)entry_point;
286	the_context->gpr13 = r13;
287	}
288	#endif
289
290	#if (PPC_ABI == PPC_ABI_EABI)
291	{ unsigned32 r2 = 0;
292	unsigned r13 = 0;
293	asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13)));
294
295	the_context->pc = (unsigned32)entry_point;
296	the_context->gpr2 = r2;
297	the_context->gpr13 = r13;
298	}
299	#endif
300	}
301
302
303	/* _CPU_ISR_install_vector
304	*
305	* This kernel routine installs the RTEMS handler for the
306	* specified vector.
307	*
308	* Input parameters:
309	* vector - interrupt vector number
310	* old_handler - former ISR for this vector number
311	* new_handler - replacement ISR for this vector number
312	*
313	* Output parameters: NONE
314	*
315	*/
316
317	void _CPU_ISR_install_vector(
318	unsigned32 vector,
319	proc_ptr new_handler,
320	proc_ptr *old_handler
321	)
322	{
323	proc_ptr ignored;
324	*old_handler = _ISR_Vector_table[ vector ];
325
326	/*
327	* If the interrupt vector table is a table of pointer to isr entry
328	* points, then we need to install the appropriate RTEMS interrupt
329	* handler for this vector number.
330	*/
331
332	/*
333	* Install the wrapper so this ISR can be invoked properly.
334	*/
335	if (_CPU_Table.exceptions_in_RAM)
336	_CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
337
338	/*
339	* We put the actual user ISR address in '_ISR_vector_table'. This will
340	* be used by the _ISR_Handler so the user gets control.
341	*/
342
343	_ISR_Vector_table[ vector ] = new_handler ? (ISR_Handler_entry)new_handler :
344	_CPU_Table.spurious_handler ?
345	(ISR_Handler_entry)_CPU_Table.spurious_handler :
346	(ISR_Handler_entry)ppc_spurious;
347	}
348
349	/*PAGE
350	*
351	* _CPU_Install_interrupt_stack
352	*/
353
354	void _CPU_Install_interrupt_stack( void )
355	{
356	#if (PPC_ABI == PPC_ABI_POWEROPEN \|\| PPC_ABI == PPC_ABI_GCC27)
357	_CPU_IRQ_info.Stack = _CPU_Interrupt_stack_high - 56;
358	#else
359	_CPU_IRQ_info.Stack = _CPU_Interrupt_stack_high - 8;
360	#endif
361	}
362
363	/* Handle a spurious interrupt */
364	static void ppc_spurious(int v, CPU_Interrupt_frame *i)
365	{
366	#if 0
367	printf("Spurious interrupt on vector %d from %08.8x\n",
368	v, i->pc);
369	#endif
370	#ifdef ppc403
371	if (v == PPC_IRQ_EXTERNAL)
372	{
373	register int r = 0;
374
375	asm volatile("mtdcr 0x42, %0" :
376	"=&r" ((r)) : "0" ((r))); /* EXIER */
377	}
378	else if (v == PPC_IRQ_PIT)
379	{
380	register int r = 0x08000000;
381
382	asm volatile("mtspr 0x3d8, %0" :
383	"=&r" ((r)) : "0" ((r))); /* TSR */
384	}
385	else if (v == PPC_IRQ_FIT)
386	{
387	register int r = 0x04000000;
388
389	asm volatile("mtspr 0x3d8, %0" :
390	"=&r" ((r)) : "0" ((r))); /* TSR */
391	}
392	#endif
393	++_CPU_spurious_count;
394	_CPU_last_spurious = v;
395	}
396
397	void _CPU_Fatal_error(unsigned32 _error)
398	{
399	asm volatile ("mr 3, %0" : : "r" ((_error)));
400	asm volatile ("tweq 5,5");
401	asm volatile ("li 0,0; mtmsr 0");
402	while (1) ;
403	}
404
405	#define PPC_SYNCHRONOUS_TRAP_BIT_MASK 0x100
406	#define PPC_ASYNCHRONOUS_TRAP( _trap ) (_trap)
407	#define PPC_SYNCHRONOUS_TRAP ( _trap ) ((_trap)+PPC_SYNCHRONOUS_TRAP_BIT_MASK)
408	#define PPC_REAL_TRAP_NUMBER ( _trap ) ((_trap)%PPC_SYNCHRONOUS_TRAP_BIT_MASK)
409
410
411	const CPU_Trap_table_entry _CPU_Trap_slot_template = {
412
413	#if (PPC_ABI == PPC_ABI_POWEROPEN \|\| PPC_ABI == PPC_ABI_GCC27)
414	#error " Vector install not tested."
415	#if (PPC_HAS_FPU)
416	#error " Vector install not tested."
417	0x9421feb0, /* stwu r1, -(204 + 188 + IP_END)(r1) */
418	#else
419	#error " Vector install not tested."
420	0x9421ff40, /* stwu r1, -(204 + IP_END)(r1) /
421	#endif
422	#else
423	0x9421ff90, /* stwu r1, -(IP_END)(r1) */
424	#endif
425
426	0x90010008, /* stw %r0, IP_0(%r1) */
427	0x38000000, /* li %r0, PPC_IRQ */
428	0x48000002 /* ba PROC (_ISR_Handler) */
429	};
430
431	#if defined(mpc860) \|\| defined(mpc821)
432	const CPU_Trap_table_entry _CPU_Trap_slot_template_m860 = {
433	0x7c0803ac, /* mtlr %r0 */
434	0x81210028, /* lwz %r9, IP_9(%r1) */
435	0x38000000, /* li %r0, PPC_IRQ */
436	0x48000002 /* b PROC (_ISR_Handler) */
437	};
438	#endif /* mpc860 */
439
440	unsigned32 ppc_exception_vector_addr(
441	unsigned32 vector
442	);
443
444
445	/*PAGE
446	*
447	* _CPU_ISR_install_raw_handler
448	*
449	* This routine installs the specified handler as a "raw" non-executive
450	* supported trap handler (a.k.a. interrupt service routine).
451	*
452	* Input Parameters:
453	* vector - trap table entry number plus synchronous
454	* vs. asynchronous information
455	* new_handler - address of the handler to be installed
456	* old_handler - pointer to an address of the handler previously installed
457	*
458	* Output Parameters: NONE
459	* *new_handler - address of the handler previously installed
460	*
461	* NOTE:
462	*
463	* This routine is based on the SPARC routine _CPU_ISR_install_raw_handler.
464	* Install a software trap handler as an executive interrupt handler
465	* (which is desirable since RTEMS takes care of window and register issues),
466	* then the executive needs to know that the return address is to the trap
467	* rather than the instruction following the trap.
468	*
469	*/
470
471	void _CPU_ISR_install_raw_handler(
472	unsigned32 vector,
473	proc_ptr new_handler,
474	proc_ptr *old_handler
475	)
476	{
477	unsigned32 real_vector;
478	CPU_Trap_table_entry *slot;
479	unsigned32 u32_handler=0;
480
481	/*
482	* Get the "real" trap number for this vector ignoring the synchronous
483	* versus asynchronous indicator included with our vector numbers.
484	*/
485
486	real_vector = vector;
487
488	/*
489	* Get the current base address of the trap table and calculate a pointer
490	* to the slot we are interested in.
491	*/
492	slot = (CPU_Trap_table_entry *)ppc_exception_vector_addr( real_vector );
493
494	/*
495	* Get the address of the old_handler from the trap table.
496	*
497	* NOTE: The old_handler returned will be bogus if it does not follow
498	* the RTEMS model.
499	*/
500
501	#define HIGH_BITS_MASK 0xFFFFFC00
502	#define HIGH_BITS_SHIFT 10
503	#define LOW_BITS_MASK 0x000003FF
504
505	if (slot->stwu_r1 == _CPU_Trap_slot_template.stwu_r1) {
506	/*
507	* Set u32_handler = to target address
508	*/
509	u32_handler = slot->b_Handler & 0x03fffffc;
510
511	/* IMD FIX: sign extend address fragment... */
512	if (u32_handler & 0x02000000) {
513	u32_handler \|= 0xfc000000;
514	}
515
516	*old_handler = (proc_ptr) u32_handler;
517	} else
518	/* There are two kinds of handlers for the MPC860. One is the 'standard'
519	* one like above. The other is for the cascaded interrupts from the SIU
520	* and CPM. Therefore we must check for the alternate one if the standard
521	* one is not present
522	*/
523	#if defined(mpc860) \|\| defined(mpc821)
524	if (slot->stwu_r1 == _CPU_Trap_slot_template_m860.stwu_r1) {
525	/*
526	* Set u32_handler = to target address
527	*/
528	u32_handler = slot->b_Handler & 0x03fffffc;
529	*old_handler = (proc_ptr) u32_handler;
530	} else
531	#endif /* mpc860 */
532
533	*old_handler = 0;
534
535	/*
536	* Copy the template to the slot and then fix it.
537	*/
538	#if defined(mpc860) \|\| defined(mpc821)
539	if (vector >= PPC_IRQ_IRQ0)
540	*slot = _CPU_Trap_slot_template_m860;
541	else
542	#endif /* mpc860 */
543	*slot = _CPU_Trap_slot_template;
544
545	u32_handler = (unsigned32) new_handler;
546
547	/*
548	* IMD FIX: insert address fragment only (bits 6..29)
549	* therefore check for proper address range
550	* and remove unwanted bits
551	*/
552	if ((u32_handler & 0xfc000000) == 0xfc000000) {
553	u32_handler &= ~0xfc000000;
554	}
555	else if ((u32_handler & 0xfc000000) != 0x00000000) {
556	_Internal_error_Occurred(INTERNAL_ERROR_CORE,
557	TRUE,
558	u32_handler);
559	}
560
561	slot->b_Handler \|= u32_handler;
562
563	slot->li_r0_IRQ \|= vector;
564
565	_CPU_Data_Cache_Block_Flush( slot );
566	}
567
568	unsigned32 ppc_exception_vector_addr(
569	unsigned32 vector
570	)
571	{
572	#if (!PPC_HAS_EVPR)
573	unsigned32 Msr;
574	#endif
575	unsigned32 Top = 0;
576	unsigned32 Offset = 0x000;
577
578	#if (PPC_HAS_EXCEPTION_PREFIX)
579	_CPU_MSR_Value ( Msr );
580	if ( ( Msr & PPC_MSR_EP) != 0 ) /* Vectors at FFFx_xxxx */
581	Top = 0xfff00000;
582	#elif (PPC_HAS_EVPR)
583	asm volatile( "mfspr %0,0x3d6" : "=r" (Top)); /* EVPR */
584	Top = Top & 0xffff0000;
585	#endif
586
587	switch ( vector ) {
588	case PPC_IRQ_SYSTEM_RESET: /* on 40x aka PPC_IRQ_CRIT */
589	Offset = 0x00100;
590	break;
591	case PPC_IRQ_MCHECK:
592	Offset = 0x00200;
593	break;
594	case PPC_IRQ_PROTECT:
595	Offset = 0x00300;
596	break;
597	case PPC_IRQ_ISI:
598	Offset = 0x00400;
599	break;
600	case PPC_IRQ_EXTERNAL:
601	Offset = 0x00500;
602	break;
603	case PPC_IRQ_ALIGNMENT:
604	Offset = 0x00600;
605	break;
606	case PPC_IRQ_PROGRAM:
607	Offset = 0x00700;
608	break;
609	case PPC_IRQ_NOFP:
610	Offset = 0x00800;
611	break;
612	case PPC_IRQ_DECREMENTER:
613	Offset = 0x00900;
614	break;
615	case PPC_IRQ_RESERVED_A:
616	Offset = 0x00a00;
617	break;
618	case PPC_IRQ_RESERVED_B:
619	Offset = 0x00b00;
620	break;
621	case PPC_IRQ_SCALL:
622	Offset = 0x00c00;
623	break;
624	case PPC_IRQ_TRACE:
625	Offset = 0x00d00;
626	break;
627	case PPC_IRQ_FP_ASST:
628	Offset = 0x00e00;
629	break;
630
631	#if defined(ppc403)
632
633	/* PPC_IRQ_CRIT is the same vector as PPC_IRQ_RESET
634	case PPC_IRQ_CRIT:
635	Offset = 0x00100;
636	break;
637	*/
638	case PPC_IRQ_PIT:
639	Offset = 0x01000;
640	break;
641	case PPC_IRQ_FIT:
642	Offset = 0x01010;
643	break;
644	case PPC_IRQ_WATCHDOG:
645	Offset = 0x01020;
646	break;
647	case PPC_IRQ_DEBUG:
648	Offset = 0x02000;
649	break;
650
651	#elif defined(ppc601)
652	case PPC_IRQ_TRACE:
653	Offset = 0x02000;
654	break;
655
656	#elif defined(ppc603)
657	case PPC_IRQ_TRANS_MISS:
658	Offset = 0x1000;
659	break;
660	case PPC_IRQ_DATA_LOAD:
661	Offset = 0x1100;
662	break;
663	case PPC_IRQ_DATA_STORE:
664	Offset = 0x1200;
665	break;
666	case PPC_IRQ_ADDR_BRK:
667	Offset = 0x1300;
668	break;
669	case PPC_IRQ_SYS_MGT:
670	Offset = 0x1400;
671	break;
672
673	#elif defined(ppc603e)
674	case PPC_TLB_INST_MISS:
675	Offset = 0x1000;
676	break;
677	case PPC_TLB_LOAD_MISS:
678	Offset = 0x1100;
679	break;
680	case PPC_TLB_STORE_MISS:
681	Offset = 0x1200;
682	break;
683	case PPC_IRQ_ADDRBRK:
684	Offset = 0x1300;
685	break;
686	case PPC_IRQ_SYS_MGT:
687	Offset = 0x1400;
688	break;
689
690	#elif defined(mpc604)
691	case PPC_IRQ_ADDR_BRK:
692	Offset = 0x1300;
693	break;
694	case PPC_IRQ_SYS_MGT:
695	Offset = 0x1400;
696	break;
697
698	#elif defined(mpc860) \|\| defined(mpc821)
699	case PPC_IRQ_EMULATE:
700	Offset = 0x1000;
701	break;
702	case PPC_IRQ_INST_MISS:
703	Offset = 0x1100;
704	break;
705	case PPC_IRQ_DATA_MISS:
706	Offset = 0x1200;
707	break;
708	case PPC_IRQ_INST_ERR:
709	Offset = 0x1300;
710	break;
711	case PPC_IRQ_DATA_ERR:
712	Offset = 0x1400;
713	break;
714	case PPC_IRQ_DATA_BPNT:
715	Offset = 0x1c00;
716	break;
717	case PPC_IRQ_INST_BPNT:
718	Offset = 0x1d00;
719	break;
720	case PPC_IRQ_IO_BPNT:
721	Offset = 0x1e00;
722	break;
723	case PPC_IRQ_DEV_PORT:
724	Offset = 0x1f00;
725	break;
726	case PPC_IRQ_IRQ0:
727	Offset = 0x2000;
728	break;
729	case PPC_IRQ_LVL0:
730	Offset = 0x2040;
731	break;
732	case PPC_IRQ_IRQ1:
733	Offset = 0x2080;
734	break;
735	case PPC_IRQ_LVL1:
736	Offset = 0x20c0;
737	break;
738	case PPC_IRQ_IRQ2:
739	Offset = 0x2100;
740	break;
741	case PPC_IRQ_LVL2:
742	Offset = 0x2140;
743	break;
744	case PPC_IRQ_IRQ3:
745	Offset = 0x2180;
746	break;
747	case PPC_IRQ_LVL3:
748	Offset = 0x21c0;
749	break;
750	case PPC_IRQ_IRQ4:
751	Offset = 0x2200;
752	break;
753	case PPC_IRQ_LVL4:
754	Offset = 0x2240;
755	break;
756	case PPC_IRQ_IRQ5:
757	Offset = 0x2280;
758	break;
759	case PPC_IRQ_LVL5:
760	Offset = 0x22c0;
761	break;
762	case PPC_IRQ_IRQ6:
763	Offset = 0x2300;
764	break;
765	case PPC_IRQ_LVL6:
766	Offset = 0x2340;
767	break;
768	case PPC_IRQ_IRQ7:
769	Offset = 0x2380;
770	break;
771	case PPC_IRQ_LVL7:
772	Offset = 0x23c0;
773	break;
774	case PPC_IRQ_CPM_ERROR:
775	Offset = 0x2400;
776	break;
777	case PPC_IRQ_CPM_PC4:
778	Offset = 0x2410;
779	break;
780	case PPC_IRQ_CPM_PC5:
781	Offset = 0x2420;
782	break;
783	case PPC_IRQ_CPM_SMC2:
784	Offset = 0x2430;
785	break;
786	case PPC_IRQ_CPM_SMC1:
787	Offset = 0x2440;
788	break;
789	case PPC_IRQ_CPM_SPI:
790	Offset = 0x2450;
791	break;
792	case PPC_IRQ_CPM_PC6:
793	Offset = 0x2460;
794	break;
795	case PPC_IRQ_CPM_TIMER4:
796	Offset = 0x2470;
797	break;
798	case PPC_IRQ_CPM_RESERVED_8:
799	Offset = 0x2480;
800	break;
801	case PPC_IRQ_CPM_PC7:
802	Offset = 0x2490;
803	break;
804	case PPC_IRQ_CPM_PC8:
805	Offset = 0x24a0;
806	break;
807	case PPC_IRQ_CPM_PC9:
808	Offset = 0x24b0;
809	break;
810	case PPC_IRQ_CPM_TIMER3:
811	Offset = 0x24c0;
812	break;
813	case PPC_IRQ_CPM_RESERVED_D:
814	Offset = 0x24d0;
815	break;
816	case PPC_IRQ_CPM_PC10:
817	Offset = 0x24e0;
818	break;
819	case PPC_IRQ_CPM_PC11:
820	Offset = 0x24f0;
821	break;
822	case PPC_IRQ_CPM_I2C:
823	Offset = 0x2500;
824	break;
825	case PPC_IRQ_CPM_RISC_TIMER:
826	Offset = 0x2510;
827	break;
828	case PPC_IRQ_CPM_TIMER2:
829	Offset = 0x2520;
830	break;
831	case PPC_IRQ_CPM_RESERVED_13:
832	Offset = 0x2530;
833	break;
834	case PPC_IRQ_CPM_IDMA2:
835	Offset = 0x2540;
836	break;
837	case PPC_IRQ_CPM_IDMA1:
838	Offset = 0x2550;
839	break;
840	case PPC_IRQ_CPM_SDMA_ERROR:
841	Offset = 0x2560;
842	break;
843	case PPC_IRQ_CPM_PC12:
844	Offset = 0x2570;
845	break;
846	case PPC_IRQ_CPM_PC13:
847	Offset = 0x2580;
848	break;
849	case PPC_IRQ_CPM_TIMER1:
850	Offset = 0x2590;
851	break;
852	case PPC_IRQ_CPM_PC14:
853	Offset = 0x25a0;
854	break;
855	case PPC_IRQ_CPM_SCC4:
856	Offset = 0x25b0;
857	break;
858	case PPC_IRQ_CPM_SCC3:
859	Offset = 0x25c0;
860	break;
861	case PPC_IRQ_CPM_SCC2:
862	Offset = 0x25d0;
863	break;
864	case PPC_IRQ_CPM_SCC1:
865	Offset = 0x25e0;
866	break;
867	case PPC_IRQ_CPM_PC15:
868	Offset = 0x25f0;
869	break;
870	#endif
871
872	}
873	Top += Offset;
874	return Top;
875	}
876

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