source: rtems/c/src/lib/libbsp/powerpc/support/new_exception_processing/cpu.h @ 48694da

4.104.114.84.95
Last change on this file since 48694da was 48694da, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 22, 2001 at 1:46:37 PM

2001-10-22 Andy Dachs <a.dachs@…>

  • Makefile.am, README, configure.ac, new_exception_processing/cpu.h, shared/include/cpu.h, shared/include/cpuIdent.c, shared/src/cache.c: Added mpc8260 support.
  • Property mode set to 100644
File size: 31.5 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the PowerPC
4 *  processor.
5 *
6 *  Modified for MPC8260 Andy Dachs <a.dachs@sstl.co.uk>
7 *  Surrey Satellite Technology Limited (SSTL), 2001
8 *
9 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
10 *
11 *  COPYRIGHT (c) 1995 by i-cubed ltd.
12 *
13 *  To anyone who acknowledges that this file is provided "AS IS"
14 *  without any express or implied warranty:
15 *      permission to use, copy, modify, and distribute this file
16 *      for any purpose is hereby granted without fee, provided that
17 *      the above copyright notice and this notice appears in all
18 *      copies, and that the name of i-cubed limited not be used in
19 *      advertising or publicity pertaining to distribution of the
20 *      software without specific, written prior permission.
21 *      i-cubed limited makes no representations about the suitability
22 *      of this software for any purpose.
23 *
24 *  Derived from c/src/exec/cpu/no_cpu/cpu.h:
25 *
26 *  COPYRIGHT (c) 1989-1997.
27 *  On-Line Applications Research Corporation (OAR).
28 *
29 *  The license and distribution terms for this file may be found in
30 *  the file LICENSE in this distribution or at
31 *  http://www.OARcorp.com/rtems/license.html.
32 *
33 *  $Id$
34 */
35
36#ifndef __CPU_h
37#define __CPU_h
38
39#ifdef __cplusplus
40extern "C" {
41#endif
42
43#include <rtems/score/ppc.h>               /* pick up machine definitions */
44#include <libcpu/cpu.h>
45 
46#ifndef ASM
47#include <rtems/score/ppctypes.h>
48#endif
49
50/* conditional compilation parameters */
51
52/*
53 *  Should the calls to _Thread_Enable_dispatch be inlined?
54 *
55 *  If TRUE, then they are inlined.
56 *  If FALSE, then a subroutine call is made.
57 *
58 *  Basically this is an example of the classic trade-off of size
59 *  versus speed.  Inlining the call (TRUE) typically increases the
60 *  size of RTEMS while speeding up the enabling of dispatching.
61 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
62 *  only be 0 or 1 unless you are in an interrupt handler and that
63 *  interrupt handler invokes the executive.]  When not inlined
64 *  something calls _Thread_Enable_dispatch which in turns calls
65 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
66 *  one subroutine call is avoided entirely.]
67 */
68
69#define CPU_INLINE_ENABLE_DISPATCH       FALSE
70
71/*
72 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
73 *  be unrolled one time?  In unrolled each iteration of the loop examines
74 *  two "nodes" on the chain being searched.  Otherwise, only one node
75 *  is examined per iteration.
76 *
77 *  If TRUE, then the loops are unrolled.
78 *  If FALSE, then the loops are not unrolled.
79 *
80 *  The primary factor in making this decision is the cost of disabling
81 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
82 *  body of the loop.  On some CPUs, the flash is more expensive than
83 *  one iteration of the loop body.  In this case, it might be desirable
84 *  to unroll the loop.  It is important to note that on some CPUs, this
85 *  code is the longest interrupt disable period in RTEMS.  So it is
86 *  necessary to strike a balance when setting this parameter.
87 */
88
89#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
90
91/*
92 *  Does RTEMS manage a dedicated interrupt stack in software?
93 *
94 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
95 *  If FALSE, nothing is done.
96 *
97 *  If the CPU supports a dedicated interrupt stack in hardware,
98 *  then it is generally the responsibility of the BSP to allocate it
99 *  and set it up.
100 *
101 *  If the CPU does not support a dedicated interrupt stack, then
102 *  the porter has two options: (1) execute interrupts on the
103 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
104 *  interrupt stack.
105 *
106 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
107 *
108 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
109 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
110 *  possible that both are FALSE for a particular CPU.  Although it
111 *  is unclear what that would imply about the interrupt processing
112 *  procedure on that CPU.
113 */
114
115#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
116
117/*
118 *  Does this CPU have hardware support for a dedicated interrupt stack?
119 *
120 *  If TRUE, then it must be installed during initialization.
121 *  If FALSE, then no installation is performed.
122 *
123 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
124 *
125 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
126 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
127 *  possible that both are FALSE for a particular CPU.  Although it
128 *  is unclear what that would imply about the interrupt processing
129 *  procedure on that CPU.
130 */
131
132#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
133
134/*
135 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
136 *
137 *  If TRUE, then the memory is allocated during initialization.
138 *  If FALSE, then the memory is allocated during initialization.
139 *
140 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
141 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
142 */
143
144#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
145
146/*
147 *  Does the RTEMS invoke the user's ISR with the vector number and
148 *  a pointer to the saved interrupt frame (1) or just the vector
149 *  number (0)?
150 */
151
152#define CPU_ISR_PASSES_FRAME_POINTER 0
153
154/*
155 *  Does the CPU have hardware floating point?
156 *
157 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
158 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
159 *
160 *  If there is a FP coprocessor such as the i387 or mc68881, then
161 *  the answer is TRUE.
162 *
163 *  The macro name "PPC_HAS_FPU" should be made CPU specific.
164 *  It indicates whether or not this CPU model has FP support.  For
165 *  example, it would be possible to have an i386_nofp CPU model
166 *  which set this to false to indicate that you have an i386 without
167 *  an i387 and wish to leave floating point support out of RTEMS.
168 */
169
170#if ( PPC_HAS_FPU == 1 )
171#define CPU_HARDWARE_FP     TRUE
172#else
173#define CPU_HARDWARE_FP     FALSE
174#endif
175
176/*
177 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
178 *
179 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
180 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
181 *
182 *  So far, the only CPU in which this option has been used is the
183 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
184 *  floating point registers to perform integer multiplies.  If
185 *  a function which you would not think utilize the FP unit DOES,
186 *  then one can not easily predict which tasks will use the FP hardware.
187 *  In this case, this option should be TRUE.
188 *
189 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
190 */
191
192#define CPU_ALL_TASKS_ARE_FP     FALSE
193
194/*
195 *  Should the IDLE task have a floating point context?
196 *
197 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
198 *  and it has a floating point context which is switched in and out.
199 *  If FALSE, then the IDLE task does not have a floating point context.
200 *
201 *  Setting this to TRUE negatively impacts the time required to preempt
202 *  the IDLE task from an interrupt because the floating point context
203 *  must be saved as part of the preemption.
204 */
205
206#define CPU_IDLE_TASK_IS_FP      FALSE
207
208/*
209 *  Should the saving of the floating point registers be deferred
210 *  until a context switch is made to another different floating point
211 *  task?
212 *
213 *  If TRUE, then the floating point context will not be stored until
214 *  necessary.  It will remain in the floating point registers and not
215 *  disturned until another floating point task is switched to.
216 *
217 *  If FALSE, then the floating point context is saved when a floating
218 *  point task is switched out and restored when the next floating point
219 *  task is restored.  The state of the floating point registers between
220 *  those two operations is not specified.
221 *
222 *  If the floating point context does NOT have to be saved as part of
223 *  interrupt dispatching, then it should be safe to set this to TRUE.
224 *
225 *  Setting this flag to TRUE results in using a different algorithm
226 *  for deciding when to save and restore the floating point context.
227 *  The deferred FP switch algorithm minimizes the number of times
228 *  the FP context is saved and restored.  The FP context is not saved
229 *  until a context switch is made to another, different FP task.
230 *  Thus in a system with only one FP task, the FP context will never
231 *  be saved or restored.
232 */
233/*
234 *  ACB Note:  This could make debugging tricky..
235 */
236
237#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
238
239/*
240 *  Does this port provide a CPU dependent IDLE task implementation?
241 *
242 *  If TRUE, then the routine _CPU_Thread_Idle_body
243 *  must be provided and is the default IDLE thread body instead of
244 *  _CPU_Thread_Idle_body.
245 *
246 *  If FALSE, then use the generic IDLE thread body if the BSP does
247 *  not provide one.
248 *
249 *  This is intended to allow for supporting processors which have
250 *  a low power or idle mode.  When the IDLE thread is executed, then
251 *  the CPU can be powered down.
252 *
253 *  The order of precedence for selecting the IDLE thread body is:
254 *
255 *    1.  BSP provided
256 *    2.  CPU dependent (if provided)
257 *    3.  generic (if no BSP and no CPU dependent)
258 */
259
260#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
261
262
263/*
264 *  Does the stack grow up (toward higher addresses) or down
265 *  (toward lower addresses)?
266 *
267 *  If TRUE, then the grows upward.
268 *  If FALSE, then the grows toward smaller addresses.
269 */
270
271#define CPU_STACK_GROWS_UP               FALSE
272
273/*
274 *  The following is the variable attribute used to force alignment
275 *  of critical RTEMS structures.  On some processors it may make
276 *  sense to have these aligned on tighter boundaries than
277 *  the minimum requirements of the compiler in order to have as
278 *  much of the critical data area as possible in a cache line.
279 *
280 *  The placement of this macro in the declaration of the variables
281 *  is based on the syntactically requirements of the GNU C
282 *  "__attribute__" extension.  For example with GNU C, use
283 *  the following to force a structures to a 32 byte boundary.
284 *
285 *      __attribute__ ((aligned (32)))
286 *
287 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
288 *         To benefit from using this, the data must be heavily
289 *         used so it will stay in the cache and used frequently enough
290 *         in the executive to justify turning this on.
291 */
292
293#define CPU_STRUCTURE_ALIGNMENT \
294  __attribute__ ((aligned (PPC_CACHE_ALIGNMENT)))
295
296/*
297 *  Define what is required to specify how the network to host conversion
298 *  routines are handled.
299 */
300
301#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
302#define CPU_BIG_ENDIAN                           TRUE
303#define CPU_LITTLE_ENDIAN                        FALSE
304
305
306/*
307 *  Processor defined structures
308 *
309 *  Examples structures include the descriptor tables from the i386
310 *  and the processor control structure on the i960ca.
311 */
312
313/* may need to put some structures here.  */
314
315/*
316 * Contexts
317 *
318 *  Generally there are 2 types of context to save.
319 *     1. Interrupt registers to save
320 *     2. Task level registers to save
321 *
322 *  This means we have the following 3 context items:
323 *     1. task level context stuff::  Context_Control
324 *     2. floating point task stuff:: Context_Control_fp
325 *     3. special interrupt level context :: Context_Control_interrupt
326 *
327 *  On some processors, it is cost-effective to save only the callee
328 *  preserved registers during a task context switch.  This means
329 *  that the ISR code needs to save those registers which do not
330 *  persist across function calls.  It is not mandatory to make this
331 *  distinctions between the caller/callee saves registers for the
332 *  purpose of minimizing context saved during task switch and on interrupts.
333 *  If the cost of saving extra registers is minimal, simplicity is the
334 *  choice.  Save the same context on interrupt entry as for tasks in
335 *  this case.
336 *
337 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
338 *  care should be used in designing the context area.
339 *
340 *  On some CPUs with hardware floating point support, the Context_Control_fp
341 *  structure will not be used or it simply consist of an array of a
342 *  fixed number of bytes.   This is done when the floating point context
343 *  is dumped by a "FP save context" type instruction and the format
344 *  is not really defined by the CPU.  In this case, there is no need
345 *  to figure out the exact format -- only the size.  Of course, although
346 *  this is enough information for RTEMS, it is probably not enough for
347 *  a debugger such as gdb.  But that is another problem.
348 */
349
350#ifndef ASM
351
352typedef struct {
353    unsigned32 gpr1;    /* Stack pointer for all */
354    unsigned32 gpr2;    /* TOC in PowerOpen, reserved SVR4, section ptr EABI + */
355    unsigned32 gpr13;   /* First non volatile PowerOpen, section ptr SVR4/EABI */
356    unsigned32 gpr14;   /* Non volatile for all */
357    unsigned32 gpr15;   /* Non volatile for all */
358    unsigned32 gpr16;   /* Non volatile for all */
359    unsigned32 gpr17;   /* Non volatile for all */
360    unsigned32 gpr18;   /* Non volatile for all */
361    unsigned32 gpr19;   /* Non volatile for all */
362    unsigned32 gpr20;   /* Non volatile for all */
363    unsigned32 gpr21;   /* Non volatile for all */
364    unsigned32 gpr22;   /* Non volatile for all */
365    unsigned32 gpr23;   /* Non volatile for all */
366    unsigned32 gpr24;   /* Non volatile for all */
367    unsigned32 gpr25;   /* Non volatile for all */
368    unsigned32 gpr26;   /* Non volatile for all */
369    unsigned32 gpr27;   /* Non volatile for all */
370    unsigned32 gpr28;   /* Non volatile for all */
371    unsigned32 gpr29;   /* Non volatile for all */
372    unsigned32 gpr30;   /* Non volatile for all */
373    unsigned32 gpr31;   /* Non volatile for all */
374    unsigned32 cr;      /* PART of the CR is non volatile for all */
375    unsigned32 pc;      /* Program counter/Link register */
376    unsigned32 msr;     /* Initial interrupt level */
377} Context_Control;
378
379typedef struct {
380    /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over
381     * procedure calls.  However, this would mean that the interrupt
382     * frame had to hold f0-f13, and the fpscr.  And as the majority
383     * of tasks will not have an FP context, we will save the whole
384     * context here.
385     */
386#if (PPC_HAS_DOUBLE == 1)
387    double      f[32];
388    double      fpscr;
389#else
390    float       f[32];
391    float       fpscr;
392#endif
393} Context_Control_fp;
394
395typedef struct CPU_Interrupt_frame {
396    unsigned32 stacklink;       /* Ensure this is a real frame (also reg1 save) */
397    unsigned32 calleeLr;        /* link register used by callees: SVR4/EABI */
398  /* This is what is left out of the primary contexts */
399    unsigned32 gpr0;
400    unsigned32 gpr2;            /* play safe */
401    unsigned32 gpr3;
402    unsigned32 gpr4;
403    unsigned32 gpr5;
404    unsigned32 gpr6;
405    unsigned32 gpr7;
406    unsigned32 gpr8;
407    unsigned32 gpr9;
408    unsigned32 gpr10;
409    unsigned32 gpr11;
410    unsigned32 gpr12;
411    unsigned32 gpr13;   /* Play safe */
412    unsigned32 gpr28;   /* For internal use by the IRQ handler */
413    unsigned32 gpr29;   /* For internal use by the IRQ handler */
414    unsigned32 gpr30;   /* For internal use by the IRQ handler */
415    unsigned32 gpr31;   /* For internal use by the IRQ handler */
416    unsigned32 cr;      /* Bits of this are volatile, so no-one may save */
417    unsigned32 ctr;
418    unsigned32 xer;
419    unsigned32 lr;
420    unsigned32 pc;
421    unsigned32 msr;
422    unsigned32 pad[3];
423} CPU_Interrupt_frame;
424 
425/*
426 *  The following table contains the information required to configure
427 *  the PowerPC processor specific parameters.
428 */
429
430typedef struct {
431  void       (*pretasking_hook)( void );
432  void       (*predriver_hook)( void );
433  void       (*postdriver_hook)( void );
434  void       (*idle_task)( void );
435  boolean      do_zero_of_workspace;
436  unsigned32   idle_task_stack_size;
437  unsigned32   interrupt_stack_size;
438  unsigned32   extra_mpci_receive_server_stack;
439  void *     (*stack_allocate_hook)( unsigned32 );
440  void       (*stack_free_hook)( void* );
441  /* end of fields required on all CPUs */
442
443  unsigned32   clicks_per_usec;        /* Timer clicks per microsecond */
444  boolean      exceptions_in_RAM;     /* TRUE if in RAM */
445
446#if (defined(ppc403) || defined(mpc860) || defined(mpc821) || defined(mpc8260))
447  unsigned32   serial_per_sec;         /* Serial clocks per second */
448  boolean      serial_external_clock;
449  boolean      serial_xon_xoff;
450  boolean      serial_cts_rts;
451  unsigned32   serial_rate;
452  unsigned32   timer_average_overhead; /* Average overhead of timer in ticks */
453  unsigned32   timer_least_valid;      /* Least valid number from timer      */
454  boolean      timer_internal_clock;   /* TRUE, when timer runs with CPU clk */
455#endif
456
457#if (defined(mpc860) || defined(mpc821) || defined( mpc8260))
458  unsigned32   clock_speed;            /* Speed of CPU in Hz */
459#endif
460}   rtems_cpu_table;
461
462/*
463 *  Macros to access required entires in the CPU Table are in
464 *  the file rtems/system.h.
465 */
466
467/*
468 *  Macros to access PowerPC MPC750 specific additions to the CPU Table
469 */
470
471#define rtems_cpu_configuration_get_clicks_per_usec() \
472   (_CPU_Table.clicks_per_usec)
473
474#define rtems_cpu_configuration_get_exceptions_in_ram() \
475   (_CPU_Table.exceptions_in_RAM)
476
477/*
478 *  This variable is optional.  It is used on CPUs on which it is difficult
479 *  to generate an "uninitialized" FP context.  It is filled in by
480 *  _CPU_Initialize and copied into the task's FP context area during
481 *  _CPU_Context_Initialize.
482 */
483
484/* EXTERN Context_Control_fp  _CPU_Null_fp_context; */
485
486/*
487 *  On some CPUs, RTEMS supports a software managed interrupt stack.
488 *  This stack is allocated by the Interrupt Manager and the switch
489 *  is performed in _ISR_Handler.  These variables contain pointers
490 *  to the lowest and highest addresses in the chunk of memory allocated
491 *  for the interrupt stack.  Since it is unknown whether the stack
492 *  grows up or down (in general), this give the CPU dependent
493 *  code the option of picking the version it wants to use.
494 *
495 *  NOTE: These two variables are required if the macro
496 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
497 */
498
499SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
500SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
501
502#endif /* ndef ASM */
503
504/*
505 *  This defines the number of levels and the mask used to pick those
506 *  bits out of a thread mode.
507 */
508
509#define CPU_MODES_INTERRUPT_LEVEL  0x00000001 /* interrupt level in mode */
510#define CPU_MODES_INTERRUPT_MASK   0x00000001 /* interrupt level in mode */
511
512/*
513 *  With some compilation systems, it is difficult if not impossible to
514 *  call a high-level language routine from assembly language.  This
515 *  is especially true of commercial Ada compilers and name mangling
516 *  C++ ones.  This variable can be optionally defined by the CPU porter
517 *  and contains the address of the routine _Thread_Dispatch.  This
518 *  can make it easier to invoke that routine at the end of the interrupt
519 *  sequence (if a dispatch is necessary).
520 */
521
522/* EXTERN void           (*_CPU_Thread_dispatch_pointer)(); */
523
524/*
525 *  Nothing prevents the porter from declaring more CPU specific variables.
526 */
527
528#ifndef ASM
529 
530SCORE_EXTERN struct {
531  unsigned32 *Disable_level;
532  void *Stack;
533  volatile boolean *Switch_necessary;
534  boolean *Signal;
535
536} _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT;
537
538#endif /* ndef ASM */
539
540/*
541 *  The size of the floating point context area.  On some CPUs this
542 *  will not be a "sizeof" because the format of the floating point
543 *  area is not defined -- only the size is.  This is usually on
544 *  CPUs with a "floating point save context" instruction.
545 */
546
547#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
548
549/*
550 * (Optional) # of bytes for libmisc/stackchk to check
551 * If not specifed, then it defaults to something reasonable
552 * for most architectures.
553 */
554
555#define CPU_STACK_CHECK_SIZE    (128)
556
557/*
558 *  Amount of extra stack (above minimum stack size) required by
559 *  MPCI receive server thread.  Remember that in a multiprocessor
560 *  system this thread must exist and be able to process all directives.
561 */
562
563#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
564
565/*
566 *  This defines the number of entries in the ISR_Vector_table managed
567 *  by RTEMS.
568 */
569
570#define CPU_INTERRUPT_NUMBER_OF_VECTORS     (PPC_INTERRUPT_MAX)
571#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (PPC_INTERRUPT_MAX - 1)
572
573/*
574 *  Should be large enough to run all RTEMS tests.  This insures
575 *  that a "reasonable" small application should not have any problems.
576 */
577
578#define CPU_STACK_MINIMUM_SIZE          (1024*8)
579
580/*
581 *  CPU's worst alignment requirement for data types on a byte boundary.  This
582 *  alignment does not take into account the requirements for the stack.
583 */
584
585#define CPU_ALIGNMENT              (PPC_ALIGNMENT)
586
587/*
588 *  This number corresponds to the byte alignment requirement for the
589 *  heap handler.  This alignment requirement may be stricter than that
590 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
591 *  common for the heap to follow the same alignment requirement as
592 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
593 *  then this should be set to CPU_ALIGNMENT.
594 *
595 *  NOTE:  This does not have to be a power of 2.  It does have to
596 *         be greater or equal to than CPU_ALIGNMENT.
597 */
598
599#define CPU_HEAP_ALIGNMENT         (PPC_ALIGNMENT)
600
601/*
602 *  This number corresponds to the byte alignment requirement for memory
603 *  buffers allocated by the partition manager.  This alignment requirement
604 *  may be stricter than that for the data types alignment specified by
605 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
606 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
607 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
608 *
609 *  NOTE:  This does not have to be a power of 2.  It does have to
610 *         be greater or equal to than CPU_ALIGNMENT.
611 */
612
613#define CPU_PARTITION_ALIGNMENT    (PPC_ALIGNMENT)
614
615/*
616 *  This number corresponds to the byte alignment requirement for the
617 *  stack.  This alignment requirement may be stricter than that for the
618 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
619 *  is strict enough for the stack, then this should be set to 0.
620 *
621 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
622 */
623
624#define CPU_STACK_ALIGNMENT        (PPC_STACK_ALIGNMENT)
625
626/*
627 * Needed for Interrupt stack
628 */
629#define CPU_MINIMUM_STACK_FRAME_SIZE 8
630
631
632/*
633 *  ISR handler macros
634 */
635
636#define _CPU_Initialize_vectors()
637
638/*
639 *  Disable all interrupts for an RTEMS critical section.  The previous
640 *  level is returned in _isr_cookie.
641 */
642
643#define loc_string(a,b) a " (" #b ")\n"
644
645#ifndef ASM
646 
647static inline unsigned32 _CPU_ISR_Get_level( void )
648{
649  register unsigned int msr;
650  _CPU_MSR_GET(msr);
651  if (msr & MSR_EE) return 0;
652  else  return 1;
653}
654
655static inline void _CPU_ISR_Set_level( unsigned32 level )
656{
657  register unsigned int msr;
658  _CPU_MSR_GET(msr);
659  if (!(level & CPU_MODES_INTERRUPT_MASK)) {
660    msr |= MSR_EE;
661  }
662  else {
663    msr &= ~MSR_EE;
664  }
665  _CPU_MSR_SET(msr);
666}
667 
668#define _CPU_ISR_install_vector(irq, new, old) {BSP_panic("_CPU_ISR_install_vector called\n");}
669
670/* Context handler macros */
671
672/*
673 *  Initialize the context to a state suitable for starting a
674 *  task after a context restore operation.  Generally, this
675 *  involves:
676 *
677 *     - setting a starting address
678 *     - preparing the stack
679 *     - preparing the stack and frame pointers
680 *     - setting the proper interrupt level in the context
681 *     - initializing the floating point context
682 *
683 *  This routine generally does not set any unnecessary register
684 *  in the context.  The state of the "general data" registers is
685 *  undefined at task start time.
686 *
687 *  NOTE:  Implemented as a subroutine for the SPARC port.
688 */
689
690void _CPU_Context_Initialize(
691  Context_Control  *the_context,
692  unsigned32       *stack_base,
693  unsigned32        size,
694  unsigned32        new_level,
695  void             *entry_point,
696  boolean           is_fp
697);
698
699/*
700 *  This routine is responsible for somehow restarting the currently
701 *  executing task.  If you are lucky, then all that is necessary
702 *  is restoring the context.  Otherwise, there will need to be
703 *  a special assembly routine which does something special in this
704 *  case.  Context_Restore should work most of the time.  It will
705 *  not work if restarting self conflicts with the stack frame
706 *  assumptions of restoring a context.
707 */
708
709#define _CPU_Context_Restart_self( _the_context ) \
710   _CPU_Context_restore( (_the_context) );
711
712/*
713 *  The purpose of this macro is to allow the initial pointer into
714 *  a floating point context area (used to save the floating point
715 *  context) to be at an arbitrary place in the floating point
716 *  context area.
717 *
718 *  This is necessary because some FP units are designed to have
719 *  their context saved as a stack which grows into lower addresses.
720 *  Other FP units can be saved by simply moving registers into offsets
721 *  from the base of the context area.  Finally some FP units provide
722 *  a "dump context" instruction which could fill in from high to low
723 *  or low to high based on the whim of the CPU designers.
724 */
725
726#define _CPU_Context_Fp_start( _base, _offset ) \
727   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
728
729/*
730 *  This routine initializes the FP context area passed to it to.
731 *  There are a few standard ways in which to initialize the
732 *  floating point context.  The code included for this macro assumes
733 *  that this is a CPU in which a "initial" FP context was saved into
734 *  _CPU_Null_fp_context and it simply copies it to the destination
735 *  context passed to it.
736 *
737 *  Other models include (1) not doing anything, and (2) putting
738 *  a "null FP status word" in the correct place in the FP context.
739 */
740
741#define _CPU_Context_Initialize_fp( _destination ) \
742  { \
743   ((Context_Control_fp *) *((void **) _destination))->fpscr = PPC_INIT_FPSCR; \
744  }
745
746/* end of Context handler macros */
747
748/* Fatal Error manager macros */
749
750/*
751 *  This routine copies _error into a known place -- typically a stack
752 *  location or a register, optionally disables interrupts, and
753 *  halts/stops the CPU.
754 */
755
756#define _CPU_Fatal_halt( _error ) \
757  _BSP_Fatal_error(_error)
758
759/* end of Fatal Error manager macros */
760
761/* Bitfield handler macros */
762
763/*
764 *  This routine sets _output to the bit number of the first bit
765 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
766 *  This type may be either 16 or 32 bits wide although only the 16
767 *  least significant bits will be used.
768 *
769 *  There are a number of variables in using a "find first bit" type
770 *  instruction.
771 *
772 *    (1) What happens when run on a value of zero?
773 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
774 *    (3) The numbering may be zero or one based.
775 *    (4) The "find first bit" instruction may search from MSB or LSB.
776 *
777 *  RTEMS guarantees that (1) will never happen so it is not a concern.
778 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
779 *  _CPU_Priority_Bits_index().  These three form a set of routines
780 *  which must logically operate together.  Bits in the _value are
781 *  set and cleared based on masks built by _CPU_Priority_mask().
782 *  The basic major and minor values calculated by _Priority_Major()
783 *  and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index()
784 *  to properly range between the values returned by the "find first bit"
785 *  instruction.  This makes it possible for _Priority_Get_highest() to
786 *  calculate the major and directly index into the minor table.
787 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
788 *  is the first bit found.
789 *
790 *  This entire "find first bit" and mapping process depends heavily
791 *  on the manner in which a priority is broken into a major and minor
792 *  components with the major being the 4 MSB of a priority and minor
793 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
794 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
795 *  to the lowest priority.
796 *
797 *  If your CPU does not have a "find first bit" instruction, then
798 *  there are ways to make do without it.  Here are a handful of ways
799 *  to implement this in software:
800 *
801 *    - a series of 16 bit test instructions
802 *    - a "binary search using if's"
803 *    - _number = 0
804 *      if _value > 0x00ff
805 *        _value >>=8
806 *        _number = 8;
807 *
808 *      if _value > 0x0000f
809 *        _value >=8
810 *        _number += 4
811 *
812 *      _number += bit_set_table[ _value ]
813 *
814 *    where bit_set_table[ 16 ] has values which indicate the first
815 *      bit set
816 */
817
818#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
819  { \
820    asm volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \
821                  "1" ((_value))); \
822  }
823
824/* end of Bitfield handler macros */
825
826/*
827 *  This routine builds the mask which corresponds to the bit fields
828 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
829 *  for that routine.
830 */
831
832#define _CPU_Priority_Mask( _bit_number ) \
833  ( 0x80000000 >> (_bit_number) )
834
835/*
836 *  This routine translates the bit numbers returned by
837 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
838 *  a major or minor component of a priority.  See the discussion
839 *  for that routine.
840 */
841
842#define _CPU_Priority_bits_index( _priority ) \
843  (_priority)
844
845/* end of Priority handler macros */
846
847/* variables */
848
849extern const unsigned32 _CPU_msrs[4];
850
851/* functions */
852
853/*
854 *  _CPU_Initialize
855 *
856 *  This routine performs CPU dependent initialization.
857 */
858
859void _CPU_Initialize(
860  rtems_cpu_table  *cpu_table,
861  void            (*thread_dispatch)
862);
863
864
865/*
866 *  _CPU_Install_interrupt_stack
867 *
868 *  This routine installs the hardware interrupt stack pointer.
869 *
870 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
871 *         is TRUE.
872 */
873
874void _CPU_Install_interrupt_stack( void );
875
876/*
877 *  _CPU_Context_switch
878 *
879 *  This routine switches from the run context to the heir context.
880 */
881
882void _CPU_Context_switch(
883  Context_Control  *run,
884  Context_Control  *heir
885);
886
887/*
888 *  _CPU_Context_restore
889 *
890 *  This routine is generallu used only to restart self in an
891 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
892 *
893 *  NOTE: May be unnecessary to reload some registers.
894 */
895
896void _CPU_Context_restore(
897  Context_Control *new_context
898);
899
900/*
901 *  _CPU_Context_save_fp
902 *
903 *  This routine saves the floating point context passed to it.
904 */
905
906void _CPU_Context_save_fp(
907  void **fp_context_ptr
908);
909
910/*
911 *  _CPU_Context_restore_fp
912 *
913 *  This routine restores the floating point context passed to it.
914 */
915
916void _CPU_Context_restore_fp(
917  void **fp_context_ptr
918);
919
920void _CPU_Fatal_error(
921  unsigned32 _error
922);
923
924/*  The following routine swaps the endian format of an unsigned int.
925 *  It must be static because it is referenced indirectly.
926 *
927 *  This version will work on any processor, but if there is a better
928 *  way for your CPU PLEASE use it.  The most common way to do this is to:
929 *
930 *     swap least significant two bytes with 16-bit rotate
931 *     swap upper and lower 16-bits
932 *     swap most significant two bytes with 16-bit rotate
933 *
934 *  Some CPUs have special instructions which swap a 32-bit quantity in
935 *  a single instruction (e.g. i486).  It is probably best to avoid
936 *  an "endian swapping control bit" in the CPU.  One good reason is
937 *  that interrupts would probably have to be disabled to insure that
938 *  an interrupt does not try to access the same "chunk" with the wrong
939 *  endian.  Another good reason is that on some CPUs, the endian bit
940 *  endianness for ALL fetches -- both code and data -- so the code
941 *  will be fetched incorrectly.
942 */
943 
944static inline unsigned int CPU_swap_u32(
945  unsigned int value
946)
947{
948  unsigned32 swapped;
949 
950  asm volatile("rlwimi %0,%1,8,24,31;"
951               "rlwimi %0,%1,24,16,23;"
952               "rlwimi %0,%1,8,8,15;"
953               "rlwimi %0,%1,24,0,7;" :
954               "=&r" ((swapped)) : "r" ((value)));
955
956  return( swapped );
957}
958
959#define CPU_swap_u16( value ) \
960  (((value&0xff) << 8) | ((value >> 8)&0xff))
961
962#endif /* ndef ASM */
963
964#ifdef __cplusplus
965}
966#endif
967
968#endif
Note: See TracBrowser for help on using the repository browser.