1 | /* cpu.h |
---|
2 | * |
---|
3 | * This include file contains information pertaining to the PowerPC |
---|
4 | * processor. |
---|
5 | * |
---|
6 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
---|
7 | * |
---|
8 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
---|
9 | * |
---|
10 | * To anyone who acknowledges that this file is provided "AS IS" |
---|
11 | * without any express or implied warranty: |
---|
12 | * permission to use, copy, modify, and distribute this file |
---|
13 | * for any purpose is hereby granted without fee, provided that |
---|
14 | * the above copyright notice and this notice appears in all |
---|
15 | * copies, and that the name of i-cubed limited not be used in |
---|
16 | * advertising or publicity pertaining to distribution of the |
---|
17 | * software without specific, written prior permission. |
---|
18 | * i-cubed limited makes no representations about the suitability |
---|
19 | * of this software for any purpose. |
---|
20 | * |
---|
21 | * Derived from c/src/exec/cpu/no_cpu/cpu.h: |
---|
22 | * |
---|
23 | * COPYRIGHT (c) 1989-1997. |
---|
24 | * On-Line Applications Research Corporation (OAR). |
---|
25 | * |
---|
26 | * The license and distribution terms for this file may be found in |
---|
27 | * the file LICENSE in this distribution or at |
---|
28 | * http://www.OARcorp.com/rtems/license.html. |
---|
29 | * |
---|
30 | * $Id$ |
---|
31 | */ |
---|
32 | |
---|
33 | #ifndef __CPU_h |
---|
34 | #define __CPU_h |
---|
35 | |
---|
36 | #ifdef __cplusplus |
---|
37 | extern "C" { |
---|
38 | #endif |
---|
39 | |
---|
40 | #include <rtems/score/ppc.h> /* pick up machine definitions */ |
---|
41 | #include <libcpu/cpu.h> |
---|
42 | |
---|
43 | #ifndef ASM |
---|
44 | #include <rtems/score/ppctypes.h> |
---|
45 | #endif |
---|
46 | |
---|
47 | /* conditional compilation parameters */ |
---|
48 | |
---|
49 | /* |
---|
50 | * Should the calls to _Thread_Enable_dispatch be inlined? |
---|
51 | * |
---|
52 | * If TRUE, then they are inlined. |
---|
53 | * If FALSE, then a subroutine call is made. |
---|
54 | * |
---|
55 | * Basically this is an example of the classic trade-off of size |
---|
56 | * versus speed. Inlining the call (TRUE) typically increases the |
---|
57 | * size of RTEMS while speeding up the enabling of dispatching. |
---|
58 | * [NOTE: In general, the _Thread_Dispatch_disable_level will |
---|
59 | * only be 0 or 1 unless you are in an interrupt handler and that |
---|
60 | * interrupt handler invokes the executive.] When not inlined |
---|
61 | * something calls _Thread_Enable_dispatch which in turns calls |
---|
62 | * _Thread_Dispatch. If the enable dispatch is inlined, then |
---|
63 | * one subroutine call is avoided entirely.] |
---|
64 | */ |
---|
65 | |
---|
66 | #define CPU_INLINE_ENABLE_DISPATCH FALSE |
---|
67 | |
---|
68 | /* |
---|
69 | * Should the body of the search loops in _Thread_queue_Enqueue_priority |
---|
70 | * be unrolled one time? In unrolled each iteration of the loop examines |
---|
71 | * two "nodes" on the chain being searched. Otherwise, only one node |
---|
72 | * is examined per iteration. |
---|
73 | * |
---|
74 | * If TRUE, then the loops are unrolled. |
---|
75 | * If FALSE, then the loops are not unrolled. |
---|
76 | * |
---|
77 | * The primary factor in making this decision is the cost of disabling |
---|
78 | * and enabling interrupts (_ISR_Flash) versus the cost of rest of the |
---|
79 | * body of the loop. On some CPUs, the flash is more expensive than |
---|
80 | * one iteration of the loop body. In this case, it might be desirable |
---|
81 | * to unroll the loop. It is important to note that on some CPUs, this |
---|
82 | * code is the longest interrupt disable period in RTEMS. So it is |
---|
83 | * necessary to strike a balance when setting this parameter. |
---|
84 | */ |
---|
85 | |
---|
86 | #define CPU_UNROLL_ENQUEUE_PRIORITY FALSE |
---|
87 | |
---|
88 | /* |
---|
89 | * Does RTEMS manage a dedicated interrupt stack in software? |
---|
90 | * |
---|
91 | * If TRUE, then a stack is allocated in _ISR_Handler_initialization. |
---|
92 | * If FALSE, nothing is done. |
---|
93 | * |
---|
94 | * If the CPU supports a dedicated interrupt stack in hardware, |
---|
95 | * then it is generally the responsibility of the BSP to allocate it |
---|
96 | * and set it up. |
---|
97 | * |
---|
98 | * If the CPU does not support a dedicated interrupt stack, then |
---|
99 | * the porter has two options: (1) execute interrupts on the |
---|
100 | * stack of the interrupted task, and (2) have RTEMS manage a dedicated |
---|
101 | * interrupt stack. |
---|
102 | * |
---|
103 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
---|
104 | * |
---|
105 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
---|
106 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
---|
107 | * possible that both are FALSE for a particular CPU. Although it |
---|
108 | * is unclear what that would imply about the interrupt processing |
---|
109 | * procedure on that CPU. |
---|
110 | */ |
---|
111 | |
---|
112 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE |
---|
113 | |
---|
114 | /* |
---|
115 | * Does this CPU have hardware support for a dedicated interrupt stack? |
---|
116 | * |
---|
117 | * If TRUE, then it must be installed during initialization. |
---|
118 | * If FALSE, then no installation is performed. |
---|
119 | * |
---|
120 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
---|
121 | * |
---|
122 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
---|
123 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
---|
124 | * possible that both are FALSE for a particular CPU. Although it |
---|
125 | * is unclear what that would imply about the interrupt processing |
---|
126 | * procedure on that CPU. |
---|
127 | */ |
---|
128 | |
---|
129 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
---|
130 | |
---|
131 | /* |
---|
132 | * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? |
---|
133 | * |
---|
134 | * If TRUE, then the memory is allocated during initialization. |
---|
135 | * If FALSE, then the memory is allocated during initialization. |
---|
136 | * |
---|
137 | * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE |
---|
138 | * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. |
---|
139 | */ |
---|
140 | |
---|
141 | #define CPU_ALLOCATE_INTERRUPT_STACK FALSE |
---|
142 | |
---|
143 | /* |
---|
144 | * Does the RTEMS invoke the user's ISR with the vector number and |
---|
145 | * a pointer to the saved interrupt frame (1) or just the vector |
---|
146 | * number (0)? |
---|
147 | */ |
---|
148 | |
---|
149 | #define CPU_ISR_PASSES_FRAME_POINTER 0 |
---|
150 | |
---|
151 | /* |
---|
152 | * Does the CPU have hardware floating point? |
---|
153 | * |
---|
154 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. |
---|
155 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. |
---|
156 | * |
---|
157 | * If there is a FP coprocessor such as the i387 or mc68881, then |
---|
158 | * the answer is TRUE. |
---|
159 | * |
---|
160 | * The macro name "PPC_HAS_FPU" should be made CPU specific. |
---|
161 | * It indicates whether or not this CPU model has FP support. For |
---|
162 | * example, it would be possible to have an i386_nofp CPU model |
---|
163 | * which set this to false to indicate that you have an i386 without |
---|
164 | * an i387 and wish to leave floating point support out of RTEMS. |
---|
165 | */ |
---|
166 | |
---|
167 | #if ( PPC_HAS_FPU == 1 ) |
---|
168 | #define CPU_HARDWARE_FP TRUE |
---|
169 | #else |
---|
170 | #define CPU_HARDWARE_FP FALSE |
---|
171 | #endif |
---|
172 | |
---|
173 | /* |
---|
174 | * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? |
---|
175 | * |
---|
176 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. |
---|
177 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. |
---|
178 | * |
---|
179 | * So far, the only CPU in which this option has been used is the |
---|
180 | * HP PA-RISC. The HP C compiler and gcc both implicitly use the |
---|
181 | * floating point registers to perform integer multiplies. If |
---|
182 | * a function which you would not think utilize the FP unit DOES, |
---|
183 | * then one can not easily predict which tasks will use the FP hardware. |
---|
184 | * In this case, this option should be TRUE. |
---|
185 | * |
---|
186 | * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. |
---|
187 | */ |
---|
188 | |
---|
189 | #define CPU_ALL_TASKS_ARE_FP FALSE |
---|
190 | |
---|
191 | /* |
---|
192 | * Should the IDLE task have a floating point context? |
---|
193 | * |
---|
194 | * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task |
---|
195 | * and it has a floating point context which is switched in and out. |
---|
196 | * If FALSE, then the IDLE task does not have a floating point context. |
---|
197 | * |
---|
198 | * Setting this to TRUE negatively impacts the time required to preempt |
---|
199 | * the IDLE task from an interrupt because the floating point context |
---|
200 | * must be saved as part of the preemption. |
---|
201 | */ |
---|
202 | |
---|
203 | #define CPU_IDLE_TASK_IS_FP FALSE |
---|
204 | |
---|
205 | /* |
---|
206 | * Should the saving of the floating point registers be deferred |
---|
207 | * until a context switch is made to another different floating point |
---|
208 | * task? |
---|
209 | * |
---|
210 | * If TRUE, then the floating point context will not be stored until |
---|
211 | * necessary. It will remain in the floating point registers and not |
---|
212 | * disturned until another floating point task is switched to. |
---|
213 | * |
---|
214 | * If FALSE, then the floating point context is saved when a floating |
---|
215 | * point task is switched out and restored when the next floating point |
---|
216 | * task is restored. The state of the floating point registers between |
---|
217 | * those two operations is not specified. |
---|
218 | * |
---|
219 | * If the floating point context does NOT have to be saved as part of |
---|
220 | * interrupt dispatching, then it should be safe to set this to TRUE. |
---|
221 | * |
---|
222 | * Setting this flag to TRUE results in using a different algorithm |
---|
223 | * for deciding when to save and restore the floating point context. |
---|
224 | * The deferred FP switch algorithm minimizes the number of times |
---|
225 | * the FP context is saved and restored. The FP context is not saved |
---|
226 | * until a context switch is made to another, different FP task. |
---|
227 | * Thus in a system with only one FP task, the FP context will never |
---|
228 | * be saved or restored. |
---|
229 | */ |
---|
230 | /* |
---|
231 | * ACB Note: This could make debugging tricky.. |
---|
232 | */ |
---|
233 | |
---|
234 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
---|
235 | |
---|
236 | /* |
---|
237 | * Does this port provide a CPU dependent IDLE task implementation? |
---|
238 | * |
---|
239 | * If TRUE, then the routine _CPU_Thread_Idle_body |
---|
240 | * must be provided and is the default IDLE thread body instead of |
---|
241 | * _CPU_Thread_Idle_body. |
---|
242 | * |
---|
243 | * If FALSE, then use the generic IDLE thread body if the BSP does |
---|
244 | * not provide one. |
---|
245 | * |
---|
246 | * This is intended to allow for supporting processors which have |
---|
247 | * a low power or idle mode. When the IDLE thread is executed, then |
---|
248 | * the CPU can be powered down. |
---|
249 | * |
---|
250 | * The order of precedence for selecting the IDLE thread body is: |
---|
251 | * |
---|
252 | * 1. BSP provided |
---|
253 | * 2. CPU dependent (if provided) |
---|
254 | * 3. generic (if no BSP and no CPU dependent) |
---|
255 | */ |
---|
256 | |
---|
257 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
---|
258 | |
---|
259 | /* |
---|
260 | * Does the stack grow up (toward higher addresses) or down |
---|
261 | * (toward lower addresses)? |
---|
262 | * |
---|
263 | * If TRUE, then the grows upward. |
---|
264 | * If FALSE, then the grows toward smaller addresses. |
---|
265 | */ |
---|
266 | |
---|
267 | #define CPU_STACK_GROWS_UP FALSE |
---|
268 | |
---|
269 | /* |
---|
270 | * The following is the variable attribute used to force alignment |
---|
271 | * of critical RTEMS structures. On some processors it may make |
---|
272 | * sense to have these aligned on tighter boundaries than |
---|
273 | * the minimum requirements of the compiler in order to have as |
---|
274 | * much of the critical data area as possible in a cache line. |
---|
275 | * |
---|
276 | * The placement of this macro in the declaration of the variables |
---|
277 | * is based on the syntactically requirements of the GNU C |
---|
278 | * "__attribute__" extension. For example with GNU C, use |
---|
279 | * the following to force a structures to a 32 byte boundary. |
---|
280 | * |
---|
281 | * __attribute__ ((aligned (32))) |
---|
282 | * |
---|
283 | * NOTE: Currently only the Priority Bit Map table uses this feature. |
---|
284 | * To benefit from using this, the data must be heavily |
---|
285 | * used so it will stay in the cache and used frequently enough |
---|
286 | * in the executive to justify turning this on. |
---|
287 | */ |
---|
288 | |
---|
289 | #define CPU_STRUCTURE_ALIGNMENT \ |
---|
290 | __attribute__ ((aligned (PPC_CACHE_ALIGNMENT))) |
---|
291 | |
---|
292 | /* |
---|
293 | * Define what is required to specify how the network to host conversion |
---|
294 | * routines are handled. |
---|
295 | */ |
---|
296 | |
---|
297 | #define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE |
---|
298 | #define CPU_BIG_ENDIAN TRUE |
---|
299 | #define CPU_LITTLE_ENDIAN FALSE |
---|
300 | |
---|
301 | |
---|
302 | /* |
---|
303 | * Processor defined structures |
---|
304 | * |
---|
305 | * Examples structures include the descriptor tables from the i386 |
---|
306 | * and the processor control structure on the i960ca. |
---|
307 | */ |
---|
308 | |
---|
309 | /* may need to put some structures here. */ |
---|
310 | |
---|
311 | /* |
---|
312 | * Contexts |
---|
313 | * |
---|
314 | * Generally there are 2 types of context to save. |
---|
315 | * 1. Interrupt registers to save |
---|
316 | * 2. Task level registers to save |
---|
317 | * |
---|
318 | * This means we have the following 3 context items: |
---|
319 | * 1. task level context stuff:: Context_Control |
---|
320 | * 2. floating point task stuff:: Context_Control_fp |
---|
321 | * 3. special interrupt level context :: Context_Control_interrupt |
---|
322 | * |
---|
323 | * On some processors, it is cost-effective to save only the callee |
---|
324 | * preserved registers during a task context switch. This means |
---|
325 | * that the ISR code needs to save those registers which do not |
---|
326 | * persist across function calls. It is not mandatory to make this |
---|
327 | * distinctions between the caller/callee saves registers for the |
---|
328 | * purpose of minimizing context saved during task switch and on interrupts. |
---|
329 | * If the cost of saving extra registers is minimal, simplicity is the |
---|
330 | * choice. Save the same context on interrupt entry as for tasks in |
---|
331 | * this case. |
---|
332 | * |
---|
333 | * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then |
---|
334 | * care should be used in designing the context area. |
---|
335 | * |
---|
336 | * On some CPUs with hardware floating point support, the Context_Control_fp |
---|
337 | * structure will not be used or it simply consist of an array of a |
---|
338 | * fixed number of bytes. This is done when the floating point context |
---|
339 | * is dumped by a "FP save context" type instruction and the format |
---|
340 | * is not really defined by the CPU. In this case, there is no need |
---|
341 | * to figure out the exact format -- only the size. Of course, although |
---|
342 | * this is enough information for RTEMS, it is probably not enough for |
---|
343 | * a debugger such as gdb. But that is another problem. |
---|
344 | */ |
---|
345 | |
---|
346 | #ifndef ASM |
---|
347 | |
---|
348 | typedef struct { |
---|
349 | unsigned32 gpr1; /* Stack pointer for all */ |
---|
350 | unsigned32 gpr2; /* TOC in PowerOpen, reserved SVR4, section ptr EABI + */ |
---|
351 | unsigned32 gpr13; /* First non volatile PowerOpen, section ptr SVR4/EABI */ |
---|
352 | unsigned32 gpr14; /* Non volatile for all */ |
---|
353 | unsigned32 gpr15; /* Non volatile for all */ |
---|
354 | unsigned32 gpr16; /* Non volatile for all */ |
---|
355 | unsigned32 gpr17; /* Non volatile for all */ |
---|
356 | unsigned32 gpr18; /* Non volatile for all */ |
---|
357 | unsigned32 gpr19; /* Non volatile for all */ |
---|
358 | unsigned32 gpr20; /* Non volatile for all */ |
---|
359 | unsigned32 gpr21; /* Non volatile for all */ |
---|
360 | unsigned32 gpr22; /* Non volatile for all */ |
---|
361 | unsigned32 gpr23; /* Non volatile for all */ |
---|
362 | unsigned32 gpr24; /* Non volatile for all */ |
---|
363 | unsigned32 gpr25; /* Non volatile for all */ |
---|
364 | unsigned32 gpr26; /* Non volatile for all */ |
---|
365 | unsigned32 gpr27; /* Non volatile for all */ |
---|
366 | unsigned32 gpr28; /* Non volatile for all */ |
---|
367 | unsigned32 gpr29; /* Non volatile for all */ |
---|
368 | unsigned32 gpr30; /* Non volatile for all */ |
---|
369 | unsigned32 gpr31; /* Non volatile for all */ |
---|
370 | unsigned32 cr; /* PART of the CR is non volatile for all */ |
---|
371 | unsigned32 pc; /* Program counter/Link register */ |
---|
372 | unsigned32 msr; /* Initial interrupt level */ |
---|
373 | } Context_Control; |
---|
374 | |
---|
375 | typedef struct { |
---|
376 | /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over |
---|
377 | * procedure calls. However, this would mean that the interrupt |
---|
378 | * frame had to hold f0-f13, and the fpscr. And as the majority |
---|
379 | * of tasks will not have an FP context, we will save the whole |
---|
380 | * context here. |
---|
381 | */ |
---|
382 | #if (PPC_HAS_DOUBLE == 1) |
---|
383 | double f[32]; |
---|
384 | double fpscr; |
---|
385 | #else |
---|
386 | float f[32]; |
---|
387 | float fpscr; |
---|
388 | #endif |
---|
389 | } Context_Control_fp; |
---|
390 | |
---|
391 | typedef struct CPU_Interrupt_frame { |
---|
392 | unsigned32 stacklink; /* Ensure this is a real frame (also reg1 save) */ |
---|
393 | unsigned32 calleeLr; /* link register used by callees: SVR4/EABI */ |
---|
394 | /* This is what is left out of the primary contexts */ |
---|
395 | unsigned32 gpr0; |
---|
396 | unsigned32 gpr2; /* play safe */ |
---|
397 | unsigned32 gpr3; |
---|
398 | unsigned32 gpr4; |
---|
399 | unsigned32 gpr5; |
---|
400 | unsigned32 gpr6; |
---|
401 | unsigned32 gpr7; |
---|
402 | unsigned32 gpr8; |
---|
403 | unsigned32 gpr9; |
---|
404 | unsigned32 gpr10; |
---|
405 | unsigned32 gpr11; |
---|
406 | unsigned32 gpr12; |
---|
407 | unsigned32 gpr13; /* Play safe */ |
---|
408 | unsigned32 gpr28; /* For internal use by the IRQ handler */ |
---|
409 | unsigned32 gpr29; /* For internal use by the IRQ handler */ |
---|
410 | unsigned32 gpr30; /* For internal use by the IRQ handler */ |
---|
411 | unsigned32 gpr31; /* For internal use by the IRQ handler */ |
---|
412 | unsigned32 cr; /* Bits of this are volatile, so no-one may save */ |
---|
413 | unsigned32 ctr; |
---|
414 | unsigned32 xer; |
---|
415 | unsigned32 lr; |
---|
416 | unsigned32 pc; |
---|
417 | unsigned32 msr; |
---|
418 | unsigned32 pad[3]; |
---|
419 | } CPU_Interrupt_frame; |
---|
420 | |
---|
421 | /* |
---|
422 | * The following table contains the information required to configure |
---|
423 | * the PowerPC processor specific parameters. |
---|
424 | */ |
---|
425 | |
---|
426 | typedef struct { |
---|
427 | void (*pretasking_hook)( void ); |
---|
428 | void (*predriver_hook)( void ); |
---|
429 | void (*postdriver_hook)( void ); |
---|
430 | void (*idle_task)( void ); |
---|
431 | boolean do_zero_of_workspace; |
---|
432 | unsigned32 idle_task_stack_size; |
---|
433 | unsigned32 interrupt_stack_size; |
---|
434 | unsigned32 extra_mpci_receive_server_stack; |
---|
435 | void * (*stack_allocate_hook)( unsigned32 ); |
---|
436 | void (*stack_free_hook)( void* ); |
---|
437 | /* end of fields required on all CPUs */ |
---|
438 | |
---|
439 | unsigned32 clicks_per_usec; /* Timer clicks per microsecond */ |
---|
440 | boolean exceptions_in_RAM; /* TRUE if in RAM */ |
---|
441 | |
---|
442 | #if (defined(ppc403) || defined(mpc860) || defined(mpc821)) |
---|
443 | unsigned32 serial_per_sec; /* Serial clocks per second */ |
---|
444 | boolean serial_external_clock; |
---|
445 | boolean serial_xon_xoff; |
---|
446 | boolean serial_cts_rts; |
---|
447 | unsigned32 serial_rate; |
---|
448 | unsigned32 timer_average_overhead; /* Average overhead of timer in ticks */ |
---|
449 | unsigned32 timer_least_valid; /* Least valid number from timer */ |
---|
450 | boolean timer_internal_clock; /* TRUE, when timer runs with CPU clk */ |
---|
451 | #endif |
---|
452 | |
---|
453 | #if (defined(mpc860) || defined(mpc821)) |
---|
454 | unsigned32 clock_speed; /* Speed of CPU in Hz */ |
---|
455 | #endif |
---|
456 | } rtems_cpu_table; |
---|
457 | |
---|
458 | /* |
---|
459 | * Macros to access required entires in the CPU Table are in |
---|
460 | * the file rtems/system.h. |
---|
461 | */ |
---|
462 | |
---|
463 | /* |
---|
464 | * Macros to access PowerPC MPC750 specific additions to the CPU Table |
---|
465 | */ |
---|
466 | |
---|
467 | #define rtems_cpu_configuration_get_clicks_per_usec() \ |
---|
468 | (_CPU_Table.clicks_per_usec) |
---|
469 | |
---|
470 | #define rtems_cpu_configuration_get_exceptions_in_ram() \ |
---|
471 | (_CPU_Table.exceptions_in_RAM) |
---|
472 | |
---|
473 | /* |
---|
474 | * This variable is optional. It is used on CPUs on which it is difficult |
---|
475 | * to generate an "uninitialized" FP context. It is filled in by |
---|
476 | * _CPU_Initialize and copied into the task's FP context area during |
---|
477 | * _CPU_Context_Initialize. |
---|
478 | */ |
---|
479 | |
---|
480 | /* EXTERN Context_Control_fp _CPU_Null_fp_context; */ |
---|
481 | |
---|
482 | /* |
---|
483 | * On some CPUs, RTEMS supports a software managed interrupt stack. |
---|
484 | * This stack is allocated by the Interrupt Manager and the switch |
---|
485 | * is performed in _ISR_Handler. These variables contain pointers |
---|
486 | * to the lowest and highest addresses in the chunk of memory allocated |
---|
487 | * for the interrupt stack. Since it is unknown whether the stack |
---|
488 | * grows up or down (in general), this give the CPU dependent |
---|
489 | * code the option of picking the version it wants to use. |
---|
490 | * |
---|
491 | * NOTE: These two variables are required if the macro |
---|
492 | * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. |
---|
493 | */ |
---|
494 | |
---|
495 | SCORE_EXTERN void *_CPU_Interrupt_stack_low; |
---|
496 | SCORE_EXTERN void *_CPU_Interrupt_stack_high; |
---|
497 | |
---|
498 | #endif /* ndef ASM */ |
---|
499 | |
---|
500 | /* |
---|
501 | * This defines the number of levels and the mask used to pick those |
---|
502 | * bits out of a thread mode. |
---|
503 | */ |
---|
504 | |
---|
505 | #define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ |
---|
506 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ |
---|
507 | |
---|
508 | /* |
---|
509 | * With some compilation systems, it is difficult if not impossible to |
---|
510 | * call a high-level language routine from assembly language. This |
---|
511 | * is especially true of commercial Ada compilers and name mangling |
---|
512 | * C++ ones. This variable can be optionally defined by the CPU porter |
---|
513 | * and contains the address of the routine _Thread_Dispatch. This |
---|
514 | * can make it easier to invoke that routine at the end of the interrupt |
---|
515 | * sequence (if a dispatch is necessary). |
---|
516 | */ |
---|
517 | |
---|
518 | /* EXTERN void (*_CPU_Thread_dispatch_pointer)(); */ |
---|
519 | |
---|
520 | /* |
---|
521 | * Nothing prevents the porter from declaring more CPU specific variables. |
---|
522 | */ |
---|
523 | |
---|
524 | #ifndef ASM |
---|
525 | |
---|
526 | SCORE_EXTERN struct { |
---|
527 | unsigned32 *Disable_level; |
---|
528 | void *Stack; |
---|
529 | volatile boolean *Switch_necessary; |
---|
530 | boolean *Signal; |
---|
531 | |
---|
532 | } _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT; |
---|
533 | |
---|
534 | #endif /* ndef ASM */ |
---|
535 | |
---|
536 | /* |
---|
537 | * The size of the floating point context area. On some CPUs this |
---|
538 | * will not be a "sizeof" because the format of the floating point |
---|
539 | * area is not defined -- only the size is. This is usually on |
---|
540 | * CPUs with a "floating point save context" instruction. |
---|
541 | */ |
---|
542 | |
---|
543 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
---|
544 | |
---|
545 | /* |
---|
546 | * (Optional) # of bytes for libmisc/stackchk to check |
---|
547 | * If not specifed, then it defaults to something reasonable |
---|
548 | * for most architectures. |
---|
549 | */ |
---|
550 | |
---|
551 | #define CPU_STACK_CHECK_SIZE (128) |
---|
552 | |
---|
553 | /* |
---|
554 | * Amount of extra stack (above minimum stack size) required by |
---|
555 | * MPCI receive server thread. Remember that in a multiprocessor |
---|
556 | * system this thread must exist and be able to process all directives. |
---|
557 | */ |
---|
558 | |
---|
559 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
---|
560 | |
---|
561 | /* |
---|
562 | * This defines the number of entries in the ISR_Vector_table managed |
---|
563 | * by RTEMS. |
---|
564 | */ |
---|
565 | |
---|
566 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS (PPC_INTERRUPT_MAX) |
---|
567 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (PPC_INTERRUPT_MAX - 1) |
---|
568 | |
---|
569 | /* |
---|
570 | * Should be large enough to run all RTEMS tests. This insures |
---|
571 | * that a "reasonable" small application should not have any problems. |
---|
572 | */ |
---|
573 | |
---|
574 | #define CPU_STACK_MINIMUM_SIZE (1024*8) |
---|
575 | |
---|
576 | /* |
---|
577 | * CPU's worst alignment requirement for data types on a byte boundary. This |
---|
578 | * alignment does not take into account the requirements for the stack. |
---|
579 | */ |
---|
580 | |
---|
581 | #define CPU_ALIGNMENT (PPC_ALIGNMENT) |
---|
582 | |
---|
583 | /* |
---|
584 | * This number corresponds to the byte alignment requirement for the |
---|
585 | * heap handler. This alignment requirement may be stricter than that |
---|
586 | * for the data types alignment specified by CPU_ALIGNMENT. It is |
---|
587 | * common for the heap to follow the same alignment requirement as |
---|
588 | * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, |
---|
589 | * then this should be set to CPU_ALIGNMENT. |
---|
590 | * |
---|
591 | * NOTE: This does not have to be a power of 2. It does have to |
---|
592 | * be greater or equal to than CPU_ALIGNMENT. |
---|
593 | */ |
---|
594 | |
---|
595 | #define CPU_HEAP_ALIGNMENT (PPC_ALIGNMENT) |
---|
596 | |
---|
597 | /* |
---|
598 | * This number corresponds to the byte alignment requirement for memory |
---|
599 | * buffers allocated by the partition manager. This alignment requirement |
---|
600 | * may be stricter than that for the data types alignment specified by |
---|
601 | * CPU_ALIGNMENT. It is common for the partition to follow the same |
---|
602 | * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict |
---|
603 | * enough for the partition, then this should be set to CPU_ALIGNMENT. |
---|
604 | * |
---|
605 | * NOTE: This does not have to be a power of 2. It does have to |
---|
606 | * be greater or equal to than CPU_ALIGNMENT. |
---|
607 | */ |
---|
608 | |
---|
609 | #define CPU_PARTITION_ALIGNMENT (PPC_ALIGNMENT) |
---|
610 | |
---|
611 | /* |
---|
612 | * This number corresponds to the byte alignment requirement for the |
---|
613 | * stack. This alignment requirement may be stricter than that for the |
---|
614 | * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT |
---|
615 | * is strict enough for the stack, then this should be set to 0. |
---|
616 | * |
---|
617 | * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. |
---|
618 | */ |
---|
619 | |
---|
620 | #define CPU_STACK_ALIGNMENT (PPC_STACK_ALIGNMENT) |
---|
621 | |
---|
622 | /* |
---|
623 | * Needed for Interrupt stack |
---|
624 | */ |
---|
625 | #define CPU_MINIMUM_STACK_FRAME_SIZE 8 |
---|
626 | |
---|
627 | |
---|
628 | /* |
---|
629 | * ISR handler macros |
---|
630 | */ |
---|
631 | |
---|
632 | #define _CPU_Initialize_vectors() |
---|
633 | |
---|
634 | /* |
---|
635 | * Disable all interrupts for an RTEMS critical section. The previous |
---|
636 | * level is returned in _isr_cookie. |
---|
637 | */ |
---|
638 | |
---|
639 | #define loc_string(a,b) a " (" #b ")\n" |
---|
640 | |
---|
641 | #ifndef ASM |
---|
642 | |
---|
643 | static inline unsigned32 _CPU_ISR_Get_level( void ) |
---|
644 | { |
---|
645 | register unsigned int msr; |
---|
646 | _CPU_MSR_GET(msr); |
---|
647 | if (msr & MSR_EE) return 0; |
---|
648 | else return 1; |
---|
649 | } |
---|
650 | |
---|
651 | static inline void _CPU_ISR_Set_level( unsigned32 level ) |
---|
652 | { |
---|
653 | register unsigned int msr; |
---|
654 | _CPU_MSR_GET(msr); |
---|
655 | if (!(level & CPU_MODES_INTERRUPT_MASK)) { |
---|
656 | msr |= MSR_EE; |
---|
657 | } |
---|
658 | else { |
---|
659 | msr &= ~MSR_EE; |
---|
660 | } |
---|
661 | _CPU_MSR_SET(msr); |
---|
662 | } |
---|
663 | |
---|
664 | #define _CPU_ISR_install_vector(irq, new, old) {BSP_panic("_CPU_ISR_install_vector called\n");} |
---|
665 | |
---|
666 | /* Context handler macros */ |
---|
667 | |
---|
668 | /* |
---|
669 | * Initialize the context to a state suitable for starting a |
---|
670 | * task after a context restore operation. Generally, this |
---|
671 | * involves: |
---|
672 | * |
---|
673 | * - setting a starting address |
---|
674 | * - preparing the stack |
---|
675 | * - preparing the stack and frame pointers |
---|
676 | * - setting the proper interrupt level in the context |
---|
677 | * - initializing the floating point context |
---|
678 | * |
---|
679 | * This routine generally does not set any unnecessary register |
---|
680 | * in the context. The state of the "general data" registers is |
---|
681 | * undefined at task start time. |
---|
682 | * |
---|
683 | * NOTE: Implemented as a subroutine for the SPARC port. |
---|
684 | */ |
---|
685 | |
---|
686 | void _CPU_Context_Initialize( |
---|
687 | Context_Control *the_context, |
---|
688 | unsigned32 *stack_base, |
---|
689 | unsigned32 size, |
---|
690 | unsigned32 new_level, |
---|
691 | void *entry_point, |
---|
692 | boolean is_fp |
---|
693 | ); |
---|
694 | |
---|
695 | /* |
---|
696 | * This routine is responsible for somehow restarting the currently |
---|
697 | * executing task. If you are lucky, then all that is necessary |
---|
698 | * is restoring the context. Otherwise, there will need to be |
---|
699 | * a special assembly routine which does something special in this |
---|
700 | * case. Context_Restore should work most of the time. It will |
---|
701 | * not work if restarting self conflicts with the stack frame |
---|
702 | * assumptions of restoring a context. |
---|
703 | */ |
---|
704 | |
---|
705 | #define _CPU_Context_Restart_self( _the_context ) \ |
---|
706 | _CPU_Context_restore( (_the_context) ); |
---|
707 | |
---|
708 | /* |
---|
709 | * The purpose of this macro is to allow the initial pointer into |
---|
710 | * a floating point context area (used to save the floating point |
---|
711 | * context) to be at an arbitrary place in the floating point |
---|
712 | * context area. |
---|
713 | * |
---|
714 | * This is necessary because some FP units are designed to have |
---|
715 | * their context saved as a stack which grows into lower addresses. |
---|
716 | * Other FP units can be saved by simply moving registers into offsets |
---|
717 | * from the base of the context area. Finally some FP units provide |
---|
718 | * a "dump context" instruction which could fill in from high to low |
---|
719 | * or low to high based on the whim of the CPU designers. |
---|
720 | */ |
---|
721 | |
---|
722 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
---|
723 | ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
---|
724 | |
---|
725 | /* |
---|
726 | * This routine initializes the FP context area passed to it to. |
---|
727 | * There are a few standard ways in which to initialize the |
---|
728 | * floating point context. The code included for this macro assumes |
---|
729 | * that this is a CPU in which a "initial" FP context was saved into |
---|
730 | * _CPU_Null_fp_context and it simply copies it to the destination |
---|
731 | * context passed to it. |
---|
732 | * |
---|
733 | * Other models include (1) not doing anything, and (2) putting |
---|
734 | * a "null FP status word" in the correct place in the FP context. |
---|
735 | */ |
---|
736 | |
---|
737 | #define _CPU_Context_Initialize_fp( _destination ) \ |
---|
738 | { \ |
---|
739 | ((Context_Control_fp *) *((void **) _destination))->fpscr = PPC_INIT_FPSCR; \ |
---|
740 | } |
---|
741 | |
---|
742 | /* end of Context handler macros */ |
---|
743 | |
---|
744 | /* Fatal Error manager macros */ |
---|
745 | |
---|
746 | /* |
---|
747 | * This routine copies _error into a known place -- typically a stack |
---|
748 | * location or a register, optionally disables interrupts, and |
---|
749 | * halts/stops the CPU. |
---|
750 | */ |
---|
751 | |
---|
752 | #define _CPU_Fatal_halt( _error ) \ |
---|
753 | _BSP_Fatal_error(_error) |
---|
754 | |
---|
755 | /* end of Fatal Error manager macros */ |
---|
756 | |
---|
757 | /* Bitfield handler macros */ |
---|
758 | |
---|
759 | /* |
---|
760 | * This routine sets _output to the bit number of the first bit |
---|
761 | * set in _value. _value is of CPU dependent type Priority_Bit_map_control. |
---|
762 | * This type may be either 16 or 32 bits wide although only the 16 |
---|
763 | * least significant bits will be used. |
---|
764 | * |
---|
765 | * There are a number of variables in using a "find first bit" type |
---|
766 | * instruction. |
---|
767 | * |
---|
768 | * (1) What happens when run on a value of zero? |
---|
769 | * (2) Bits may be numbered from MSB to LSB or vice-versa. |
---|
770 | * (3) The numbering may be zero or one based. |
---|
771 | * (4) The "find first bit" instruction may search from MSB or LSB. |
---|
772 | * |
---|
773 | * RTEMS guarantees that (1) will never happen so it is not a concern. |
---|
774 | * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and |
---|
775 | * _CPU_Priority_Bits_index(). These three form a set of routines |
---|
776 | * which must logically operate together. Bits in the _value are |
---|
777 | * set and cleared based on masks built by _CPU_Priority_mask(). |
---|
778 | * The basic major and minor values calculated by _Priority_Major() |
---|
779 | * and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index() |
---|
780 | * to properly range between the values returned by the "find first bit" |
---|
781 | * instruction. This makes it possible for _Priority_Get_highest() to |
---|
782 | * calculate the major and directly index into the minor table. |
---|
783 | * This mapping is necessary to ensure that 0 (a high priority major/minor) |
---|
784 | * is the first bit found. |
---|
785 | * |
---|
786 | * This entire "find first bit" and mapping process depends heavily |
---|
787 | * on the manner in which a priority is broken into a major and minor |
---|
788 | * components with the major being the 4 MSB of a priority and minor |
---|
789 | * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest |
---|
790 | * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next |
---|
791 | * to the lowest priority. |
---|
792 | * |
---|
793 | * If your CPU does not have a "find first bit" instruction, then |
---|
794 | * there are ways to make do without it. Here are a handful of ways |
---|
795 | * to implement this in software: |
---|
796 | * |
---|
797 | * - a series of 16 bit test instructions |
---|
798 | * - a "binary search using if's" |
---|
799 | * - _number = 0 |
---|
800 | * if _value > 0x00ff |
---|
801 | * _value >>=8 |
---|
802 | * _number = 8; |
---|
803 | * |
---|
804 | * if _value > 0x0000f |
---|
805 | * _value >=8 |
---|
806 | * _number += 4 |
---|
807 | * |
---|
808 | * _number += bit_set_table[ _value ] |
---|
809 | * |
---|
810 | * where bit_set_table[ 16 ] has values which indicate the first |
---|
811 | * bit set |
---|
812 | */ |
---|
813 | |
---|
814 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
---|
815 | { \ |
---|
816 | asm volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \ |
---|
817 | "1" ((_value))); \ |
---|
818 | } |
---|
819 | |
---|
820 | /* end of Bitfield handler macros */ |
---|
821 | |
---|
822 | /* |
---|
823 | * This routine builds the mask which corresponds to the bit fields |
---|
824 | * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion |
---|
825 | * for that routine. |
---|
826 | */ |
---|
827 | |
---|
828 | #define _CPU_Priority_Mask( _bit_number ) \ |
---|
829 | ( 0x80000000 >> (_bit_number) ) |
---|
830 | |
---|
831 | /* |
---|
832 | * This routine translates the bit numbers returned by |
---|
833 | * _CPU_Bitfield_Find_first_bit() into something suitable for use as |
---|
834 | * a major or minor component of a priority. See the discussion |
---|
835 | * for that routine. |
---|
836 | */ |
---|
837 | |
---|
838 | #define _CPU_Priority_bits_index( _priority ) \ |
---|
839 | (_priority) |
---|
840 | |
---|
841 | /* end of Priority handler macros */ |
---|
842 | |
---|
843 | /* variables */ |
---|
844 | |
---|
845 | extern const unsigned32 _CPU_msrs[4]; |
---|
846 | |
---|
847 | /* functions */ |
---|
848 | |
---|
849 | /* |
---|
850 | * _CPU_Initialize |
---|
851 | * |
---|
852 | * This routine performs CPU dependent initialization. |
---|
853 | */ |
---|
854 | |
---|
855 | void _CPU_Initialize( |
---|
856 | rtems_cpu_table *cpu_table, |
---|
857 | void (*thread_dispatch) |
---|
858 | ); |
---|
859 | |
---|
860 | |
---|
861 | /* |
---|
862 | * _CPU_Install_interrupt_stack |
---|
863 | * |
---|
864 | * This routine installs the hardware interrupt stack pointer. |
---|
865 | * |
---|
866 | * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK |
---|
867 | * is TRUE. |
---|
868 | */ |
---|
869 | |
---|
870 | void _CPU_Install_interrupt_stack( void ); |
---|
871 | |
---|
872 | /* |
---|
873 | * _CPU_Context_switch |
---|
874 | * |
---|
875 | * This routine switches from the run context to the heir context. |
---|
876 | */ |
---|
877 | |
---|
878 | void _CPU_Context_switch( |
---|
879 | Context_Control *run, |
---|
880 | Context_Control *heir |
---|
881 | ); |
---|
882 | |
---|
883 | /* |
---|
884 | * _CPU_Context_restore |
---|
885 | * |
---|
886 | * This routine is generallu used only to restart self in an |
---|
887 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
---|
888 | * |
---|
889 | * NOTE: May be unnecessary to reload some registers. |
---|
890 | */ |
---|
891 | |
---|
892 | void _CPU_Context_restore( |
---|
893 | Context_Control *new_context |
---|
894 | ); |
---|
895 | |
---|
896 | /* |
---|
897 | * _CPU_Context_save_fp |
---|
898 | * |
---|
899 | * This routine saves the floating point context passed to it. |
---|
900 | */ |
---|
901 | |
---|
902 | void _CPU_Context_save_fp( |
---|
903 | void **fp_context_ptr |
---|
904 | ); |
---|
905 | |
---|
906 | /* |
---|
907 | * _CPU_Context_restore_fp |
---|
908 | * |
---|
909 | * This routine restores the floating point context passed to it. |
---|
910 | */ |
---|
911 | |
---|
912 | void _CPU_Context_restore_fp( |
---|
913 | void **fp_context_ptr |
---|
914 | ); |
---|
915 | |
---|
916 | void _CPU_Fatal_error( |
---|
917 | unsigned32 _error |
---|
918 | ); |
---|
919 | |
---|
920 | /* The following routine swaps the endian format of an unsigned int. |
---|
921 | * It must be static because it is referenced indirectly. |
---|
922 | * |
---|
923 | * This version will work on any processor, but if there is a better |
---|
924 | * way for your CPU PLEASE use it. The most common way to do this is to: |
---|
925 | * |
---|
926 | * swap least significant two bytes with 16-bit rotate |
---|
927 | * swap upper and lower 16-bits |
---|
928 | * swap most significant two bytes with 16-bit rotate |
---|
929 | * |
---|
930 | * Some CPUs have special instructions which swap a 32-bit quantity in |
---|
931 | * a single instruction (e.g. i486). It is probably best to avoid |
---|
932 | * an "endian swapping control bit" in the CPU. One good reason is |
---|
933 | * that interrupts would probably have to be disabled to insure that |
---|
934 | * an interrupt does not try to access the same "chunk" with the wrong |
---|
935 | * endian. Another good reason is that on some CPUs, the endian bit |
---|
936 | * endianness for ALL fetches -- both code and data -- so the code |
---|
937 | * will be fetched incorrectly. |
---|
938 | */ |
---|
939 | |
---|
940 | static inline unsigned int CPU_swap_u32( |
---|
941 | unsigned int value |
---|
942 | ) |
---|
943 | { |
---|
944 | unsigned32 swapped; |
---|
945 | |
---|
946 | asm volatile("rlwimi %0,%1,8,24,31;" |
---|
947 | "rlwimi %0,%1,24,16,23;" |
---|
948 | "rlwimi %0,%1,8,8,15;" |
---|
949 | "rlwimi %0,%1,24,0,7;" : |
---|
950 | "=&r" ((swapped)) : "r" ((value))); |
---|
951 | |
---|
952 | return( swapped ); |
---|
953 | } |
---|
954 | |
---|
955 | #define CPU_swap_u16( value ) \ |
---|
956 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
---|
957 | |
---|
958 | #endif /* ndef ASM */ |
---|
959 | |
---|
960 | #ifdef __cplusplus |
---|
961 | } |
---|
962 | #endif |
---|
963 | |
---|
964 | #endif |
---|