source: rtems/c/src/lib/libbsp/powerpc/support/new_exception_processing/cpu.c @ 75ad7376

4.104.114.84.95
Last change on this file since 75ad7376 was 75ad7376, checked in by Joel Sherrill <joel.sherrill@…>, on Nov 28, 2001 at 6:15:51 PM

2001-11-28 Joel Sherrill <joel@…>,

This was tracked as PR91.

  • rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which is used to specify if the port uses the standard macro for this (FALSE). A TRUE setting indicates the port provides its own implementation.
  • rtems/score/c_isr.inl: Deleted and contents merged into cpu.c.
  • cpu.c: Received contents of c_isr.inl.
  • Makefile.am: Deleted reference to c_isr.inl.
  • Property mode set to 100644
File size: 3.1 KB
Line 
1/*
2 *  PowerPC CPU Dependent Source
3 *
4 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
5 *
6 *  COPYRIGHT (c) 1995 by i-cubed ltd.
7 *
8 *  To anyone who acknowledges that this file is provided "AS IS"
9 *  without any express or implied warranty:
10 *      permission to use, copy, modify, and distribute this file
11 *      for any purpose is hereby granted without fee, provided that
12 *      the above copyright notice and this notice appears in all
13 *      copies, and that the name of i-cubed limited not be used in
14 *      advertising or publicity pertaining to distribution of the
15 *      software without specific, written prior permission.
16 *      i-cubed limited makes no representations about the suitability
17 *      of this software for any purpose.
18 *
19 *  Derived from c/src/exec/cpu/no_cpu/cpu.c:
20 *
21 *  COPYRIGHT (c) 1989-1997.
22 *  On-Line Applications Research Corporation (OAR).
23 *
24 *  The license and distribution terms for this file may be found in
25 *  the file LICENSE in this distribution or at
26 *  http://www.OARcorp.com/rtems/license.html.
27 *
28 *  $Id$
29 */
30
31#include <rtems/system.h>
32#include <rtems/score/isr.h>
33#include <rtems/score/context.h>
34#include <rtems/score/thread.h>
35#include <rtems/score/interr.h>
36
37
38/*  _CPU_Initialize
39 *
40 *  This routine performs processor dependent initialization.
41 *
42 *  INPUT PARAMETERS:
43 *    cpu_table       - CPU table to initialize
44 *    thread_dispatch - address of disptaching routine
45 */
46
47void _CPU_Initialize(
48  rtems_cpu_table  *cpu_table,
49  void      (*thread_dispatch)      /* ignored on this CPU */
50)
51{
52  _CPU_Table = *cpu_table;
53}
54
55/*PAGE
56 *
57 *  _CPU_Context_Initialize
58 */
59
60void _CPU_Context_Initialize(
61  Context_Control  *the_context,
62  unsigned32       *stack_base,
63  unsigned32        size,
64  unsigned32        new_level,
65  void             *entry_point,
66  boolean           is_fp
67)
68{
69  unsigned32 msr_value;
70  unsigned32 sp;
71
72  sp = (unsigned32)stack_base + size - CPU_MINIMUM_STACK_FRAME_SIZE;
73  *((unsigned32 *)sp) = 0;
74  the_context->gpr1 = sp;
75   
76  _CPU_MSR_GET( msr_value );
77
78  if (!(new_level & CPU_MODES_INTERRUPT_MASK)) {
79    msr_value |= MSR_EE;
80  }
81  else {
82    msr_value &= ~MSR_EE;
83  }
84
85  the_context->msr = msr_value;
86
87  /*
88   *  The FP bit of the MSR should only be enabled if this is a floating
89   *  point task.  Unfortunately, the vfprintf_r routine in newlib
90   *  ends up pushing a floating point register regardless of whether or
91   *  not a floating point number is being printed.  Serious restructuring
92   *  of vfprintf.c will be required to avoid this behavior.  At this
93   *  time (7 July 1997), this restructuring is not being done.
94   */
95
96  /*if ( is_fp ) */
97    the_context->msr |= PPC_MSR_FP;
98
99  the_context->pc = (unsigned32)entry_point;
100}
101
102
103
104/*PAGE
105 *
106 *  _CPU_Install_interrupt_stack
107 */
108
109void _CPU_Install_interrupt_stack( void )
110{
111}
112
113/*PAGE
114 *
115 *  This is the PowerPC specific implementation of the routine which
116 *  returns TRUE if an interrupt is in progress.
117 */
118
119boolean _ISR_Is_in_progress( void )
120{
121  register unsigned int isr_nesting_level;
122  /*
123   * Move from special purpose register 0 (mfspr SPRG0, r3)
124   */
125  asm volatile ("mfspr  %0, 272" : "=r" (isr_nesting_level));
126  return isr_nesting_level;
127}
128
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