| 1 | /* start.S |
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| 2 | * |
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| 3 | * This file contains the entry veneer for RTEMS programs on the Intec |
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| 4 | * SS555 board. It jumps to the BSP which is responsible for performing |
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| 5 | * all remaining initialization. |
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| 6 | * |
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| 7 | * This file is based on several others: |
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| 8 | * |
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| 9 | * (1) start360.s from the gen68360 BSP by |
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| 10 | * W. Eric Norum (eric@skatter.usask.ca) |
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| 11 | * with the following copyright and license: |
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| 12 | * |
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| 13 | * COPYRIGHT (c) 1989-1998. |
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| 14 | * On-Line Applications Research Corporation (OAR). |
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| 15 | * |
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| 16 | * The license and distribution terms for this file may in |
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| 17 | * the file LICENSE in this distribution or at |
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| 18 | * http://www.rtems.com/license/LICENSE. |
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| 19 | * |
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| 20 | * (2) start.s for the eth_comm port by |
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| 21 | * Jay Monkman (jmonkman@fracsa.com), |
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| 22 | * which itself is based on the |
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| 23 | * |
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| 24 | * (3) dlentry.s for the Papyrus BSP, written by: |
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| 25 | * Andrew Bray <andy@i-cubed.co.uk> |
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| 26 | * with the following copyright and license: |
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| 27 | * |
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| 28 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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| 29 | * |
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| 30 | * (4) start860.S for the MBX821/MBX860, written by: |
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| 31 | * Darlene A. Stewart <darlene.stewart@iit.nrc.ca> |
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| 32 | * Copyright (c) 1999, National Research Council of Canada |
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| 33 | * |
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| 34 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 35 | * without any express or implied warranty: |
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| 36 | * permission to use, copy, modify, and distribute this file |
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| 37 | * for any purpose is hereby granted without fee, provided that |
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| 38 | * the above copyright notice and this notice appears in all |
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| 39 | * copies, and that the name of i-cubed limited not be used in |
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| 40 | * advertising or publicity pertaining to distribution of the |
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| 41 | * software without specific, written prior permission. |
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| 42 | * i-cubed limited makes no representations about the suitability |
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| 43 | * of this software for any purpose. |
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| 44 | * |
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| 45 | * (5) Modifications (for MBX8xx) of respective RTEMS files: |
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| 46 | * Copyright (c) 1999, National Research Council of Canada |
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| 47 | * |
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| 48 | * SS555 port sponsored by Defence Research and Development Canada - Suffield |
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| 49 | * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) |
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| 50 | */ |
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| 51 | |
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| 52 | #include <rtems/asm.h> |
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| 53 | #include <rtems/powerpc/registers.h> |
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| 54 | |
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| 55 | /* |
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| 56 | * The initial stack is set to the top of the internal RAM. |
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| 57 | * |
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| 58 | * All the entry veneer has to do is to clear the .bss section and copy the |
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| 59 | * initializers into the .data section. |
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| 60 | */ |
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| 61 | |
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| 62 | /* |
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| 63 | * GDB likes to have debugging information for the entry veneer. |
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| 64 | * Play compiler and provide some DWARF information. |
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| 65 | * |
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| 66 | * CHANGE TO SUIT YOUR SETUP! |
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| 67 | */ |
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| 68 | |
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| 69 | .section .entry,"ax",@progbits |
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| 70 | .L_text_b: |
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| 71 | .L_LC1: |
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| 72 | .previous |
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| 73 | |
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| 74 | .section .debug_sfnames |
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| 75 | .L_sfnames_b: |
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| 76 | .byte "rtems/c/src/lib/libbsp/powerpc/ss555/startup/" |
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| 77 | .byte 0 |
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| 78 | .L_F0: |
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| 79 | .byte "start.S" |
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| 80 | .byte 0 |
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| 81 | .previous |
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| 82 | |
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| 83 | .section .line |
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| 84 | .L_line_b: |
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| 85 | .4byte .L_line_e-.L_line_b |
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| 86 | .4byte .L_text_b |
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| 87 | .L_LE1: |
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| 88 | .L_line_last: |
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| 89 | .4byte 0x0 |
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| 90 | .2byte 0xffff |
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| 91 | .4byte .L_text_e-.L_text_b |
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| 92 | .L_line_e: |
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| 93 | .previous |
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| 94 | |
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| 95 | .section .debug_srcinfo |
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| 96 | .L_srcinfo_b: |
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| 97 | .4byte .L_line_b |
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| 98 | .4byte .L_sfnames_b |
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| 99 | .4byte .L_text_b |
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| 100 | .4byte .L_text_e |
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| 101 | .4byte 0xffffffff |
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| 102 | .4byte .L_LE1-.L_line_b |
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| 103 | .4byte .L_F0-.L_sfnames_b |
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| 104 | .4byte .L_line_last-.L_line_b |
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| 105 | .4byte 0xffffffff |
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| 106 | .previous |
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| 107 | |
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| 108 | .section .debug_pubnames |
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| 109 | .4byte .L_debug_b |
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| 110 | .4byte .L_P0 |
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| 111 | .byte "start" |
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| 112 | .byte 0 |
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| 113 | .4byte 0x0 |
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| 114 | .byte 0 |
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| 115 | .previous |
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| 116 | |
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| 117 | .section .debug_aranges |
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| 118 | .4byte .L_debug_b |
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| 119 | .4byte .L_text_b |
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| 120 | .4byte .L_text_e-.L_text_b |
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| 121 | .4byte 0 |
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| 122 | .4byte 0 |
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| 123 | .4byte 0 |
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| 124 | .4byte 0 |
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| 125 | .4byte 0 |
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| 126 | .4byte 0 |
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| 127 | .4byte 0x0 |
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| 128 | .4byte 0x0 |
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| 129 | .previous |
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| 130 | |
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| 131 | .section .debug |
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| 132 | .L_debug_b: |
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| 133 | .L_D1: |
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| 134 | .4byte .L_D1_e-.L_D1 |
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| 135 | .2byte 0x11 /* TAG_compile_unit */ |
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| 136 | .2byte 0x12 /* AT_sibling */ |
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| 137 | .4byte .L_D2 |
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| 138 | .2byte 0x38 /* AT_name */ |
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| 139 | .byte "start.S" |
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| 140 | .byte 0 |
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| 141 | .2byte 0x258 /* AT_producer */ |
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| 142 | .byte "GAS 2.5.2" |
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| 143 | .byte 0 |
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| 144 | .2byte 0x111 /* AT_low_pc */ |
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| 145 | .4byte .L_text_b |
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| 146 | .2byte 0x121 /* AT_high_pc */ |
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| 147 | .4byte .L_text_e |
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| 148 | .2byte 0x106 /* AT_stmt_list */ |
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| 149 | .4byte .L_line_b |
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| 150 | .2byte 0x1b8 /* AT_comp_dir */ |
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| 151 | .byte "rtems/c/src/lib/libbsp/powerpc/ss555/startup/" |
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| 152 | .byte 0 |
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| 153 | .2byte 0x8006 /* AT_sf_names */ |
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| 154 | .4byte .L_sfnames_b |
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| 155 | .2byte 0x8016 /* AT_src_info */ |
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| 156 | .4byte .L_srcinfo_b |
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| 157 | .L_D1_e: |
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| 158 | .L_P0: |
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| 159 | .L_D3: |
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| 160 | .4byte .L_D3_e-.L_D3 |
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| 161 | .2byte 0x6 /* TAG_global_subroutine */ |
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| 162 | .2byte 0x12 /* AT_sibling */ |
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| 163 | .4byte .L_D4 |
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| 164 | .2byte 0x38 /* AT_name */ |
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| 165 | .byte "start" |
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| 166 | .byte 0 |
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| 167 | .2byte 0x278 /* AT_prototyped */ |
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| 168 | .byte 0 |
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| 169 | .2byte 0x111 /* AT_low_pc */ |
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| 170 | .4byte .L_text_b |
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| 171 | .2byte 0x121 /* AT_high_pc */ |
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| 172 | .4byte .L_text_e |
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| 173 | .2byte 0x8041 /* AT_body_begin */ |
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| 174 | .4byte .L_text_b |
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| 175 | .2byte 0x8051 /* AT_body_end */ |
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| 176 | .4byte .L_text_e |
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| 177 | .L_D3_e: |
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| 178 | |
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| 179 | .L_D4: |
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| 180 | .4byte .L_D4_e-.L_D4 |
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| 181 | .align 2 |
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| 182 | .L_D4_e: |
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| 183 | .L_D2: |
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| 184 | .previous |
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| 185 | |
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| 186 | /* |
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| 187 | * Tell C's eabi-ctor's that we have an atexit function, |
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| 188 | * and that it is to register __do_global_dtors. |
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| 189 | */ |
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| 190 | EXTERN_PROC(atexit) |
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| 191 | PUBLIC_VAR(__atexit) |
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| 192 | .section ".sdata","aw" |
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| 193 | .align 2 |
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| 194 | SYM(__atexit): |
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| 195 | EXT_PROC_REF(atexit)@fixup |
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| 196 | .previous |
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| 197 | |
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| 198 | .section ".fixup","aw" |
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| 199 | .align 2 |
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| 200 | EXT_SYM_REF(__atexit) |
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| 201 | .previous |
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| 202 | |
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| 203 | /* That should do it */ |
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| 204 | |
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| 205 | /* |
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| 206 | * Put the entry point in its own section. That way, we can guarantee |
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| 207 | * to put it first in the .text section in the linker script. |
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| 208 | */ |
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| 209 | .section .entry |
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| 210 | |
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| 211 | PUBLIC_VAR (start) |
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| 212 | SYM(start): |
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| 213 | bl .startup /* or bl .spin */ |
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| 214 | base_addr: |
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| 215 | |
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| 216 | /* |
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| 217 | * Parameters from linker |
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| 218 | */ |
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| 219 | stack_top: |
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| 220 | .long initStackPtr |
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| 221 | |
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| 222 | toc_pointer: |
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| 223 | .long __GOT_START__ |
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| 224 | |
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| 225 | bss_length: |
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| 226 | .long bss.size |
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| 227 | bss_addr: |
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| 228 | .long bss.start |
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| 229 | |
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| 230 | data_length: |
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| 231 | .long data.size |
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| 232 | data_addr: |
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| 233 | .long data.start |
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| 234 | contents_addr: |
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| 235 | .long data.contents.start |
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| 236 | |
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| 237 | PUBLIC_VAR (text_addr) |
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| 238 | text_addr: |
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| 239 | .long text.start |
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| 240 | |
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| 241 | PUBLIC_VAR (text_length) |
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| 242 | text_length: |
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| 243 | .long text.size |
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| 244 | |
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| 245 | /* |
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| 246 | * Spin, if necessary, to acquire control from debugger (CodeWarrior). |
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| 247 | */ |
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| 248 | spin: |
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| 249 | .long 0x0001 |
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| 250 | .spin: |
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| 251 | lis r3, spin@ha |
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| 252 | lwz r3, spin@l(r3) |
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| 253 | cmpwi r3, 0x1 |
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| 254 | beq .spin |
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| 255 | |
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| 256 | /* |
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| 257 | * Initialization code |
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| 258 | */ |
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| 259 | .startup: |
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| 260 | /* Capture address of linker parameters. */ |
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| 261 | mflr r3 |
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| 262 | |
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| 263 | /* Set initial stack pointer to end of internal RAM - 56. */ |
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| 264 | lwz r1, stack_top-base_addr(r3) |
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| 265 | addi r1, r1, -56 |
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| 266 | |
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| 267 | /* Initialize essential registers. */ |
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| 268 | bl initregs |
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| 269 | |
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| 270 | /* Set TOC pointer */ |
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| 271 | lwz r2, toc_pointer-base_addr(r3) |
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| 272 | |
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| 273 | /* Initialize the memory mapped MPC555 registers (done in C). */ |
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| 274 | EXTERN_PROC (_InitSS555) |
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| 275 | bl PROC (_InitSS555) |
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| 276 | |
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| 277 | /* Clear the .bss section. */ |
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| 278 | bl bssclr |
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| 279 | |
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| 280 | /* Copy initializers into the .data section */ |
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| 281 | bl datacopy |
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| 282 | |
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| 283 | /* Enable floating point, since gcc sometimes uses the floating |
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| 284 | * point registers for data moves, even if the C source code doesn't |
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| 285 | * include floating point operations. |
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| 286 | */ |
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| 287 | mfmsr r0 |
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| 288 | ori r0, r0, MSR_FP |
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| 289 | mtmsr r0 |
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| 290 | |
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| 291 | /* Start system. */ |
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| 292 | li r3, 0 /* command line */ |
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| 293 | EXTERN_PROC (boot_card) |
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| 294 | bl PROC (boot_card) /* call the first C routine */ |
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| 295 | |
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| 296 | /* We should never return from boot_card, but in case we do ... */ |
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| 297 | /* The next instructions are dependent on your runtime environment. */ |
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| 298 | |
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| 299 | stop_here: |
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| 300 | b stop_here |
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| 301 | |
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| 302 | /* |
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| 303 | * datacopy - copy initializers into .data section |
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| 304 | */ |
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| 305 | datacopy: |
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| 306 | lis r3, base_addr@ha /* point to linker data */ |
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| 307 | addi r3, r3, base_addr@l |
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| 308 | |
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| 309 | lwz r4, contents_addr-base_addr(r3) /* .data contents in ROM */ |
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| 310 | lwz r5, data_addr-base_addr(r3) /* .data section in RAM */ |
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| 311 | lwz r6, data_length-base_addr(r3) /* length of .data */ |
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| 312 | |
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| 313 | rlwinm. r6, r6, 30, 0x3FFFFFFF /* form length / 4 */ |
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| 314 | beqlr /* no .data - return */ |
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| 315 | |
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| 316 | mtctr r6 /* set ctr reg */ |
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| 317 | dc1: |
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| 318 | lwz r6, 0(r4) /* get word */ |
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| 319 | stw r6, 0(r5) /* store word */ |
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| 320 | addi r4, r4, 0x4 /* next source */ |
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| 321 | addi r5, r5, 0x4 /* next target */ |
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| 322 | bdnz dc1 /* dec counter and loop */ |
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| 323 | |
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| 324 | blr /* return */ |
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| 325 | |
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| 326 | /* |
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| 327 | * bssclr - zero out bss |
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| 328 | */ |
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| 329 | bssclr: |
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| 330 | lis r3, base_addr@ha /* point to linker data */ |
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| 331 | addi r3, r3, base_addr@l |
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| 332 | |
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| 333 | lwz r4, bss_addr-base_addr(r3) /* Start of bss */ |
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| 334 | lwz r5, bss_length-base_addr(r3) /* Length of bss */ |
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| 335 | |
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| 336 | rlwinm. r5, r5, 30, 0x3FFFFFFF /* form length/4 */ |
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| 337 | beqlr /* no bss - return */ |
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| 338 | |
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| 339 | mtctr r5 /* set ctr reg */ |
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| 340 | li r5, 0x0000 /* r5 = 0 */ |
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| 341 | clear_bss: |
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| 342 | stw r5, 0(r4) /* store r6 */ |
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| 343 | addi r4, r4, 0x4 /* update r4 */ |
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| 344 | bdnz clear_bss /* dec counter and loop */ |
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| 345 | |
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| 346 | blr /* return */ |
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| 347 | |
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| 348 | /* |
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| 349 | * initregs |
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| 350 | * Initialize the MSR and basic core PowerPC registers |
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| 351 | * |
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| 352 | * Register usage: |
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| 353 | * r0 - scratch |
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| 354 | */ |
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| 355 | initregs: |
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| 356 | /* |
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| 357 | * Set the processor for big-endian mode, exceptions vectored to |
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| 358 | * 0x000n_nnnn, no execution tracing, machine check exceptions |
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| 359 | * enabled, floating-point not available, supervisor priviledge |
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| 360 | * level, external interrupts disabled, power management disabled |
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| 361 | * (normal operation mode). |
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| 362 | */ |
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| 363 | li r0, 0x1000 /* MSR_ME */ |
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| 364 | mtmsr r0 /* Context-synchronizing */ |
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| 365 | isync |
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| 366 | |
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| 367 | /* |
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| 368 | * Clear the exception handling registers. |
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| 369 | */ |
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| 370 | li r0, 0x0000 |
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| 371 | mtdar r0 |
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| 372 | mtspr sprg0, r0 |
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| 373 | mtspr sprg1, r0 |
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| 374 | mtspr sprg2, r0 |
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| 375 | mtspr sprg3, r0 |
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| 376 | mtspr srr0, r0 |
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| 377 | mtspr srr1, r0 |
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| 378 | |
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| 379 | mr r6, r0 |
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| 380 | mr r7, r0 |
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| 381 | mr r8, r0 |
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| 382 | mr r9, r0 |
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| 383 | mr r10, r0 |
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| 384 | mr r11, r0 |
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| 385 | mr r12, r0 |
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| 386 | mr r13, r0 |
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| 387 | mr r14, r0 |
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| 388 | mr r15, r0 |
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| 389 | mr r16, r0 |
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| 390 | mr r17, r0 |
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| 391 | mr r18, r0 |
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| 392 | mr r19, r0 |
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| 393 | mr r20, r0 |
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| 394 | mr r21, r0 |
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| 395 | mr r22, r0 |
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| 396 | mr r23, r0 |
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| 397 | mr r24, r0 |
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| 398 | mr r25, r0 |
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| 399 | mr r26, r0 |
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| 400 | mr r27, r0 |
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| 401 | mr r28, r0 |
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| 402 | mr r29, r0 |
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| 403 | mr r30, r0 |
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| 404 | mr r31, r0 |
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| 405 | |
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| 406 | blr /* return */ |
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| 407 | |
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| 408 | .L_text_e: |
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