source: rtems/c/src/lib/libbsp/powerpc/ss555/startup/iss555.c @ a800d09c

4.104.114.84.95
Last change on this file since a800d09c was a800d09c, checked in by Joel Sherrill <joel.sherrill@…>, on Apr 12, 2004 at 9:52:13 PM

2004-04-12 David Querbach <querbach@…>

  • .cvsignore, ChangeLog?, Makefile.am, README, bsp_specs, configure.ac, times, clock/p_clock.c, console/console.c, include/.cvsignore, include/bsp.h, include/coverhd.h, irq/irq.h, startup/bspstart.c, startup/iss555.c, startup/linkcmds, startup/start.S, wrapup/.cvsignore, wrapup/Makefile.am: New files.
  • Property mode set to 100644
File size: 4.5 KB
Line 
1/*
2 *  iss555.c
3 *
4 *  Intec SS555 initialization routines.
5 *
6 *  SS555 port sponsored by Defence Research and Development Canada - Suffield
7 *  Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
8 *
9 *  Derived from c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c:
10 *
11 *  Copyright (c) 1999, National Research Council of Canada
12 *
13 *  The license and distribution terms for this file may be
14 *  found in the file LICENSE in this distribution or at
15 *  http://www.rtems.com/license/LICENSE.
16 */
17
18#include <bsp.h>
19
20SPR_RW(ICTRL);
21SPR_RW(DEC);
22SPR_RW(TBWU);
23SPR_RW(TBWL);
24SPR_RO(IMMR);
25SPR_RW(MI_GRA);
26SPR_RW(L2U_GRA);
27SPR_RW(BBCMCR);
28
29
30/*
31 *  Initialize SS555
32 */
33void _InitSS555 (void)
34{
35  register unsigned32 plprcr, msr;
36
37  /*
38   * Initialize the System Protection Control Register (SYPCR).
39   * The SYPCR can only be written once after Reset.
40   */
41  usiu.sypcr = 
42      USIU_SYPCR_SWTC(WATCHDOG_TIMEOUT) /* set watchdog timeout */
43    | USIU_SYPCR_BMT(0xFF)              /* set bus monitor timeout */
44    | USIU_SYPCR_BME                    /* enable bus monitor */
45    | USIU_SYPCR_SWF                    /* watchdog halted in freeze */
46#if WATCHDOG_TIMEOUT != 0xFFFF
47    | USIU_SYPCR_SWE                    /* enable watchdog */
48#endif
49    | USIU_SYPCR_SWRI                   /* watchdog forces reset */
50    | USIU_SYPCR_SWP;                   /* prescale watchdog by 2048 */
51
52  TICKLE_WATCHDOG();                    /* restart watchdog timer */
53 
54  /*
55   * Re-tune the PLL to the desired system clock frequency.
56   */
57  usiu.plprck = USIU_UNLOCK_KEY;        /* unlock PLPRCR */
58  usiu.plprcr = 
59      USIU_PLPRCR_TEXPS                 /* assert TEXP always */
60    | USIU_PLPRCR_MF(BSP_CLOCK_HZ / BSP_CRYSTAL_HZ);
61                                        /* PLL multiplication factor */
62  usiu.plprck = 0;                      /* lock PLPRCR */
63
64  while (((plprcr = usiu.plprcr) & USIU_PLPRCR_SPLS) == 0)
65    ;                                   /* wait for PLL to re-lock */
66   
67  /*
68   * Enable the timebase and decrementer, then initialize decrementer
69   * register to a large value to guarantee that a decrementer interrupt
70   * will not be generated before the kernel is fully initialized.
71   * Initialize the timebase register to zero.
72   */
73  usiu.tbscrk = USIU_UNLOCK_KEY;
74  usiu.tbscr |= USIU_TBSCR_TBE;         /* enable time base and decrementer */
75  usiu.tbscrk = 0;
76
77  usiu.tbk = USIU_UNLOCK_KEY;
78  _write_DEC(0x7FFFFFFF);
79  _write_TBWU(0x00000000 );
80  _write_TBWL(0x00000000 );
81  usiu.tbk = 0;
82
83  /*
84   * Run the Inter-Module Bus at full speed.
85   */
86  imb.uimb.umcr &= ~UIMB_UMCR_HSPEED;
87 
88  /*
89   * Initialize Memory Controller for External RAM
90   *
91   * Initialize the Base and Option Registers (BR0-BR7 and OR0-OR7).  Note
92   * that for all chip selects, ORx should be programmed before BRx.
93   *
94   * If booting from internal flash ROM, configure the external RAM to
95   * extend the internal RAM.  If booting from external RAM, leave it at
96   * zero but set it up appropriately.
97   */
98  extern char int_ram_top[];            /* top of internal ram */
99                     
100  usiu.memc[0]._or =
101      USIU_MEMC_OR_512K                 /* bank size */
102    | USIU_MEMC_OR_SCY(0)               /* wait states in first beat of burst */
103    | USIU_MEMC_OR_BSCY(0);             /* wait states in subsequent beats */
104                       
105  usiu.memc[0]._br =
106      USIU_MEMC_BR_BA(_read_IMMR() & IMMR_FLEN
107        ? (rtems_unsigned32)int_ram_top : 0)    /* base address */
108    | USIU_MEMC_BR_PS32                 /* 32-bit data bus */
109    | USIU_MEMC_BR_TBDIP                /* toggle bdip */
110    | USIU_MEMC_BR_V;                   /* base register valid */
111 
112  /*
113   * Initialize Memory Controller for External CPLD
114   *
115   * The SS555 board includes a CPLD to control on-board features and
116   * off-board devices.  (Configuration taken from Intec's hwhook.c)
117   */
118  usiu.memc[3]._or =
119      USIU_MEMC_OR_16M                  /* bank size */
120    | USIU_MEMC_OR_CSNT                 /* negate CS/WE early */
121    | USIU_MEMC_OR_ACS_HALF             /* assert CS half cycle after address */
122    | USIU_MEMC_OR_SCY(15)              /* wait states in first beat of burst */
123    | USIU_MEMC_OR_TRLX;                /* relaxed timing */   
124
125  usiu.memc[3]._br =
126      USIU_MEMC_BR_BA(&cpld)            /* base address */
127    | USIU_MEMC_BR_PS16                 /* 16-bit data bus */
128    | USIU_MEMC_BR_BI                   /* inhibit bursting */
129    | USIU_MEMC_BR_V;                   /* base register valid */
130 
131  /*
132   * Disable show cycles and serialization so that burst accesses will work
133   * properly.  A different value, such as 0x0, may be more appropriate for
134   * debugging, but can be set with the debugger, if needed.
135   */
136  _write_ICTRL(0x00000007);
137       
138  /*
139   * Set up Burst Buffer Controller (BBC)
140   */
141  _write_BBCMCR(
142      BBCMCR_ETRE                       /* enable exception relocation */
143    | BBCMCR_BE);                       /* enable burst accesses */
144  _isync;
145
146  _CPU_MSR_GET(msr);
147  msr |= MSR_IP;                /* set prefix for exception relocation */ 
148  _CPU_MSR_SET(msr);
149}
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