source: rtems/c/src/lib/libbsp/powerpc/ss555/irq/irq.h @ bf4fdb1

5
Last change on this file since bf4fdb1 was bf4fdb1, checked in by Sebastian Huber <sebastian.huber@…>, on 11/11/16 at 10:31:13

powerpc: Move legacy CPU_Interrupt_frame

The only remaining user of CPU_Interrupt_frame on PowerPC is the mpc5xx
support. Move it to here.

Update #2809.

  • Property mode set to 100644
File size: 2.1 KB
RevLine 
[a800d09c]1/* irq.h
2 *
3 *  This include file describe the data structure and the functions implemented
4 *  by rtems to write interrupt handlers.
5 *
6 *
7 *  SS555 port sponsored by Defence Research and Development Canada - Suffield
8 *  Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
9 *
10 *  Derived from libbsp/powerpc/mbx8xx/irq/irq.h:
11 *
12 *  CopyRight (C) 1999 valette@crf.canon.fr
13 *
14 *  This code is heavilly inspired by the public specification of STREAM V2
15 *  that can be found at :
16 *
17 *      <http://www.chorus.com/Documentation/index.html> by following
18 *  the STREAM API Specification Document link.
19 *
20 *  The license and distribution terms for this file may be
[0c875c6a]21 *  found in the file LICENSE in this distribution or at
[c499856]22 *  http://www.rtems.org/license/LICENSE.
[a800d09c]23 */
24
25#ifndef LIBBSP_POWERPC_SS555_IRQ_IRQ_H
26#define LIBBSP_POWERPC_SS555_IRQ_IRQ_H
27
28#include <libcpu/irq.h>
29
30#ifndef ASM
31
32#ifdef __cplusplus
33extern "C" {
34#endif
35
[af2af2b4]36/*
37 *  These are no longer prototyped anywhere else. This appears to be
38 *  remnants of the IRQ code upgrade.
39 *
40 *  --joel 28 April 2010
41 */
42int CPU_install_rtems_irq_handler(const rtems_irq_connect_data* irq);
43int CPU_get_current_rtems_irq_handler(rtems_irq_connect_data* irq);
44int CPU_remove_rtems_irq_handler(const rtems_irq_connect_data* irq);
45int CPU_rtems_irq_mngt_set(rtems_irq_global_settings* config);
46int CPU_rtems_irq_mngt_get(rtems_irq_global_settings** config);
[f62c7daa]47void C_default_exception_handler(CPU_Exception_frame* excPtr);
[af2af2b4]48
[a800d09c]49/*
50 * The SS555 has no external interrupt controller chip, so use the standard
51 * routines from the CPU-dependent code.
[6128a4a]52 */
53#define BSP_install_rtems_irq_handler(ptr)      CPU_install_rtems_irq_handler(ptr)
[a800d09c]54#define BSP_get_current_rtems_irq_handler(ptr)  CPU_get_current_rtems_irq_handler(ptr)
55#define BSP_remove_rtems_irq_handler(ptr)       CPU_remove_rtems_irq_handler(ptr)
56#define BSP_rtems_irq_mngt_set(config)          CPU_rtems_irq_mngt_set(config)
57#define BSP_rtems_irq_mngt_get(config)          CPU_rtems_irq_mngt_get(config)
58#define BSP_rtems_irq_mng_init(cpuId)           CPU_rtems_irq_mng_init(cpuId)
59
60#ifdef __cplusplus
61}
62#endif
63
64#endif /* ASM */
65
66#endif /* LIBBSP_POWERPC_SS555_IRQ_IRQ_H */
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