source: rtems/c/src/lib/libbsp/powerpc/ss555/include/bsp.h @ 283e6f0

4.104.11
Last change on this file since 283e6f0 was 283e6f0, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 18, 2008 at 3:09:21 PM

2008-09-18 Joel Sherrill <joel.sherrill@…>

  • include/bsp.h: Eliminate definitions of BSP_LIBIO_MAX_FDS since this is NOT used anywhere.
  • Property mode set to 100644
File size: 2.1 KB
Line 
1/*  bsp.h
2 *
3 *  This include file contains all board IO definitions.
4 *
5 *  This file includes definitions for the Intec SS555.
6 *
7 *
8 *  SS555 port sponsored by Defence Research and Development Canada - Suffield
9 *  Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
10 *
11 *  Derived from c/src/lib/libbsp/powerpc/mbx8xx/include/bsp.h:
12 *
13 *  COPYRIGHT (c) 1989-1998.
14 *  On-Line Applications Research Corporation (OAR).
15 *
16 *  The license and distribution terms for this file may be
17 *  found in the file LICENSE in this distribution or at
18 *  http://www.rtems.com/license/LICENSE.
19 *
20 *  $Id$
21 */
22
23#ifndef _BSP_H
24#define _BSP_H
25
26#ifdef __cplusplus
27extern "C" {
28#endif
29
30#include <bspopts.h>
31
32#include <rtems.h>
33#include <rtems/console.h>
34#include <rtems/clockdrv.h>
35#include <mpc5xx.h>
36#include <mpc5xx/console.h>
37#include <libcpu/vectors.h>
38#include <bsp/irq.h>
39
40/*
41 * Clock definitions
42 */
43
44#define BSP_CRYSTAL_HZ   4000000        /* crystal frequency, Hz */
45#define BSP_CLOCK_HZ    40000000        /* CPU clock frequency, Hz
46
47/*
48 * I/O definitions
49 *
50 * The SS555 board includes a CPLD to control on-board features and
51 * off-board devices.
52 */
53typedef struct cpld_ {
54  uint8_t       cs3a[32];               /* Chip select 3A */
55  uint8_t       pad0[0x200000 - 0x000020];
56
57  uint8_t       cs3b[32];               /* Chip select 3B */
58  uint8_t       pad2[0x400000 - 0x200020];
59
60  uint8_t       cs3c[32];               /* Chip select 3C */
61  uint8_t       pad4[0x600000 - 0x400020];
62
63  uint8_t       cs3d[32];               /* Chip select 3D */
64  uint8_t       pad6[0x800000 - 0x600020];
65
66  uint8_t       serial_ints;    /* Enable/disable serial interrupts */
67  uint8_t       serial_resets;  /* Enable/disable serial resets */
68  uint8_t       serial_ack;     /* Acknowledge serial transfers */
69  uint8_t       pad8[0xA00000 - 0x800003];
70
71  uint8_t       iflash_writess; /* Enable/disable internal-flash writes */
72  uint8_t       nflash_writess; /* Enable/disable NAND-flash writes */
73  uint8_t       padA[0xC00000 - 0xA00002];
74} cpld_t;
75
76extern volatile cpld_t cpld;              /* defined in linkcmds */
77
78/* miscellaneous stuff assumed to exist */
79
80/*
81 *  Device Driver Table Entries
82 */
83
84/*
85 * NOTE: Use the standard Console driver entry
86 */
87
88/*
89 * NOTE: Use the standard Clock driver entry
90 */
91
92#ifdef __cplusplus
93}
94#endif
95
96#endif
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