source: rtems/c/src/lib/libbsp/powerpc/shared/vectors/vectors.h @ 73cdeb6

4.104.114.84.9
Last change on this file since 73cdeb6 was 73cdeb6, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on Jul 4, 2007 at 12:25:49 PM

merged individual exception handler code to a common one.

  • Property mode set to 100644
File size: 4.7 KB
Line 
1/*
2 * vectors.h Exception frame related contant and API.
3 *
4 *  This include file describe the data structure and the functions implemented
5 *  by rtems to handle exceptions.
6 *
7 *  CopyRight (C) 1999 valette@crf.canon.fr
8 *
9 *  The license and distribution terms for this file may be
10 *  found in found in the file LICENSE in this distribution or at
11 *  http://www.rtems.com/license/LICENSE.
12 *
13 *  $Id$
14 */
15#ifndef LIBBSP_POWERPC_SHARED_VECTORS_H
16#define LIBBSP_POWERPC_SHARED_VECTORS_H
17#include <libcpu/raw_exception.h>
18
19/*
20 * The callee (high level exception code written in C)
21 * will store the Link Registers (return address) at entry r1 + 4 !!!.
22 * So let room for it!!!.
23 */
24#define LINK_REGISTER_CALLEE_UPDATE_ROOM 4
25#define SRR0_FRAME_OFFSET 8
26#define SRR1_FRAME_OFFSET 12
27#define EXCEPTION_NUMBER_OFFSET 16
28#define GPR0_OFFSET 20
29#define GPR1_OFFSET 24
30#define GPR2_OFFSET 28
31#define GPR3_OFFSET 32
32#define GPR4_OFFSET 36
33#define GPR5_OFFSET 40
34#define GPR6_OFFSET 44
35#define GPR7_OFFSET 48
36#define GPR8_OFFSET 52
37#define GPR9_OFFSET 56
38#define GPR10_OFFSET 60
39#define GPR11_OFFSET 64
40#define GPR12_OFFSET 68
41#define GPR13_OFFSET 72
42#define GPR14_OFFSET 76
43#define GPR15_OFFSET 80
44#define GPR16_OFFSET 84
45#define GPR17_OFFSET 88
46#define GPR18_OFFSET 92
47#define GPR19_OFFSET 96
48#define GPR20_OFFSET 100
49#define GPR21_OFFSET 104
50#define GPR22_OFFSET 108
51#define GPR23_OFFSET 112
52#define GPR24_OFFSET 116
53#define GPR25_OFFSET 120
54#define GPR26_OFFSET 124
55#define GPR27_OFFSET 128
56#define GPR28_OFFSET 132
57#define GPR29_OFFSET 136
58#define GPR30_OFFSET 140
59#define GPR31_OFFSET 144
60#define EXC_CR_OFFSET 148
61#define EXC_CTR_OFFSET 152
62#define EXC_XER_OFFSET 156
63#define EXC_LR_OFFSET 160
64#define EXC_MSR_OFFSET 164
65#define EXC_DAR_OFFSET 168
66/*
67 * maintain the EABI requested 8 bytes aligment
68 * As SVR4 ABI requires 16, make it 16 (as some
69 * exception may need more registers to be processed...)
70 */
71#define    EXCEPTION_FRAME_END 176
72
73#ifndef ASM
74/*
75 * default raw exception handlers
76 * The "*_size" symbol is generated by the linker; prevent it from
77 * being accessed in one of the short data areas by declaring
78 * it as an array
79 */
80
81extern  void default_exception_vector_code_prolog();
82extern  unsigned int  default_exception_vector_code_prolog_size[];
83extern  void tgpr_clr_exception_vector_code_prolog();
84extern  unsigned int  tgpr_clr_exception_vector_code_prolog_size[];
85/*
86 * FIXME: these should move to a "irq_asm.h"
87 */
88extern  void external_exception_vector_prolog_code();
89extern  unsigned int  external_exception_vector_prolog_code_size[];
90extern  void decrementer_exception_vector_prolog_code();
91extern  unsigned int  decrementer_exception_vector_prolog_code_size[];
92extern  void pit_exception_vector_prolog_code();
93extern  unsigned int  pit_exception_vector_prolog_code_size[];
94extern  void fit_exception_vector_prolog_code();
95extern  unsigned int  fit_exception_vector_prolog_code_size[];
96
97/* codemove is like memmove, but it also gets the cache line size
98 * as 4th parameter to synchronize them. If this last parameter is
99 * zero, it performs more or less like memmove. No copy is performed if
100 * source and destination addresses are equal. However the caches
101 * are synchronized. Note that the size is always rounded up to the
102 * next mutiple of 4.
103 */
104extern void * codemove(void *, const void *, unsigned int, unsigned long);
105extern void exception_nop_enable(const rtems_raw_except_connect_data* ptr);
106extern int  exception_always_enabled(const rtems_raw_except_connect_data* ptr);
107extern void initialize_exceptions();
108
109typedef struct {
110  unsigned      EXC_SRR0;
111  unsigned      EXC_SRR1;
112  unsigned      _EXC_number;
113  unsigned      GPR0;
114  unsigned      GPR1;
115  unsigned      GPR2;
116  unsigned      GPR3;
117  unsigned      GPR4;
118  unsigned      GPR5;
119  unsigned      GPR6;
120  unsigned      GPR7;
121  unsigned      GPR8;
122  unsigned      GPR9;
123  unsigned      GPR10;
124  unsigned      GPR11;
125  unsigned      GPR12;
126  unsigned      GPR13;
127  unsigned      GPR14;
128  unsigned      GPR15;
129  unsigned      GPR16;
130  unsigned      GPR17;
131  unsigned      GPR18;
132  unsigned      GPR19;
133  unsigned      GPR20;
134  unsigned      GPR21;
135  unsigned      GPR22;
136  unsigned      GPR23;
137  unsigned      GPR24;
138  unsigned      GPR25;
139  unsigned      GPR26;
140  unsigned      GPR27;
141  unsigned      GPR28;
142  unsigned      GPR29;
143  unsigned      GPR30;
144  unsigned      GPR31;
145  unsigned      EXC_CR;
146  unsigned      EXC_CTR;
147  unsigned      EXC_XER;
148  unsigned      EXC_LR;
149  unsigned      EXC_MSR;
150  unsigned      EXC_DAR;
151}BSP_Exception_frame;
152
153typedef void (*exception_handler_t) (BSP_Exception_frame* excPtr);
154extern exception_handler_t globalExceptHdl;
155/*
156 * Compatibility with pc386
157 */
158typedef BSP_Exception_frame CPU_Exception_frame;
159typedef exception_handler_t cpuExcHandlerType;
160
161/*
162 * dummy functions for exception interface
163 */
164void exception_nop_enable(const rtems_raw_except_connect_data* ptr);
165int exception_always_enabled(const rtems_raw_except_connect_data* ptr);
166
167#endif /* ASM */
168
169#endif /* LIBBSP_POWERPC_MCP750_VECTORS_H */
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