source: rtems/c/src/lib/libbsp/powerpc/shared/vectors/vectors.h @ 2ae52c75

Last change on this file since 2ae52c75 was 2ae52c75, checked in by Joel Sherrill <joel.sherrill@…>, on 03/18/03 at 19:24:59

2003-03-18 Till Straumann <strauman@…>

PR 356/bsps
This patch makes RTEMS/powerpc/shared EABI compliant.

  • irq/irq_init.c, start/Makefile.am, start/start.S, startup/bspstart.c, startup/pgtbl_setup.c, vectors/vectors.h, vectors/vectors_init.c: zero_bss() should clear not only bss but sbss and sbss2 also (this is probably a bugfix, as sbss/sbss2 are probably used even if -msdata=eabi is not specified).
  • start/rtems_crti.S: New file which must be linked immediately after ecrti.o. rtems_crti.o contains a code snippet who lets init() return immediately. Also, a new entry point '_init' to the C++ Ctors is generated for use by the RTEMS Thread_Handler.
  • Property mode set to 100644
File size: 3.7 KB
Line 
1/*
2 * vectors.h Exception frame related contant and API.
3 *
4 *  This include file describe the data structure and the functions implemented
5 *  by rtems to handle exceptions.
6 *
7 *  CopyRight (C) 1999 valette@crf.canon.fr
8 *
9 *  The license and distribution terms for this file may be
10 *  found in found in the file LICENSE in this distribution or at
11 *  http://www.OARcorp.com/rtems/license.html.
12 *
13 *  $Id$
14 */
15#ifndef LIBBSP_POWERPC_MCP750_VECTORS_H
16#define LIBBSP_POWERPC_MCP750_VECTORS_H
17
18/*
19 * The callee (high level exception code written in C)
20 * will store the Link Registers (return address) at entry r1 + 4 !!!.
21 * So let room for it!!!.
22 */
23#define LINK_REGISTER_CALLEE_UPDATE_ROOM 4
24#define SRR0_FRAME_OFFSET 8
25#define SRR1_FRAME_OFFSET 12
26#define EXCEPTION_NUMBER_OFFSET 16
27#define GPR0_OFFSET 20
28#define GPR1_OFFSET 24
29#define GPR2_OFFSET 28
30#define GPR3_OFFSET 32
31#define GPR4_OFFSET 36
32#define GPR5_OFFSET 40
33#define GPR6_OFFSET 44
34#define GPR7_OFFSET 48
35#define GPR8_OFFSET 52
36#define GPR9_OFFSET 56
37#define GPR10_OFFSET 60
38#define GPR11_OFFSET 64
39#define GPR12_OFFSET 68
40#define GPR13_OFFSET 72
41#define GPR14_OFFSET 76
42#define GPR15_OFFSET 80
43#define GPR16_OFFSET 84
44#define GPR17_OFFSET 88
45#define GPR18_OFFSET 92
46#define GPR19_OFFSET 96
47#define GPR20_OFFSET 100
48#define GPR21_OFFSET 104
49#define GPR22_OFFSET 108
50#define GPR23_OFFSET 112
51#define GPR24_OFFSET 116
52#define GPR25_OFFSET 120
53#define GPR26_OFFSET 124
54#define GPR27_OFFSET 128
55#define GPR28_OFFSET 132
56#define GPR29_OFFSET 136
57#define GPR30_OFFSET 140
58#define GPR31_OFFSET 144
59#define EXC_CR_OFFSET 148
60#define EXC_CTR_OFFSET 152
61#define EXC_XER_OFFSET 156
62#define EXC_LR_OFFSET 160
63#define EXC_MSR_OFFSET 164
64#define EXC_DAR_OFFSET 168
65/*
66 * maintain the EABI requested 8 bytes aligment
67 * As SVR4 ABI requires 16, make it 16 (as some
68 * exception may need more registers to be processed...)
69 */
70#define    EXCEPTION_FRAME_END 176
71
72#ifndef ASM
73/*
74 * default raw exception handlers
75 */
76
77extern  void default_exception_vector_code_prolog();
78/* This symbol is generated by the linker; prevent it from
79 * being accessed in one of the short data areas by declaring
80 * it as an array
81 */
82extern  int  default_exception_vector_code_prolog_size[];
83
84/* codemove is like memmove, but it also gets the cache line size
85 * as 4th parameter to synchronize them. If this last parameter is
86 * zero, it performs more or less like memmove. No copy is performed if
87 * source and destination addresses are equal. However the caches
88 * are synchronized. Note that the size is always rounded up to the
89 * next mutiple of 4.
90 */
91extern void * codemove(void *, const void *, unsigned int, unsigned long);
92extern void initialize_exceptions();
93
94typedef struct {
95  unsigned      EXC_SRR0;
96  unsigned      EXC_SRR1;
97  unsigned      _EXC_number;
98  unsigned      GPR0;
99  unsigned      GPR1;
100  unsigned      GPR2;
101  unsigned      GPR3;
102  unsigned      GPR4;
103  unsigned      GPR5;
104  unsigned      GPR6;
105  unsigned      GPR7;
106  unsigned      GPR8;
107  unsigned      GPR9;
108  unsigned      GPR10;
109  unsigned      GPR11;
110  unsigned      GPR12;
111  unsigned      GPR13;
112  unsigned      GPR14;
113  unsigned      GPR15;
114  unsigned      GPR16;
115  unsigned      GPR17;
116  unsigned      GPR18;
117  unsigned      GPR19;
118  unsigned      GPR20;
119  unsigned      GPR21;
120  unsigned      GPR22;
121  unsigned      GPR23;
122  unsigned      GPR24;
123  unsigned      GPR25;
124  unsigned      GPR26;
125  unsigned      GPR27;
126  unsigned      GPR28;
127  unsigned      GPR29;
128  unsigned      GPR30;
129  unsigned      GPR31;
130  unsigned      EXC_CR;
131  unsigned      EXC_CTR;
132  unsigned      EXC_XER;
133  unsigned      EXC_LR;
134  unsigned      EXC_MSR;
135  unsigned      EXC_DAR;
136}BSP_Exception_frame;
137
138
139typedef void (*exception_handler_t) (BSP_Exception_frame* excPtr);
140extern exception_handler_t globalExceptHdl;
141/*
142 * Compatibility with pc386
143 */
144typedef BSP_Exception_frame CPU_Exception_frame;
145typedef exception_handler_t cpuExcHandlerType;
146
147#endif /* ASM */
148
149#endif /* LIBBSP_POWERPC_MCP750_VECTORS_H */
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