1 | /* |
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2 | * (c) 1999, Eric Valette valette@crf.canon.fr |
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3 | * |
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4 | * |
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5 | * This file contains the assembly code for the PowerPC |
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6 | * exception veneers for RTEMS. |
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7 | * |
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8 | * $Id$ |
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9 | */ |
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10 | |
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11 | |
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12 | |
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13 | #include <bsp/vectors.h> |
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14 | #include <libcpu/cpu.h> |
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15 | #include <rtems/score/targopts.h> |
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16 | #include "asm.h" |
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17 | |
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18 | |
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19 | #define SYNC \ |
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20 | sync; \ |
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21 | isync |
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22 | |
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23 | PUBLIC_VAR (__rtems_start) |
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24 | .section .entry_point_section,"awx",@progbits |
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25 | /* |
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26 | * Entry point information used by bootloader code |
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27 | */ |
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28 | SYM (__rtems_start): |
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29 | .long __rtems_entry_point |
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30 | |
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31 | /* |
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32 | * end of special Entry point section |
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33 | */ |
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34 | .text |
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35 | .p2align 5 |
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36 | |
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37 | PUBLIC_VAR(default_exception_vector_code_prolog) |
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38 | SYM (default_exception_vector_code_prolog): |
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39 | /* |
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40 | * let room for exception frame |
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41 | */ |
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42 | stwu r1, - (EXCEPTION_FRAME_END)(r1) |
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43 | stw r3, GPR3_OFFSET(r1) |
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44 | stw r2, GPR2_OFFSET(r1) |
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45 | mflr r2 |
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46 | stw r2, EXC_LR_OFFSET(r1) |
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47 | bl 0f |
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48 | 0: /* |
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49 | * r3 = exception vector entry point |
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50 | * (256 * vector number) + few instructions |
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51 | */ |
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52 | mflr r3 |
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53 | /* |
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54 | * r3 = r3 >> 8 = vector |
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55 | */ |
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56 | srwi r3,r3,8 |
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57 | ba push_normalized_frame |
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58 | |
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59 | PUBLIC_VAR (default_exception_vector_code_prolog_size) |
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60 | |
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61 | default_exception_vector_code_prolog_size= . - default_exception_vector_code_prolog |
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62 | |
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63 | .p2align 5 |
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64 | PUBLIC_VAR (push_normalized_frame) |
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65 | SYM (push_normalized_frame): |
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66 | stw r3, EXCEPTION_NUMBER_OFFSET(r1) |
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67 | stw r0, GPR0_OFFSET(r1) |
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68 | mfsrr0 r2 |
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69 | stw r2, SRR0_FRAME_OFFSET(r1) |
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70 | mfsrr1 r3 |
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71 | stw r3, SRR1_FRAME_OFFSET(r1) |
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72 | /* |
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73 | * Save general purpose registers |
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74 | * Already saved in prolog : R1, R2, R3, LR. |
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75 | * Saved a few line above : R0 |
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76 | * |
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77 | * Manual says that "stmw" instruction may be slower than |
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78 | * series of individual "stw" but who cares about performance |
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79 | * for the DEFAULT exception handler? |
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80 | */ |
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81 | stmw r4, GPR4_OFFSET(r1) /* save R4->R31 */ |
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82 | |
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83 | mfcr r31 |
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84 | stw r31, EXC_CR_OFFSET(r1) |
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85 | mfctr r30 |
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86 | stw r30, EXC_CTR_OFFSET(r1) |
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87 | mfxer r28 |
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88 | stw r28, EXC_XER_OFFSET(r1) |
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89 | /* |
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90 | * compute SP at exception entry |
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91 | */ |
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92 | addi r2, r1, EXCEPTION_FRAME_END |
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93 | /* |
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94 | * store it at the right place |
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95 | */ |
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96 | stw r2, GPR1_OFFSET(r1) |
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97 | /* |
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98 | * Enable data and instruction address translation, exception nesting |
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99 | */ |
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100 | mfmsr r3 |
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101 | ori r3,r3, MSR_RI | MSR_IR | MSR_DR |
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102 | mtmsr r3 |
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103 | SYNC |
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104 | |
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105 | /* |
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106 | * Call C exception handler |
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107 | */ |
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108 | /* |
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109 | * store the execption frame address in r3 (first param) |
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110 | */ |
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111 | addi r3, r1, 0x8 |
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112 | /* |
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113 | * globalExceptHdl(r3) |
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114 | */ |
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115 | addis r4, 0, globalExceptHdl@ha |
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116 | lwz r5, globalExceptHdl@l(r4) |
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117 | mtlr r5 |
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118 | blrl |
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119 | /* |
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120 | * Restore registers status |
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121 | */ |
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122 | lwz r31, EXC_CR_OFFSET(r1) |
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123 | mtcr r31 |
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124 | lwz r30, EXC_CTR_OFFSET(r1) |
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125 | mtctr r30 |
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126 | lwz r29, EXC_LR_OFFSET(r1) |
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127 | mtlr r29 |
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128 | lwz r28, EXC_XER_OFFSET(r1) |
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129 | mtxer r28 |
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130 | |
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131 | lmw r4, GPR4_OFFSET(r1) |
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132 | lwz r2, GPR2_OFFSET(r1) |
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133 | lwz r0, GPR0_OFFSET(r1) |
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134 | |
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135 | /* |
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136 | * Disable data and instruction translation. Make path non recoverable... |
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137 | */ |
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138 | mfmsr r3 |
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139 | xori r3, r3, MSR_RI | MSR_IR | MSR_DR |
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140 | mtmsr r3 |
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141 | SYNC |
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142 | /* |
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143 | * Restore rfi related settings |
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144 | */ |
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145 | |
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146 | lwz r3, SRR1_FRAME_OFFSET(r1) |
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147 | mtsrr1 r3 |
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148 | lwz r3, SRR0_FRAME_OFFSET(r1) |
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149 | mtsrr0 r3 |
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150 | |
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151 | lwz r3, GPR3_OFFSET(r1) |
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152 | addi r1,r1, EXCEPTION_FRAME_END |
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153 | SYNC |
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154 | rfi |
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