[902a417] | 1 | /* $Id$ */ |
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| 2 | #include <rtems.h> |
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| 3 | #include <libcpu/spr.h> |
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| 4 | #include <libcpu/cpuIdent.h> |
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| 5 | #include <rtems/bspIo.h> |
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| 6 | |
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[ac7af4a] | 7 | /* |
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[f774fc06] | 8 | * Authorship |
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| 9 | * ---------- |
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| 10 | * This software was created by |
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| 11 | * Till Straumann <strauman@slac.stanford.edu>, 2005, |
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| 12 | * Stanford Linear Accelerator Center, Stanford University. |
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[ac7af4a] | 13 | * |
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[f774fc06] | 14 | * Acknowledgement of sponsorship |
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| 15 | * ------------------------------ |
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| 16 | * This software was produced by |
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| 17 | * the Stanford Linear Accelerator Center, Stanford University, |
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| 18 | * under Contract DE-AC03-76SFO0515 with the Department of Energy. |
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[ac7af4a] | 19 | * |
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[f774fc06] | 20 | * Government disclaimer of liability |
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| 21 | * ---------------------------------- |
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| 22 | * Neither the United States nor the United States Department of Energy, |
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| 23 | * nor any of their employees, makes any warranty, express or implied, or |
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| 24 | * assumes any legal liability or responsibility for the accuracy, |
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| 25 | * completeness, or usefulness of any data, apparatus, product, or process |
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| 26 | * disclosed, or represents that its use would not infringe privately owned |
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| 27 | * rights. |
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[ac7af4a] | 28 | * |
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[f774fc06] | 29 | * Stanford disclaimer of liability |
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| 30 | * -------------------------------- |
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| 31 | * Stanford University makes no representations or warranties, express or |
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| 32 | * implied, nor assumes any liability for the use of this software. |
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[ac7af4a] | 33 | * |
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[f774fc06] | 34 | * Stanford disclaimer of copyright |
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| 35 | * -------------------------------- |
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| 36 | * Stanford University, owner of the copyright, hereby disclaims its |
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| 37 | * copyright and all other rights in this software. Hence, anyone may |
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[ac7af4a] | 38 | * freely use it for any purpose without restriction. |
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| 39 | * |
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[f774fc06] | 40 | * Maintenance of notices |
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| 41 | * ---------------------- |
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| 42 | * In the interest of clarity regarding the origin and status of this |
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| 43 | * SLAC software, this and all the preceding Stanford University notices |
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| 44 | * are to remain affixed to any copy or derivative of this software made |
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| 45 | * or distributed by the recipient and are to be affixed to any copy of |
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| 46 | * software made or distributed by the recipient that contains a copy or |
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| 47 | * derivative of this software. |
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[ac7af4a] | 48 | * |
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[f774fc06] | 49 | * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 |
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[ac7af4a] | 50 | */ |
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[f774fc06] | 51 | |
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[902a417] | 52 | |
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| 53 | /* Simple memory probing routine |
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[ac7af4a] | 54 | * |
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| 55 | * - call from MMU-disabled section to avoid having to |
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[902a417] | 56 | * set up mappings. |
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| 57 | * NOTE: this implies WIMG = 0011 |
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| 58 | * - call AFTER image is at its destination and PRIOR |
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| 59 | * to setting up the heap or using any memory beyond |
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| 60 | * __rtems_end, i.e., the probing algorithm may safely |
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| 61 | * tamper with memory > __rtems_end. |
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| 62 | * - MUST lock caches since we're gonna hit space with |
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| 63 | * no memory attached. |
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| 64 | * |
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| 65 | * ASSUMPTIONS: |
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| 66 | * o image occupies addresses between 0..__rtems_end |
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| 67 | * o memory size is a multiple of 1<<LD_MEM_PROBE_STEP |
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| 68 | * |
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| 69 | * CAVEATS: |
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| 70 | * o all caches must be disabled or locked (some |
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| 71 | * boards really don't like it if you try to |
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| 72 | * cache physical addresses with nothing attached) |
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| 73 | * and this is highly CPU dependent :-(... |
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| 74 | * |
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| 75 | * - RETURNS size of memory detected in bytes or 0 on |
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| 76 | * error. |
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| 77 | */ |
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| 78 | |
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| 79 | /* declare as an array so the compiler doesn't generate |
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| 80 | * a reloc to .sdata & friends |
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| 81 | */ |
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| 82 | extern uint32_t __rtems_end[]; |
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| 83 | |
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| 84 | #ifndef LD_MEM_PROBE_STEP |
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| 85 | #define LD_MEM_PROBE_STEP (24) /* 16MB */ |
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| 86 | #endif |
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| 87 | |
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| 88 | #define TAG 0xfeedcafe |
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| 89 | |
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| 90 | #define __DO_ALIGN(a, s) (((uint32_t)(a) + (s)-1) & ~((s)-1)) |
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| 91 | #define __ALIGN(a) __DO_ALIGN(a, (1<<LD_MEM_PROBE_STEP)) |
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| 92 | |
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| 93 | #define SWITCH_MSR(msr) \ |
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[689429f8] | 94 | do { \ |
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| 95 | register uint32_t __rr; \ |
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[902a417] | 96 | asm volatile( \ |
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| 97 | " mtsrr1 %0 \n" \ |
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| 98 | " bl 1f \n" \ |
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| 99 | "1: mflr %0 \n" \ |
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| 100 | " addi %0, %0, 1f-1b \n"\ |
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| 101 | " mtsrr0 %0 \n" \ |
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| 102 | " sync \n" \ |
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| 103 | " rfi \n" \ |
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| 104 | "1: \n" \ |
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[689429f8] | 105 | :"=b&"(__rr) \ |
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| 106 | :"0"(msr) \ |
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| 107 | :"lr","memory" \ |
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| 108 | ); \ |
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| 109 | } while (0) |
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[902a417] | 110 | |
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| 111 | SPR_RW(L2CR) |
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| 112 | SPR_RW(L3CR) |
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| 113 | SPR_RO(PVR) |
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| 114 | SPR_RW(HID0) |
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| 115 | |
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| 116 | |
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| 117 | /* Shouldn't matter if the caches are enabled or not... */ |
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| 118 | |
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| 119 | /* FIXME: This should go into libcpu, really... */ |
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| 120 | int |
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| 121 | CPU_lockUnlockCaches(register int doLock) |
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| 122 | { |
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| 123 | register uint32_t v, x; |
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| 124 | if ( _read_MSR() & MSR_VE ) { |
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| 125 | #define DSSALL 0x7e00066c /* dssall opcode */ |
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[bd918ff7] | 126 | __asm__ volatile(" .long %0"::"i"(DSSALL)); |
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[902a417] | 127 | #undef DSSALL |
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| 128 | } |
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| 129 | asm volatile("sync"); |
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| 130 | switch ( _read_PVR()>>16 ) { |
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| 131 | default: printk(__FILE__" CPU_lockUnlockCaches(): unknown CPU (PVR = 0x%08x)\n",_read_PVR()); |
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| 132 | return -1; |
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| 133 | case PPC_750: printk("CPU_lockUnlockCaches(): Can't lock L2 on a mpc750, sorry :-(\n"); |
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| 134 | return -2; /* cannot lock L2 :-( */ |
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[ac7af4a] | 135 | case PPC_7455: |
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| 136 | case PPC_7457: |
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[902a417] | 137 | v = _read_L3CR(); |
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| 138 | x = 1<<(31-9); |
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| 139 | v = doLock ? v | x : v & ~x; |
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| 140 | _write_L3CR(v); |
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| 141 | |
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| 142 | v = _read_L2CR(); |
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| 143 | x = 1<<(31-11); |
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| 144 | v = doLock ? v | x : v & ~x; |
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| 145 | _write_L2CR(v); |
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| 146 | break; |
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| 147 | |
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| 148 | case PPC_7400: |
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| 149 | v = _read_L2CR(); |
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| 150 | x = 1<<(31-21); |
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| 151 | v = doLock ? v | x : v & ~x; |
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| 152 | _write_L2CR(v); |
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| 153 | break; |
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| 154 | case PPC_603: |
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| 155 | case PPC_604: |
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| 156 | case PPC_604e: |
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| 157 | break; |
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| 158 | } |
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[ac7af4a] | 159 | |
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[902a417] | 160 | v = _read_HID0(); |
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| 161 | x = 1<<(31-19); |
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| 162 | v = doLock ? v | x : v & ~x; |
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| 163 | _write_HID0(v); |
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[689429f8] | 164 | asm volatile("sync":::"memory"); |
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[902a417] | 165 | return 0; |
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| 166 | } |
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| 167 | |
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| 168 | uint32_t |
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[2fa726e] | 169 | probeMemoryEnd(void) |
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[902a417] | 170 | { |
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| 171 | register volatile uint32_t *probe; |
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| 172 | register uint32_t scratch; |
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| 173 | register uint32_t tag = TAG; |
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| 174 | register uint32_t flags; |
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| 175 | |
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| 176 | probe = (volatile uint32_t *)__ALIGN(__rtems_end); |
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| 177 | |
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| 178 | /* Start with some checks. We avoid using any services |
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| 179 | * such as 'printk' so we can run at a very early stage. |
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| 180 | * Also, we *try* to avoid to really rely on the memory |
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| 181 | * being unused by restoring the probed locations and |
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| 182 | * keeping everything in registers. Hence we could |
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| 183 | * even probe our own stack :-) |
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| 184 | */ |
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| 185 | |
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| 186 | if ( CPU_lockUnlockCaches(1) ) |
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| 187 | return 0; |
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| 188 | |
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[af3fcf12] | 189 | _CPU_MSR_GET(flags); |
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[902a417] | 190 | |
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| 191 | SWITCH_MSR( flags & ~(MSR_EE|MSR_DR|MSR_IR) ); |
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| 192 | |
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| 193 | for ( ; (uint32_t)probe ; probe += (1<<LD_MEM_PROBE_STEP)/sizeof(*probe) ) { |
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| 194 | |
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| 195 | /* see if by chance our tag is already there */ |
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| 196 | if ( tag == (scratch = *probe) ) { |
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| 197 | /* try another tag */ |
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| 198 | tag = ~tag; |
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| 199 | } |
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| 200 | *probe = tag; |
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| 201 | |
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| 202 | /* make sure it's written out */ |
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[689429f8] | 203 | asm volatile ("sync":::"memory"); |
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[902a417] | 204 | |
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| 205 | /* try to read back */ |
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| 206 | if ( tag != *probe ) { |
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| 207 | break; |
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| 208 | } |
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| 209 | /* restore */ |
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| 210 | *probe = scratch; |
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| 211 | /* make sure the icache is not contaminated */ |
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[689429f8] | 212 | asm volatile ("sync; icbi 0, %0"::"r"(probe):"memory"); |
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[902a417] | 213 | } |
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| 214 | |
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| 215 | SWITCH_MSR(flags); |
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| 216 | |
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| 217 | CPU_lockUnlockCaches(0); |
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| 218 | |
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| 219 | return (uint32_t) probe; |
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| 220 | } |
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