source: rtems/c/src/lib/libbsp/powerpc/shared/startup/bspstart.c @ db77b92

4.104.11
Last change on this file since db77b92 was db77b92, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 15, 2008 at 10:05:19 PM

2008-09-15 Joel Sherrill <joel.sherrill@…>

  • shared/startup/bspstart.c, shared/startup/pretaskinghook.c: Add use of bsp_get_work_area() in its own file and rely on BSP Framework to perform more initialization.
  • shared/startup/bspgetworkarea.c: New file.
  • Property mode set to 100644
File size: 10.0 KB
Line 
1/*
2 *  This routine starts the application.  It includes application,
3 *  board, and monitor specific initialization and configuration.
4 *  The generic CPU dependent initialization has been performed
5 *  before this routine is invoked.
6 *
7 *  COPYRIGHT (c) 1989-2007.
8 *  On-Line Applications Research Corporation (OAR).
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.rtems.com/license/LICENSE.
13 *
14 *  Modified to support the MCP750.
15 *  Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
16 *
17 *  $Id$
18 */
19
20#warning The interrupt disable mask is now stored in SPRG0, please verify that this is compatible to this BSP (see also bootcard.c).
21
22#include <string.h>
23
24#include <bsp.h>
25#include <rtems/bspIo.h>
26#include <bsp/consoleIo.h>
27#include <libcpu/spr.h>
28#include <bsp/residual.h>
29#include <bsp/pci.h>
30#include <bsp/openpic.h>
31#include <bsp/irq.h>
32#include <libcpu/bat.h>
33#include <libcpu/pte121.h>
34#include <libcpu/cpuIdent.h>
35#include <bsp/vectors.h>
36#include <bsp/motorola.h>
37#include <rtems/powerpc/powerpc.h>
38
39extern void _return_to_ppcbug(void);
40extern unsigned long __rtems_end[];
41extern void L1_caches_enables(void);
42extern unsigned get_L2CR(void);
43extern void set_L2CR(unsigned);
44extern Triv121PgTbl BSP_pgtbl_setup(unsigned long);
45extern void                     BSP_pgtbl_activate(Triv121PgTbl);
46extern void                     BSP_vme_config(void);
47
48SPR_RW(SPRG1)
49
50#if defined(DEBUG_BATS)
51extern void ShowBATS(void);
52#endif
53
54/*
55 *  Driver configuration parameters
56 */
57uint32_t   bsp_clicks_per_usec;
58
59/*
60 * Copy of residuals passed by firmware
61 */
62RESIDUAL residualCopy;
63/*
64 * Copy Additional boot param passed by boot loader
65 */
66#define MAX_LOADER_ADD_PARM 80
67char loaderParam[MAX_LOADER_ADD_PARM];
68
69char *BSP_commandline_string = loaderParam;
70/*
71 * Vital Board data Start using DATA RESIDUAL
72 */
73/*
74 * Total memory using RESIDUAL DATA
75 */
76unsigned int BSP_mem_size;
77
78/*
79 * PCI Bus Frequency
80 */
81unsigned int BSP_bus_frequency;
82/*
83 * processor clock frequency
84 */
85unsigned int BSP_processor_frequency;
86/*
87 * Time base divisior (how many tick for 1 second).
88 */
89unsigned int BSP_time_base_divisor;
90/*
91 * system init stack
92 */
93#define INIT_STACK_SIZE 0x1000
94
95void BSP_panic(char *s)
96{
97  printk("%s PANIC %s\n",_RTEMS_version, s);
98  __asm__ __volatile ("sc");
99}
100
101void _BSP_Fatal_error(unsigned int v)
102{
103  printk("%s PANIC ERROR %x\n",_RTEMS_version, v);
104  __asm__ __volatile ("sc");
105}
106
107/*
108 *  Use the shared implementations of the following routines
109 */
110
111void save_boot_params(
112  RESIDUAL *r3,
113  void     *r4,
114  void     *r5,
115  char     *additional_boot_options
116)
117{
118
119  residualCopy = *r3;
120  strncpy(loaderParam, additional_boot_options, MAX_LOADER_ADD_PARM);
121  loaderParam[MAX_LOADER_ADD_PARM - 1] ='\0';
122}
123
124#if defined(mvme2100)
125unsigned int EUMBBAR;
126
127/*
128 * Return the current value of the Embedded Utilities Memory Block Base Address
129 * Register (EUMBBAR) as read from the processor configuration register using
130 * Processor Address Map B (CHRP).
131 */ 
132unsigned int get_eumbbar(void) {
133  out_le32( (uint32_t*)0xfec00000, 0x80000078 );
134  return in_le32( (uint32_t*)0xfee00000 );
135}
136#endif
137
138/*
139 *  bsp_start
140 *
141 *  This routine does the bulk of the system initialization.
142 */
143
144void bsp_start( void )
145{
146  unsigned char *stack;
147#if !defined(mvme2100)
148  unsigned l2cr;
149#endif
150  uint32_t intrStackStart;
151  uint32_t intrStackSize;
152  ppc_cpu_id_t myCpu;
153  ppc_cpu_revision_t myCpuRevision;
154  prep_t boardManufacturer;
155  motorolaBoard myBoard;
156  Triv121PgTbl  pt=0;
157
158  /*
159   * Get CPU identification dynamically. Note that the get_ppc_cpu_type()
160   * function store the result in global variables so that it can be used
161   * later...
162   */
163  myCpu         = get_ppc_cpu_type();
164  myCpuRevision = get_ppc_cpu_revision();
165
166  /*
167   * Init MMU block address translation to enable hardware access
168   */
169
170#if !defined(mvme2100)
171  /*
172   * PC legacy IO space used for inb/outb and all PC compatible hardware
173   */
174  setdbat(1, _IO_BASE, _IO_BASE, 0x10000000, IO_PAGE);
175#endif
176
177  /*
178   * PCI devices memory area. Needed to access OpenPIC features
179   * provided by the Raven
180   *
181   * T. Straumann: give more PCI address space
182   */
183  setdbat(2, PCI_MEM_BASE+PCI_MEM_WIN0, PCI_MEM_BASE+PCI_MEM_WIN0, 0x10000000, IO_PAGE);
184
185  /*
186   * Must have acces to open pic PCI ACK registers provided by the RAVEN
187   */
188  setdbat(3, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE);
189
190#if defined(mvme2100)
191  /* Need 0xfec00000 mapped for this */
192  EUMBBAR = get_eumbbar(); 
193#endif
194
195  /*
196   * enables L1 Cache. Note that the L1_caches_enables() codes checks for
197   * relevant CPU type so that the reason why there is no use of myCpu...
198   */
199  L1_caches_enables();
200
201#if !defined(mvme2100)
202  /*
203   * Enable L2 Cache. Note that the set_L2CR(L2CR) codes checks for
204   * relevant CPU type (mpc750)...
205   */
206  l2cr = get_L2CR();
207#ifdef SHOW_LCR2_REGISTER
208  printk("Initial L2CR value = %x\n", l2cr);
209#endif
210  if ( (! (l2cr & 0x80000000)) && ((int) l2cr == -1))
211    set_L2CR(0xb9A14000);
212#endif
213
214  /*
215   * the initial stack  has aready been set to this value in start.S
216   * so there is no need to set it in r1 again... It is just for info
217   * so that It can be printed without accessing R1.
218   */
219  stack = ((unsigned char*) __rtems_end) +
220               INIT_STACK_SIZE - PPC_MINIMUM_STACK_FRAME_SIZE;
221
222  /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */
223  *((uint32_t*)stack) = 0;
224
225  /*
226   * Initialize the interrupt related settings.
227   */
228  intrStackStart = (uint32_t) __rtems_end + INIT_STACK_SIZE;
229  intrStackSize = rtems_configuration_get_interrupt_stack_size();
230
231  /*
232   * Initialize default raw exception handlers.
233   */
234  ppc_exc_initialize(
235    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
236    intrStackStart,
237    intrStackSize
238  );
239
240  select_console(CONSOLE_LOG);
241
242  /*
243   * We check that the keyboard is present and immediately
244   * select the serial console if not.
245   */
246#if defined(BSP_KBD_IOBASE)
247  { int err;
248    err = kbdreset();
249    if (err) select_console(CONSOLE_SERIAL);
250  }
251#else
252  select_console(CONSOLE_SERIAL);
253#endif
254
255  boardManufacturer   =  checkPrepBoardType(&residualCopy);
256  if (boardManufacturer != PREP_Motorola) {
257    printk("Unsupported hardware vendor\n");
258    while (1);
259  }
260  myBoard = getMotorolaBoard();
261
262  printk("-----------------------------------------\n");
263  printk("Welcome to %s on %s\n", _RTEMS_version,
264                                    motorolaBoardToString(myBoard));
265  printk("-----------------------------------------\n");
266#ifdef SHOW_MORE_INIT_SETTINGS
267  printk("Residuals are located at %x\n", (unsigned) &residualCopy);
268  printk("Additionnal boot options are %s\n", loaderParam);
269  printk("Initial system stack at %x\n",stack);
270  printk("Software IRQ stack starts at %x with size %u\n", intrStackStart, intrStackSize);
271  printk("-----------------------------------------\n");
272#endif
273
274#ifdef TEST_RETURN_TO_PPCBUG
275  printk("Hit <Enter> to return to PPCBUG monitor\n");
276  printk("When Finished hit GO. It should print <Back from monitor>\n");
277  debug_getc();
278  _return_to_ppcbug();
279  printk("Back from monitor\n");
280  _return_to_ppcbug();
281#endif /* TEST_RETURN_TO_PPCBUG  */
282
283#ifdef SHOW_MORE_INIT_SETTINGS
284  printk("Going to start PCI buses scanning and initialization\n");
285#endif
286
287  pci_initialize();
288  {
289    const struct _int_map *bspmap  = motorolaIntMap(currentBoard);
290    if( bspmap ) {
291       printk("pci : Configuring interrupt routing for '%s'\n",
292          motorolaBoardToString(currentBoard));
293       FixupPCI(bspmap, motorolaIntSwizzle(currentBoard));
294    }
295    else
296       printk("pci : Interrupt routing not available for this bsp\n");
297 }
298
299#ifdef SHOW_MORE_INIT_SETTINGS
300  printk("Number of PCI buses found is : %d\n", pci_bus_count());
301#endif
302#ifdef TEST_RAW_EXCEPTION_CODE
303  printk("Testing exception handling Part 1\n");
304  /*
305   * Cause a software exception
306   */
307  __asm__ __volatile ("sc");
308  /*
309   * Check we can still catch exceptions and return coorectly.
310   */
311  printk("Testing exception handling Part 2\n");
312  __asm__ __volatile ("sc");
313
314  /*
315   * Somehow doing the above seems to clobber SPRG0 on the mvme2100.  The
316   * interrupt disable mask is stored in SPRG0. Is this a problem?
317   */
318  ppc_interrupt_set_disable_mask( PPC_INTERRUPT_DISABLE_MASK_DEFAULT);
319
320#endif
321
322/* See above */
323#warning The interrupt disable mask is now stored in SPRG0, please verify that this is compatible to this BSP (see also bootcard.c).
324
325  BSP_mem_size            = residualCopy.TotalMemory;
326  BSP_bus_frequency       = residualCopy.VitalProductData.ProcessorBusHz;
327  BSP_processor_frequency = residualCopy.VitalProductData.ProcessorHz;
328  BSP_time_base_divisor   = (residualCopy.VitalProductData.TimeBaseDivisor?
329                    residualCopy.VitalProductData.TimeBaseDivisor : 4000);
330
331  /* clear hostbridge errors but leave MCP disabled -
332   * PCI config space scanning code will trip otherwise :-(
333   */
334  _BSP_clear_hostbridge_errors(0 /* enableMCP */, 0/*quiet*/);
335
336  /* Allocate and set up the page table mappings
337   * This is only available on >604 CPUs.
338   *
339   * NOTE: This setup routine may modify the available memory
340   *       size. It is essential to call it before
341   *       calculating the workspace etc.
342   */
343  pt = BSP_pgtbl_setup(&BSP_mem_size);
344
345  if (!pt || TRIV121_MAP_SUCCESS != triv121PgTblMap(
346            pt, TRIV121_121_VSID, 0xfeff0000, 1,
347            TRIV121_ATTR_IO_PAGE, TRIV121_PP_RW_PAGE)) {
348        printk("WARNING: unable to setup page tables VME "
349               "bridge must share PCI space\n");
350  }
351
352  /*
353   *  initialize the device driver parameters
354   */
355  bsp_clicks_per_usec    = BSP_bus_frequency/(BSP_time_base_divisor * 1000);
356
357  /*
358   * Initalize RTEMS IRQ system
359   */
360  BSP_rtems_irq_mng_init(0);
361
362  /* Activate the page table mappings only after
363   * initializing interrupts because the irq_mng_init()
364   * routine needs to modify the text
365   */
366  if (pt) {
367#ifdef  SHOW_MORE_INIT_SETTINGS
368    printk("Page table setup finished; will activate it NOW...\n");
369#endif
370    BSP_pgtbl_activate(pt);
371    /* finally, switch off DBAT3 */
372    setdbat(3, 0, 0, 0, 0); 
373  }
374
375#if defined(DEBUG_BATS)
376  ShowBATS();
377#endif
378
379#ifdef SHOW_MORE_INIT_SETTINGS
380  printk("Exit from bspstart\n");
381#endif
382}
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