source: rtems/c/src/lib/libbsp/powerpc/shared/startup/bspstart.c @ b1e8a58

4.11
Last change on this file since b1e8a58 was b1e8a58, checked in by Sebastian Huber <sebastian.huber@…>, on Nov 14, 2012 at 8:57:55 AM

bsps/powerpc: Exception initialization error is fatal

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File size: 9.4 KB
Line 
1/*
2 *  This routine starts the application.  It includes application,
3 *  board, and monitor specific initialization and configuration.
4 *  The generic CPU dependent initialization has been performed
5 *  before this routine is invoked.
6 *
7 *  COPYRIGHT (c) 1989-2007.
8 *  On-Line Applications Research Corporation (OAR).
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.rtems.com/license/LICENSE.
13 *
14 *  Modified to support the MCP750.
15 *  Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
16 */
17
18#include <string.h>
19
20#include <bsp.h>
21#include <rtems/bspIo.h>
22#include <bsp/consoleIo.h>
23#include <libcpu/spr.h>
24#include <bsp/residual.h>
25#include <bsp/pci.h>
26#include <bsp/openpic.h>
27#include <bsp/irq.h>
28#include <libcpu/bat.h>
29#include <libcpu/pte121.h>
30#include <libcpu/cpuIdent.h>
31#include <bsp/vectors.h>
32#include <bsp/motorola.h>
33#include <rtems/powerpc/powerpc.h>
34
35extern void _return_to_ppcbug(void);
36extern unsigned long __rtems_end[];
37extern void L1_caches_enables(void);
38extern unsigned get_L2CR(void);
39extern void set_L2CR(unsigned);
40extern Triv121PgTbl BSP_pgtbl_setup(unsigned int *);
41extern void                     BSP_pgtbl_activate(Triv121PgTbl);
42
43SPR_RW(SPRG1)
44
45#if defined(DEBUG_BATS)
46extern void ShowBATS(void);
47#endif
48
49/*
50 *  Driver configuration parameters
51 */
52uint32_t   bsp_clicks_per_usec;
53
54/*
55 * Copy of residuals passed by firmware
56 */
57RESIDUAL residualCopy;
58/*
59 * Copy Additional boot param passed by boot loader
60 */
61#define MAX_LOADER_ADD_PARM 80
62char loaderParam[MAX_LOADER_ADD_PARM];
63
64char *BSP_commandline_string = loaderParam;
65/*
66 * Vital Board data Start using DATA RESIDUAL
67 */
68/*
69 * Total memory using RESIDUAL DATA
70 */
71unsigned int BSP_mem_size;
72
73/*
74 * PCI Bus Frequency
75 */
76unsigned int BSP_bus_frequency;
77/*
78 * processor clock frequency
79 */
80unsigned int BSP_processor_frequency;
81/*
82 * Time base divisior (how many tick for 1 second).
83 */
84unsigned int BSP_time_base_divisor;
85
86void BSP_panic(char *s)
87{
88  printk("%s PANIC %s\n",_RTEMS_version, s);
89  __asm__ __volatile ("sc");
90}
91
92void _BSP_Fatal_error(unsigned int v)
93{
94  printk("%s PANIC ERROR %x\n",_RTEMS_version, v);
95  __asm__ __volatile ("sc");
96}
97
98/*
99 *  Use the shared implementations of the following routines
100 */
101
102char * save_boot_params(
103  RESIDUAL *r3,
104  void     *r4,
105  void     *r5,
106  char     *additional_boot_options
107)
108{
109
110  residualCopy = *r3;
111  strncpy(loaderParam, additional_boot_options, MAX_LOADER_ADD_PARM);
112  loaderParam[MAX_LOADER_ADD_PARM - 1] ='\0';
113  return loaderParam;
114}
115
116#if defined(mvme2100)
117unsigned int EUMBBAR;
118
119/*
120 * Return the current value of the Embedded Utilities Memory Block Base Address
121 * Register (EUMBBAR) as read from the processor configuration register using
122 * Processor Address Map B (CHRP).
123 */
124unsigned int get_eumbbar(void) {
125  out_le32( (volatile unsigned *)0xfec00000, 0x80000078 );
126  return in_le32( (volatile unsigned *)0xfee00000 );
127}
128#endif
129
130/*
131 *  bsp_start
132 *
133 *  This routine does the bulk of the system initialization.
134 */
135
136void bsp_start( void )
137{
138#if !defined(mvme2100)
139  unsigned l2cr;
140#endif
141  uintptr_t intrStackStart;
142  uintptr_t intrStackSize;
143/*  ppc_cpu_id_t myCpu; */
144/*  ppc_cpu_revision_t myCpuRevision; */
145  prep_t boardManufacturer;
146  motorolaBoard myBoard;
147  Triv121PgTbl  pt=0;
148
149  /*
150   * Get CPU identification dynamically. Note that the get_ppc_cpu_type()
151   * function store the result in global variables so that it can be used
152   * later...
153   */
154  /* myCpu      = */ get_ppc_cpu_type();
155  /* myCpuRevision = */ get_ppc_cpu_revision();
156
157  /*
158   * Init MMU block address translation to enable hardware access
159   */
160
161#if !defined(mvme2100)
162  /*
163   * PC legacy IO space used for inb/outb and all PC compatible hardware
164   */
165  setdbat(1, _IO_BASE, _IO_BASE, 0x10000000, IO_PAGE);
166#endif
167
168  /*
169   * PCI devices memory area. Needed to access OpenPIC features
170   * provided by the Raven
171   *
172   * T. Straumann: give more PCI address space
173   */
174  setdbat(2, PCI_MEM_BASE+PCI_MEM_WIN0, PCI_MEM_BASE+PCI_MEM_WIN0, 0x10000000, IO_PAGE);
175
176  /*
177   * Must have acces to open pic PCI ACK registers provided by the RAVEN
178   */
179#ifndef qemu
180  setdbat(3, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE);
181#else
182  setdbat(3, 0xb0000000, 0xb0000000, 0x10000000, IO_PAGE);
183#endif
184
185#if defined(mvme2100)
186  /* Need 0xfec00000 mapped for this */
187  EUMBBAR = get_eumbbar();
188#endif
189
190  /*
191   * enables L1 Cache. Note that the L1_caches_enables() codes checks for
192   * relevant CPU type so that the reason why there is no use of myCpu...
193   */
194  L1_caches_enables();
195
196  select_console(CONSOLE_LOG);
197
198  /*
199   * We check that the keyboard is present and immediately
200   * select the serial console if not.
201   */
202#if defined(BSP_KBD_IOBASE)
203  { int err;
204    err = kbdreset();
205    if (err) select_console(CONSOLE_SERIAL);
206  }
207#else
208  select_console(CONSOLE_SERIAL);
209#endif
210
211
212#if !defined(mvme2100)
213  /*
214   * Enable L2 Cache. Note that the set_L2CR(L2CR) codes checks for
215   * relevant CPU type (mpc750)...
216   */
217  l2cr = get_L2CR();
218#ifdef SHOW_LCR2_REGISTER
219  printk("Initial L2CR value = %x\n", l2cr);
220#endif
221  if ( (! (l2cr & 0x80000000)) && ((int) l2cr == -1))
222    set_L2CR(0xb9A14000);
223#endif
224
225  /*
226   * Initialize the interrupt related settings.
227   */
228  intrStackStart = (uintptr_t) __rtems_end;
229  intrStackSize = rtems_configuration_get_interrupt_stack_size();
230
231  /*
232   * Initialize default raw exception handlers.
233   */
234  ppc_exc_initialize(
235    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
236    intrStackStart,
237    intrStackSize
238  );
239
240  boardManufacturer   =  checkPrepBoardType(&residualCopy);
241  if (boardManufacturer != PREP_Motorola) {
242    printk("Unsupported hardware vendor\n");
243    while (1);
244  }
245  myBoard = getMotorolaBoard();
246
247  printk("-----------------------------------------\n");
248  printk("Welcome to %s on %s\n", _RTEMS_version,
249                                    motorolaBoardToString(myBoard));
250  printk("-----------------------------------------\n");
251#ifdef SHOW_MORE_INIT_SETTINGS
252  printk("Residuals are located at %x\n", (unsigned) &residualCopy);
253  printk("Additionnal boot options are %s\n", loaderParam);
254  printk("Software IRQ stack starts at %x with size %u\n", intrStackStart, intrStackSize);
255  printk("-----------------------------------------\n");
256#endif
257
258#ifdef TEST_RETURN_TO_PPCBUG
259  printk("Hit <Enter> to return to PPCBUG monitor\n");
260  printk("When Finished hit GO. It should print <Back from monitor>\n");
261  debug_getc();
262  _return_to_ppcbug();
263  printk("Back from monitor\n");
264  _return_to_ppcbug();
265#endif /* TEST_RETURN_TO_PPCBUG  */
266
267#ifdef SHOW_MORE_INIT_SETTINGS
268  printk("Going to start PCI buses scanning and initialization\n");
269#endif
270
271  pci_initialize();
272  {
273    const struct _int_map *bspmap  = motorolaIntMap(currentBoard);
274    if( bspmap ) {
275       printk("pci : Configuring interrupt routing for '%s'\n",
276          motorolaBoardToString(currentBoard));
277       FixupPCI(bspmap, motorolaIntSwizzle(currentBoard));
278    }
279    else
280       printk("pci : Interrupt routing not available for this bsp\n");
281 }
282
283#ifdef SHOW_MORE_INIT_SETTINGS
284  printk("Number of PCI buses found is : %d\n", pci_bus_count());
285#endif
286#ifdef TEST_RAW_EXCEPTION_CODE
287  printk("Testing exception handling Part 1\n");
288  /*
289   * Cause a software exception
290   */
291  __asm__ __volatile ("sc");
292  /*
293   * Check we can still catch exceptions and return coorectly.
294   */
295  printk("Testing exception handling Part 2\n");
296  __asm__ __volatile ("sc");
297
298  /*
299   * Somehow doing the above seems to clobber SPRG0 on the mvme2100.  The
300   * interrupt disable mask is stored in SPRG0. Is this a problem?
301   */
302  ppc_interrupt_set_disable_mask( PPC_INTERRUPT_DISABLE_MASK_DEFAULT);
303
304#endif
305
306/* See above */
307
308  BSP_mem_size            = residualCopy.TotalMemory;
309  BSP_bus_frequency       = residualCopy.VitalProductData.ProcessorBusHz;
310  BSP_processor_frequency = residualCopy.VitalProductData.ProcessorHz;
311  BSP_time_base_divisor   = (residualCopy.VitalProductData.TimeBaseDivisor?
312                    residualCopy.VitalProductData.TimeBaseDivisor : 4000);
313
314  /* clear hostbridge errors but leave MCP disabled -
315   * PCI config space scanning code will trip otherwise :-(
316   */
317  _BSP_clear_hostbridge_errors(0 /* enableMCP */, 0/*quiet*/);
318
319  /* Allocate and set up the page table mappings
320   * This is only available on >604 CPUs.
321   *
322   * NOTE: This setup routine may modify the available memory
323   *       size. It is essential to call it before
324   *       calculating the workspace etc.
325   */
326  pt = BSP_pgtbl_setup(&BSP_mem_size);
327
328  if (!pt || TRIV121_MAP_SUCCESS != triv121PgTblMap(
329            pt, TRIV121_121_VSID,
330#ifndef qemu
331            0xfeff0000,
332#else
333            0xbffff000,
334#endif
335            1,
336            TRIV121_ATTR_IO_PAGE, TRIV121_PP_RW_PAGE)) {
337        printk("WARNING: unable to setup page tables VME "
338               "bridge must share PCI space\n");
339  }
340
341  /*
342   *  initialize the device driver parameters
343   */
344  bsp_clicks_per_usec    = BSP_bus_frequency/(BSP_time_base_divisor * 1000);
345
346  /*
347   * Initalize RTEMS IRQ system
348   */
349  BSP_rtems_irq_mng_init(0);
350
351  /* Activate the page table mappings only after
352   * initializing interrupts because the irq_mng_init()
353   * routine needs to modify the text
354   */
355  if (pt) {
356#ifdef  SHOW_MORE_INIT_SETTINGS
357    printk("Page table setup finished; will activate it NOW...\n");
358#endif
359    BSP_pgtbl_activate(pt);
360    /* finally, switch off DBAT3 */
361    setdbat(3, 0, 0, 0, 0);
362  }
363
364#if defined(DEBUG_BATS)
365  ShowBATS();
366#endif
367
368#ifdef SHOW_MORE_INIT_SETTINGS
369  printk("Exit from bspstart\n");
370#endif
371}
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