1 | /* |
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2 | * This routine starts the application. It includes application, |
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3 | * board, and monitor specific initialization and configuration. |
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4 | * The generic CPU dependent initialization has been performed |
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5 | * before this routine is invoked. |
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6 | * |
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7 | * COPYRIGHT (c) 1989-1998. |
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8 | * On-Line Applications Research Corporation (OAR). |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.com/license/LICENSE. |
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13 | * |
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14 | * Modified to support the MCP750. |
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15 | * Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr |
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16 | * |
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17 | * $Id$ |
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18 | */ |
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19 | |
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20 | #include <string.h> |
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21 | |
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22 | #include <bsp.h> |
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23 | #include <rtems/libio.h> |
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24 | #include <rtems/libcsupport.h> |
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25 | #include <bsp/consoleIo.h> |
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26 | #include <libcpu/spr.h> |
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27 | #include <bsp/residual.h> |
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28 | #include <bsp/pci.h> |
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29 | #include <bsp/openpic.h> |
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30 | #include <bsp/irq.h> |
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31 | #include <bsp/VME.h> |
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32 | #include <libcpu/bat.h> |
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33 | #include <libcpu/pte121.h> |
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34 | #include <libcpu/cpuIdent.h> |
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35 | #include <bsp/vectors.h> |
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36 | #include <bsp/motorola.h> |
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37 | |
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38 | extern void _return_to_ppcbug(); |
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39 | extern unsigned long __rtems_end[]; |
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40 | extern void L1_caches_enables(); |
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41 | extern unsigned get_L2CR(); |
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42 | extern void set_L2CR(unsigned); |
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43 | extern void bsp_cleanup(void); |
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44 | extern Triv121PgTbl BSP_pgtbl_setup(); |
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45 | extern void BSP_pgtbl_activate(); |
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46 | extern void BSP_vme_config(); |
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47 | |
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48 | SPR_RW(SPRG0) |
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49 | SPR_RW(SPRG1) |
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50 | |
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51 | #if defined(DEBUG_BATS) |
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52 | void printBAT( int bat, unsigned32 upper, unsigned32 lower ) |
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53 | { |
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54 | unsigned32 lowest_addr; |
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55 | unsigned32 size; |
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56 | |
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57 | printk("BAT%d raw(upper=0x%08x, lower=0x%08x) ", bat, upper, lower ); |
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58 | |
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59 | lowest_addr = (upper & 0xFFFE0000); |
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60 | size = (((upper & 0x00001FFC) >> 2) + 1) * (128 * 1024); |
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61 | printk(" range(0x%08x, 0x%08x) %s%s %s%s%s%s %s\n", |
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62 | lowest_addr, |
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63 | lowest_addr + (size - 1), |
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64 | (upper & 0x01) ? "P" : "p", |
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65 | (upper & 0x02) ? "S" : "s", |
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66 | (lower & 0x08) ? "G" : "g", |
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67 | (lower & 0x10) ? "M" : "m", |
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68 | (lower & 0x20) ? "I" : "i", |
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69 | (lower & 0x40) ? "W" : "w", |
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70 | (lower & 0x01) ? "Read Only" : |
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71 | ((lower & 0x02) ? "Read/Write" : "No Access") |
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72 | ); |
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73 | } |
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74 | |
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75 | void ShowBATS(){ |
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76 | unsigned32 lower; |
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77 | unsigned32 upper; |
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78 | |
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79 | __MFSPR(536, upper); __MFSPR(537, lower); printBAT( 0, upper, lower ); |
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80 | __MFSPR(538, upper); __MFSPR(539, lower); printBAT( 1, upper, lower ); |
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81 | __MFSPR(540, upper); __MFSPR(541, lower); printBAT( 2, upper, lower ); |
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82 | __MFSPR(542, upper); __MFSPR(543, lower); printBAT( 3, upper, lower ); |
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83 | } |
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84 | #endif |
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85 | |
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86 | /* |
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87 | * Copy of residuals passed by firmware |
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88 | */ |
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89 | RESIDUAL residualCopy; |
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90 | /* |
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91 | * Copy Additional boot param passed by boot loader |
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92 | */ |
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93 | #define MAX_LOADER_ADD_PARM 80 |
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94 | char loaderParam[MAX_LOADER_ADD_PARM]; |
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95 | /* |
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96 | * Vital Board data Start using DATA RESIDUAL |
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97 | */ |
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98 | /* |
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99 | * Total memory using RESIDUAL DATA |
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100 | */ |
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101 | unsigned int BSP_mem_size; |
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102 | /* |
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103 | * PCI Bus Frequency |
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104 | */ |
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105 | unsigned int BSP_bus_frequency; |
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106 | /* |
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107 | * processor clock frequency |
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108 | */ |
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109 | unsigned int BSP_processor_frequency; |
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110 | /* |
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111 | * Time base divisior (how many tick for 1 second). |
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112 | */ |
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113 | unsigned int BSP_time_base_divisor; |
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114 | /* |
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115 | * system init stack and soft ir stack size |
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116 | */ |
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117 | #define INIT_STACK_SIZE 0x1000 |
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118 | #define INTR_STACK_SIZE CONFIGURE_INTERRUPT_STACK_MEMORY |
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119 | |
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120 | void BSP_panic(char *s) |
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121 | { |
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122 | printk("%s PANIC %s\n",_RTEMS_version, s); |
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123 | __asm__ __volatile ("sc"); |
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124 | } |
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125 | |
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126 | void _BSP_Fatal_error(unsigned int v) |
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127 | { |
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128 | printk("%s PANIC ERROR %x\n",_RTEMS_version, v); |
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129 | __asm__ __volatile ("sc"); |
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130 | } |
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131 | |
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132 | /* |
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133 | * The original table from the application and our copy of it with |
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134 | * some changes. |
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135 | */ |
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136 | |
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137 | extern rtems_configuration_table Configuration; |
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138 | |
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139 | rtems_configuration_table BSP_Configuration; |
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140 | |
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141 | rtems_cpu_table Cpu_table; |
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142 | |
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143 | char *rtems_progname; |
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144 | |
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145 | /* |
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146 | * Use the shared implementations of the following routines |
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147 | */ |
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148 | |
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149 | void bsp_postdriver_hook(void); |
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150 | void bsp_libc_init( void *, uint32_t, int ); |
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151 | |
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152 | /* |
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153 | * Function: bsp_pretasking_hook |
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154 | * Created: 95/03/10 |
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155 | * |
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156 | * Description: |
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157 | * BSP pretasking hook. Called just before drivers are initialized. |
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158 | * Used to setup libc and install any BSP extensions. |
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159 | * |
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160 | * NOTES: |
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161 | * Must not use libc (to do io) from here, since drivers are |
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162 | * not yet initialized. |
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163 | * |
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164 | */ |
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165 | |
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166 | void bsp_pretasking_hook(void) |
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167 | { |
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168 | rtems_unsigned32 heap_start; |
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169 | rtems_unsigned32 heap_size; |
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170 | rtems_unsigned32 heap_sbrk_spared; |
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171 | extern rtems_unsigned32 _bsp_sbrk_init(rtems_unsigned32, rtems_unsigned32*); |
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172 | |
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173 | heap_start = ((rtems_unsigned32) __rtems_end) + |
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174 | INIT_STACK_SIZE + INTR_STACK_SIZE; |
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175 | if (heap_start & (CPU_ALIGNMENT-1)) |
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176 | heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1); |
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177 | |
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178 | heap_size = (BSP_mem_size - heap_start) - BSP_Configuration.work_space_size; |
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179 | heap_sbrk_spared=_bsp_sbrk_init(heap_start, &heap_size); |
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180 | |
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181 | #ifdef SHOW_MORE_INIT_SETTINGS |
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182 | printk( "HEAP start %x size %x (%x bytes spared for sbrk)\n", |
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183 | heap_start, heap_size, heap_sbrk_spared); |
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184 | #endif |
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185 | |
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186 | bsp_libc_init((void *) 0, heap_size, heap_sbrk_spared); |
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187 | |
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188 | #ifdef RTEMS_DEBUG |
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189 | rtems_debug_enable( RTEMS_DEBUG_ALL_MASK ); |
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190 | #endif |
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191 | } |
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192 | |
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193 | void zero_bss() |
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194 | { |
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195 | /* prevent these from being accessed in the short data areas */ |
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196 | extern unsigned long __bss_start[], __SBSS_START__[], __SBSS_END__[]; |
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197 | extern unsigned long __SBSS2_START__[], __SBSS2_END__[]; |
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198 | memset(__SBSS_START__, 0, ((unsigned) __SBSS_END__) - ((unsigned)__SBSS_START__)); |
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199 | memset(__SBSS2_START__, 0, ((unsigned) __SBSS2_END__) - ((unsigned)__SBSS2_START__)); |
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200 | memset(__bss_start, 0, ((unsigned) __rtems_end) - ((unsigned)__bss_start)); |
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201 | } |
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202 | |
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203 | void save_boot_params(RESIDUAL* r3, void *r4, void* r5, char *additional_boot_options) |
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204 | { |
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205 | |
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206 | residualCopy = *r3; |
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207 | strncpy(loaderParam, additional_boot_options, MAX_LOADER_ADD_PARM); |
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208 | loaderParam[MAX_LOADER_ADD_PARM - 1] ='\0'; |
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209 | } |
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210 | |
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211 | #if defined(mpc8240) || defined(mpc8245) |
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212 | unsigned int EUMBBAR; |
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213 | |
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214 | /* |
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215 | * Return the current value of the Embedded Utilities Memory Block Base Address |
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216 | * Register (EUMBBAR) as read from the processor configuration register using |
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217 | * Processor Address Map B (CHRP). |
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218 | */ |
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219 | unsigned int get_eumbbar() { |
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220 | register int a, e; |
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221 | |
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222 | asm volatile( "lis %0,0xfec0; ori %0,%0,0x0000": "=r" (a) ); |
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223 | asm volatile("sync"); |
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224 | |
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225 | asm volatile("lis %0,0x8000; ori %0,%0,0x0078": "=r"(e) ); |
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226 | asm volatile("stwbrx %0,0x0,%1": "=r"(e): "r"(a)); |
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227 | asm volatile("sync"); |
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228 | |
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229 | asm volatile("lis %0,0xfee0; ori %0,%0,0x0000": "=r" (a) ); |
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230 | asm volatile("sync"); |
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231 | |
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232 | asm volatile("lwbrx %0,0x0,%1": "=r" (e): "r" (a)); |
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233 | asm volatile("isync"); |
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234 | return e; |
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235 | } |
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236 | #endif |
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237 | |
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238 | /* |
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239 | * bsp_start |
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240 | * |
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241 | * This routine does the bulk of the system initialization. |
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242 | */ |
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243 | |
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244 | void bsp_start( void ) |
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245 | { |
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246 | unsigned char *stack; |
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247 | #if !defined(mpc8240) && !defined(mpc8245) |
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248 | unsigned l2cr; |
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249 | #endif |
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250 | register uint32_t intrStack; |
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251 | register uint32_t *intrStackPtr; |
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252 | unsigned char *work_space_start; |
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253 | ppc_cpu_id_t myCpu; |
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254 | ppc_cpu_revision_t myCpuRevision; |
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255 | prep_t boardManufacturer; |
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256 | motorolaBoard myBoard; |
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257 | Triv121PgTbl pt=0; |
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258 | |
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259 | /* |
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260 | * Get CPU identification dynamically. Note that the get_ppc_cpu_type() |
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261 | * function store the result in global variables so that it can be used |
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262 | * later... |
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263 | */ |
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264 | myCpu = get_ppc_cpu_type(); |
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265 | myCpuRevision = get_ppc_cpu_revision(); |
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266 | |
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267 | #if defined(mvme2100) |
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268 | EUMBBAR = get_eumbbar(); |
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269 | |
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270 | Cpu_table.exceptions_in_RAM = TRUE; |
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271 | { unsigned v = 0x3000 ; _CPU_MSR_SET(v); } |
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272 | #endif |
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273 | |
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274 | #if !defined(mpc8240) && !defined(mpc8245) |
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275 | /* |
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276 | * enables L1 Cache. Note that the L1_caches_enables() codes checks for |
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277 | * relevant CPU type so that the reason why there is no use of myCpu... |
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278 | */ |
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279 | L1_caches_enables(); |
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280 | |
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281 | /* |
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282 | * Enable L2 Cache. Note that the set_L2CR(L2CR) codes checks for |
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283 | * relevant CPU type (mpc750)... |
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284 | */ |
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285 | l2cr = get_L2CR(); |
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286 | #ifdef SHOW_LCR2_REGISTER |
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287 | printk("Initial L2CR value = %x\n", l2cr); |
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288 | #endif |
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289 | if ( (! (l2cr & 0x80000000)) && ((int) l2cr == -1)) |
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290 | set_L2CR(0xb9A14000); |
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291 | #endif |
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292 | |
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293 | /* |
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294 | * the initial stack has aready been set to this value in start.S |
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295 | * so there is no need to set it in r1 again... It is just for info |
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296 | * so that It can be printed without accessing R1. |
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297 | */ |
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298 | stack = ((unsigned char*) __rtems_end) + |
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299 | INIT_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE; |
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300 | |
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301 | /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */ |
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302 | *((uint32_t*)stack) = 0; |
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303 | |
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304 | /* |
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305 | * Initialize the interrupt related settings |
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306 | * SPRG1 = software managed IRQ stack |
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307 | * |
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308 | * This could be done later (e.g in IRQ_INIT) but it helps to understand |
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309 | * some settings below... |
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310 | */ |
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311 | intrStack = ((uint32_t) __rtems_end) + |
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312 | INIT_STACK_SIZE + INTR_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE; |
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313 | |
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314 | /* make sure it's properly aligned */ |
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315 | intrStack &= ~(CPU_STACK_ALIGNMENT-1); |
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316 | |
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317 | /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */ |
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318 | intrStackPtr = (uint32_t*) intrStack; |
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319 | *intrStackPtr = 0; |
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320 | |
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321 | _write_SPRG1(intrStack); |
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322 | |
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323 | /* signal them that we have fixed PR288 - eventually, this should go away */ |
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324 | _write_SPRG0(PPC_BSP_HAS_FIXED_PR288); |
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325 | |
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326 | /* |
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327 | * Initialize default raw exception handlers. See vectors/vectors_init.c |
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328 | */ |
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329 | initialize_exceptions(); |
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330 | |
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331 | /* |
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332 | * Init MMU block address translation to enable hardware access |
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333 | */ |
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334 | |
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335 | #if !defined(mvme2100) |
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336 | /* |
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337 | * PC legacy IO space used for inb/outb and all PC compatible hardware |
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338 | */ |
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339 | setdbat(1, _IO_BASE, _IO_BASE, 0x10000000, IO_PAGE); |
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340 | #endif |
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341 | |
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342 | /* |
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343 | * PCI devices memory area. Needed to access OpenPIC features |
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344 | * provided by the Raven |
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345 | * |
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346 | * T. Straumann: give more PCI address space |
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347 | */ |
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348 | setdbat(2, PCI_MEM_BASE, PCI_MEM_BASE, 0x10000000, IO_PAGE); |
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349 | |
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350 | /* |
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351 | * Must have acces to open pic PCI ACK registers provided by the RAVEN |
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352 | */ |
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353 | setdbat(3, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE); |
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354 | |
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355 | select_console(CONSOLE_LOG); |
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356 | |
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357 | /* |
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358 | * We check that the keyboard is present and immediately |
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359 | * select the serial console if not. |
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360 | */ |
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361 | #if defined(BSP_KBD_IOBASE) |
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362 | { int err; |
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363 | err = kbdreset(); |
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364 | if (err) select_console(CONSOLE_SERIAL); |
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365 | } |
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366 | #else |
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367 | select_console(CONSOLE_SERIAL); |
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368 | #endif |
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369 | |
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370 | boardManufacturer = checkPrepBoardType(&residualCopy); |
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371 | if (boardManufacturer != PREP_Motorola) { |
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372 | printk("Unsupported hardware vendor\n"); |
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373 | while (1); |
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374 | } |
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375 | myBoard = getMotorolaBoard(); |
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376 | |
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377 | printk("-----------------------------------------\n"); |
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378 | printk("Welcome to %s on %s\n", _RTEMS_version, |
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379 | motorolaBoardToString(myBoard)); |
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380 | printk("-----------------------------------------\n"); |
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381 | #ifdef SHOW_MORE_INIT_SETTINGS |
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382 | printk("Residuals are located at %x\n", (unsigned) &residualCopy); |
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383 | printk("Additionnal boot options are %s\n", loaderParam); |
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384 | printk("Initial system stack at %x\n",stack); |
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385 | printk("Software IRQ stack at %x\n",intrStack); |
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386 | printk("-----------------------------------------\n"); |
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387 | #endif |
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388 | |
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389 | #ifdef TEST_RETURN_TO_PPCBUG |
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390 | printk("Hit <Enter> to return to PPCBUG monitor\n"); |
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391 | printk("When Finished hit GO. It should print <Back from monitor>\n"); |
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392 | debug_getc(); |
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393 | _return_to_ppcbug(); |
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394 | printk("Back from monitor\n"); |
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395 | _return_to_ppcbug(); |
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396 | #endif /* TEST_RETURN_TO_PPCBUG */ |
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397 | |
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398 | #ifdef SHOW_MORE_INIT_SETTINGS |
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399 | printk("Going to start PCI buses scanning and initialization\n"); |
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400 | #endif |
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401 | InitializePCI(); |
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402 | |
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403 | { |
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404 | const struct _int_map *bspmap = motorolaIntMap(currentBoard); |
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405 | if( bspmap ) { |
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406 | printk("pci : Configuring interrupt routing for '%s'\n", |
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407 | motorolaBoardToString(currentBoard)); |
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408 | FixupPCI(bspmap, motorolaIntSwizzle(currentBoard)); |
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409 | } |
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410 | else |
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411 | printk("pci : Interrupt routing not available for this bsp\n"); |
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412 | } |
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413 | |
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414 | #ifdef SHOW_MORE_INIT_SETTINGS |
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415 | printk("Number of PCI buses found is : %d\n", BusCountPCI()); |
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416 | #endif |
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417 | #ifdef TEST_RAW_EXCEPTION_CODE |
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418 | printk("Testing exception handling Part 1\n"); |
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419 | /* |
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420 | * Cause a software exception |
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421 | */ |
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422 | __asm__ __volatile ("sc"); |
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423 | /* |
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424 | * Check we can still catch exceptions and return coorectly. |
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425 | */ |
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426 | printk("Testing exception handling Part 2\n"); |
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427 | __asm__ __volatile ("sc"); |
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428 | |
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429 | /* |
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430 | * Somehow doing the above seems to clobber SPRG0 on the mvme2100. It |
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431 | * is probably a not so subtle hint that you do not want to use PPCBug |
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432 | * once RTEMS is up and running. Anyway, we still needs to indicate |
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433 | * that we have fixed PR288. Eventually, this should go away. |
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434 | */ |
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435 | _write_SPRG0(PPC_BSP_HAS_FIXED_PR288); |
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436 | #endif |
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437 | |
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438 | BSP_mem_size = residualCopy.TotalMemory; |
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439 | BSP_bus_frequency = residualCopy.VitalProductData.ProcessorBusHz; |
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440 | BSP_processor_frequency = residualCopy.VitalProductData.ProcessorHz; |
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441 | BSP_time_base_divisor = (residualCopy.VitalProductData.TimeBaseDivisor? |
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442 | residualCopy.VitalProductData.TimeBaseDivisor : 4000); |
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443 | |
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444 | /* clear hostbridge errors but leave MCP disabled - |
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445 | * PCI config space scanning code will trip otherwise :-( |
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446 | */ |
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447 | _BSP_clear_hostbridge_errors(0 /* enableMCP */, 0/*quiet*/); |
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448 | |
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449 | /* Allocate and set up the page table mappings |
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450 | * This is only available on >604 CPUs. |
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451 | * |
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452 | * NOTE: This setup routine may modify the available memory |
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453 | * size. It is essential to call it before |
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454 | * calculating the workspace etc. |
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455 | */ |
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456 | pt = BSP_pgtbl_setup(&BSP_mem_size); |
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457 | |
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458 | if (!pt || TRIV121_MAP_SUCCESS != triv121PgTblMap( |
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459 | pt, TRIV121_121_VSID, 0xfeff0000, 1, |
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460 | TRIV121_ATTR_IO_PAGE, TRIV121_PP_RW_PAGE)) { |
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461 | printk("WARNING: unable to setup page tables VME " |
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462 | "bridge must share PCI space\n"); |
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463 | } |
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464 | |
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465 | /* |
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466 | * Set up our hooks |
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467 | * Make sure libc_init is done before drivers initialized so that |
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468 | * they can use atexit() |
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469 | */ |
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470 | |
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471 | Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */ |
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472 | Cpu_table.postdriver_hook = bsp_postdriver_hook; |
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473 | Cpu_table.do_zero_of_workspace = TRUE; |
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474 | Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY; |
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475 | Cpu_table.clicks_per_usec = BSP_processor_frequency/(BSP_time_base_divisor * 1000); |
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476 | Cpu_table.exceptions_in_RAM = TRUE; |
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477 | |
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478 | #ifdef SHOW_MORE_INIT_SETTINGS |
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479 | printk("BSP_Configuration.work_space_size = %x\n", |
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480 | BSP_Configuration.work_space_size); |
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481 | #endif |
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482 | |
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483 | work_space_start = |
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484 | (unsigned char *)BSP_mem_size - BSP_Configuration.work_space_size; |
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485 | |
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486 | if ( work_space_start <= |
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487 | ((unsigned char *)__rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE) { |
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488 | printk( "bspstart: Not enough RAM!!!\n" ); |
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489 | bsp_cleanup(); |
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490 | } |
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491 | |
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492 | BSP_Configuration.work_space_start = work_space_start; |
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493 | |
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494 | /* |
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495 | * Initalize RTEMS IRQ system |
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496 | */ |
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497 | BSP_rtems_irq_mng_init(0); |
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498 | |
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499 | /* Activate the page table mappings only after |
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500 | * initializing interrupts because the irq_mng_init() |
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501 | * routine needs to modify the text |
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502 | */ |
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503 | if (pt) { |
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504 | #ifdef SHOW_MORE_INIT_SETTINGS |
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505 | printk("Page table setup finished; will activate it NOW...\n"); |
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506 | #endif |
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507 | BSP_pgtbl_activate(pt); |
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508 | #if !defined(mvme2100) |
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509 | /* finally, switch off DBAT3 */ |
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510 | setdbat(3, 0, 0, 0, 0); |
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511 | #endif |
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512 | } |
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513 | |
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514 | /* |
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515 | * Initialize VME bridge - needs working PCI and IRQ subsystems... |
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516 | */ |
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517 | #ifdef SHOW_MORE_INIT_SETTINGS |
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518 | printk("Going to initialize VME bridge\n"); |
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519 | #endif |
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520 | /* |
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521 | * VME initialization is in a separate file so apps which don't use VME or |
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522 | * want a different configuration may link against a customized routine. |
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523 | */ |
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524 | BSP_vme_config(); |
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525 | |
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526 | #if defined(DEBUG_BATS) |
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527 | ShowBATS(); |
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528 | #endif |
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529 | |
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530 | #ifdef SHOW_MORE_INIT_SETTINGS |
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531 | printk("Exit from bspstart\n"); |
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532 | #endif |
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533 | } |
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