source: rtems/c/src/lib/libbsp/powerpc/shared/startup/bspstart.c @ 5cf0656

Last change on this file since 5cf0656 was 5cf0656, checked in by Éric Tremblay <e.tremblay@…>, on Mar 20, 2018 at 1:14:39 PM

bsps/powerpc: Support more than 256MiB of RAM

Close #3322.

  • Property mode set to 100644
File size: 9.7 KB
Line 
1/*
2 *  This routine does the bulk of the system initialization.
3 */
4
5/*
6 *  COPYRIGHT (c) 1989-2007.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.rtems.org/license/LICENSE.
12 *
13 *  Modified to support the MCP750.
14 *  Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
15 */
16
17#include <string.h>
18
19#include <bsp.h>
20#include <bsp/bootcard.h>
21#include <rtems/bspIo.h>
22#include <rtems/counter.h>
23#include <bsp/consoleIo.h>
24#include <libcpu/spr.h>
25#include <bsp/residual.h>
26#include <bsp/pci.h>
27#include <bsp/openpic.h>
28#include <bsp/irq.h>
29#include <libcpu/bat.h>
30#include <libcpu/pte121.h>
31#include <libcpu/cpuIdent.h>
32#include <bsp/vectors.h>
33#include <bsp/motorola.h>
34#include <rtems/powerpc/powerpc.h>
35
36extern void _return_to_ppcbug(void);
37extern unsigned long __rtems_end[];
38extern void L1_caches_enables(void);
39extern unsigned get_L2CR(void);
40extern void set_L2CR(unsigned);
41extern Triv121PgTbl BSP_pgtbl_setup(unsigned int *);
42extern void                     BSP_pgtbl_activate(Triv121PgTbl);
43
44SPR_RW(SPRG1)
45
46#if defined(DEBUG_BATS)
47extern void ShowBATS(void);
48#endif
49
50/*
51 *  Driver configuration parameters
52 */
53uint32_t   bsp_clicks_per_usec;
54
55/*
56 * Copy of residuals passed by firmware
57 */
58RESIDUAL residualCopy;
59/*
60 * Copy Additional boot param passed by boot loader
61 */
62#define MAX_LOADER_ADD_PARM 80
63char loaderParam[MAX_LOADER_ADD_PARM];
64
65char *BSP_commandline_string = loaderParam;
66/*
67 * Vital Board data Start using DATA RESIDUAL
68 */
69/*
70 * Total memory using RESIDUAL DATA
71 */
72unsigned int BSP_mem_size;
73
74/*
75 * PCI Bus Frequency
76 */
77unsigned int BSP_bus_frequency;
78/*
79 * processor clock frequency
80 */
81unsigned int BSP_processor_frequency;
82/*
83 * Time base divisior (how many tick for 1 second).
84 */
85unsigned int BSP_time_base_divisor;
86
87/*
88 *  Use the shared implementations of the following routines
89 */
90
91char *save_boot_params(
92  void *r3,
93  void *r4,
94  void *r5,
95  char *cmdline_start,
96  char *cmdline_end
97)
98{
99
100  residualCopy = *(RESIDUAL *)r3;
101  strncpy(loaderParam, cmdline_start, MAX_LOADER_ADD_PARM);
102  loaderParam[MAX_LOADER_ADD_PARM - 1] ='\0';
103  return loaderParam;
104}
105
106#if defined(mvme2100)
107unsigned int EUMBBAR;
108
109/*
110 * Return the current value of the Embedded Utilities Memory Block Base Address
111 * Register (EUMBBAR) as read from the processor configuration register using
112 * Processor Address Map B (CHRP).
113 */
114static unsigned int get_eumbbar(void) {
115  out_le32( (volatile uint32_t *)0xfec00000, 0x80000078 );
116  return in_le32( (volatile uint32_t *)0xfee00000 );
117}
118#endif
119
120/*
121 *  bsp_start
122 *
123 *  This routine does the bulk of the system initialization.
124 */
125
126void bsp_start( void )
127{
128#if !defined(mvme2100)
129  unsigned l2cr;
130#endif
131  uintptr_t intrStackStart;
132  uintptr_t intrStackSize;
133  prep_t boardManufacturer;
134  motorolaBoard myBoard;
135  Triv121PgTbl  pt=0;
136
137  /*
138   * Get CPU identification dynamically. Note that the get_ppc_cpu_type()
139   * function store the result in global variables so that it can be used
140   * later...
141   */
142  get_ppc_cpu_type();
143  get_ppc_cpu_revision();
144
145  /*
146   * Init MMU block address translation to enable hardware access
147   */
148
149#if !defined(mvme2100)
150  /*
151   * PC legacy IO space used for inb/outb and all PC compatible hardware
152   */
153  setdbat(1, _IO_BASE, _IO_BASE, 0x10000000, IO_PAGE);
154#endif
155
156  /*
157   * PCI devices memory area. Needed to access OpenPIC features
158   * provided by the Raven
159   *
160   * T. Straumann: give more PCI address space
161   */
162  setdbat(2, PCI_MEM_BASE+PCI_MEM_WIN0, PCI_MEM_BASE+PCI_MEM_WIN0, 0x10000000, IO_PAGE);
163
164  /*
165   * Must have acces to open pic PCI ACK registers provided by the RAVEN
166   */
167#ifndef qemu
168  setdbat(3, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE);
169#else
170  setdbat(3, 0xb0000000, 0xb0000000, 0x10000000, IO_PAGE);
171#endif
172
173#if defined(mvme2100)
174  /* Need 0xfec00000 mapped for this */
175  EUMBBAR = get_eumbbar();
176#endif
177
178  /*
179   * enables L1 Cache. Note that the L1_caches_enables() codes checks for
180   * relevant CPU type so that the reason why there is no use of myCpu...
181   */
182  L1_caches_enables();
183
184  select_console(CONSOLE_LOG);
185
186  /*
187   * We check that the keyboard is present and immediately
188   * select the serial console if not.
189   */
190#if defined(BSP_KBD_IOBASE)
191  { int err;
192    err = kbdreset();
193    if (err) select_console(CONSOLE_SERIAL);
194  }
195#else
196  select_console(CONSOLE_SERIAL);
197#endif
198
199
200#if !defined(mvme2100)
201  /*
202   * Enable L2 Cache. Note that the set_L2CR(L2CR) codes checks for
203   * relevant CPU type (mpc750)...
204   */
205  l2cr = get_L2CR();
206#ifdef SHOW_LCR2_REGISTER
207  printk("Initial L2CR value = %x\n", l2cr);
208#endif
209  if ( (! (l2cr & 0x80000000)) && ((int) l2cr == -1))
210    set_L2CR(0xb9A14000);
211#endif
212
213  /*
214   * Initialize the interrupt related settings.
215   */
216  intrStackStart = (uintptr_t) __rtems_end;
217  intrStackSize = rtems_configuration_get_interrupt_stack_size();
218
219  /*
220   * Initialize default raw exception handlers.
221   */
222  ppc_exc_initialize(intrStackStart, intrStackSize);
223
224  boardManufacturer   =  checkPrepBoardType(&residualCopy);
225  if (boardManufacturer != PREP_Motorola) {
226    printk("Unsupported hardware vendor\n");
227    while (1);
228  }
229  myBoard = getMotorolaBoard();
230
231  printk("-----------------------------------------\n");
232  printk("Welcome to %s on %s\n", _RTEMS_version,
233                                    motorolaBoardToString(myBoard));
234  printk("-----------------------------------------\n");
235#ifdef SHOW_MORE_INIT_SETTINGS
236  printk("Residuals are located at %x\n", (unsigned) &residualCopy);
237  printk("Additionnal boot options are %s\n", loaderParam);
238  printk("Software IRQ stack starts at %x with size %u\n", intrStackStart, intrStackSize);
239  printk("-----------------------------------------\n");
240#endif
241
242#ifdef TEST_RETURN_TO_PPCBUG
243  printk("Hit <Enter> to return to PPCBUG monitor\n");
244  printk("When Finished hit GO. It should print <Back from monitor>\n");
245  debug_getc();
246  _return_to_ppcbug();
247  printk("Back from monitor\n");
248  _return_to_ppcbug();
249#endif /* TEST_RETURN_TO_PPCBUG  */
250
251#ifdef SHOW_MORE_INIT_SETTINGS
252  printk("Going to start PCI buses scanning and initialization\n");
253#endif
254
255  pci_initialize();
256  {
257    const struct _int_map *bspmap  = motorolaIntMap(currentBoard);
258    if( bspmap ) {
259       printk("pci : Configuring interrupt routing for '%s'\n",
260          motorolaBoardToString(currentBoard));
261       FixupPCI(bspmap, motorolaIntSwizzle(currentBoard));
262    }
263    else
264       printk("pci : Interrupt routing not available for this bsp\n");
265 }
266
267#ifdef SHOW_MORE_INIT_SETTINGS
268  printk("Number of PCI buses found is : %d\n", pci_bus_count());
269#endif
270#ifdef TEST_RAW_EXCEPTION_CODE
271  printk("Testing exception handling Part 1\n");
272  /*
273   * Cause a software exception
274   */
275  __asm__ __volatile ("sc");
276  /*
277   * Check we can still catch exceptions and return coorectly.
278   */
279  printk("Testing exception handling Part 2\n");
280  __asm__ __volatile ("sc");
281
282  /*
283   * Somehow doing the above seems to clobber SPRG0 on the mvme2100.  The
284   * interrupt disable mask is stored in SPRG0. Is this a problem?
285   */
286  ppc_interrupt_set_disable_mask( PPC_INTERRUPT_DISABLE_MASK_DEFAULT);
287
288#endif
289
290/* See above */
291
292  BSP_mem_size            = residualCopy.TotalMemory;
293  BSP_bus_frequency       = residualCopy.VitalProductData.ProcessorBusHz;
294  BSP_processor_frequency = residualCopy.VitalProductData.ProcessorHz;
295  BSP_time_base_divisor   = (residualCopy.VitalProductData.TimeBaseDivisor?
296                    residualCopy.VitalProductData.TimeBaseDivisor : 4000);
297
298  /* clear hostbridge errors but leave MCP disabled -
299   * PCI config space scanning code will trip otherwise :-(
300   */
301  _BSP_clear_hostbridge_errors(0 /* enableMCP */, 0/*quiet*/);
302
303  if (BSP_mem_size > 0x10000000)
304  {
305    /* Support cases of system memory size larger than 256Mb.
306     *
307     * We use BAT3 in order to obtain access to the top section of the RAM.
308     * We also need to do this just before setting up the page table because
309     * this is where the page table will be located.
310     */
311    const unsigned int mem256Count = (BSP_mem_size / 0x10000000);
312    const unsigned int BAT3Addr    = ((BSP_mem_size % 0x10000000)  ?
313                                       (mem256Count     * 0x10000000) :
314                                      ((mem256Count-1) * 0x10000000));
315    setdbat(3, BAT3Addr, BAT3Addr, 0x10000000, IO_PAGE);
316#ifdef SHOW_MORE_INIT_SETTINGS
317    printk("Setting up BAT3 for large memory support. (BAT3 --> 0x%x)\n", BAT3Addr);
318#endif
319  }
320
321  /* Allocate and set up the page table mappings
322   * This is only available on >604 CPUs.
323   *
324   * NOTE: This setup routine may modify the available memory
325   *       size. It is essential to call it before
326   *       calculating the workspace etc.
327   */
328  pt = BSP_pgtbl_setup(&BSP_mem_size);
329
330  if (!pt || TRIV121_MAP_SUCCESS != triv121PgTblMap(
331            pt, TRIV121_121_VSID,
332#ifndef qemu
333            0xfeff0000,
334#else
335            0xbffff000,
336#endif
337            1,
338            TRIV121_ATTR_IO_PAGE, TRIV121_PP_RW_PAGE)) {
339        printk("WARNING: unable to setup page tables VME "
340               "bridge must share PCI space\n");
341  }
342
343  /*
344   *  initialize the device driver parameters
345   */
346  bsp_clicks_per_usec    = BSP_bus_frequency/(BSP_time_base_divisor * 1000);
347  rtems_counter_initialize_converter(
348    BSP_bus_frequency / (BSP_time_base_divisor / 1000)
349  );
350
351  /*
352   * Initalize RTEMS IRQ system
353   */
354  BSP_rtems_irq_mng_init(0);
355
356  /* Activate the page table mappings only after
357   * initializing interrupts because the irq_mng_init()
358   * routine needs to modify the text
359   */
360  if (pt) {
361#ifdef  SHOW_MORE_INIT_SETTINGS
362    printk("Page table setup finished; will activate it NOW...\n");
363#endif
364    BSP_pgtbl_activate(pt);
365    /* finally, switch off DBAT3 */
366    setdbat(3, 0, 0, 0, 0);
367  }
368
369#if defined(DEBUG_BATS)
370  ShowBATS();
371#endif
372
373#ifdef SHOW_MORE_INIT_SETTINGS
374  printk("Exit from bspstart\n");
375#endif
376}
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