source: rtems/c/src/lib/libbsp/powerpc/shared/startup/bspstart.c @ 591e964e

4.115
Last change on this file since 591e964e was 591e964e, checked in by Ralf Corsepius <ralf.corsepius@…>, on 10/07/11 at 14:29:38

2011-10-07 Ralf Corsépius <ralf.corsepius@…>

  • shared/startup/bspstart.c: Comment out unused vars.
  • Property mode set to 100644
File size: 9.5 KB
Line 
1/*
2 *  This routine starts the application.  It includes application,
3 *  board, and monitor specific initialization and configuration.
4 *  The generic CPU dependent initialization has been performed
5 *  before this routine is invoked.
6 *
7 *  COPYRIGHT (c) 1989-2007.
8 *  On-Line Applications Research Corporation (OAR).
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.rtems.com/license/LICENSE.
13 *
14 *  Modified to support the MCP750.
15 *  Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
16 *
17 *  $Id$
18 */
19
20#include <string.h>
21
22#include <bsp.h>
23#include <rtems/bspIo.h>
24#include <bsp/consoleIo.h>
25#include <libcpu/spr.h>
26#include <bsp/residual.h>
27#include <bsp/pci.h>
28#include <bsp/openpic.h>
29#include <bsp/irq.h>
30#include <libcpu/bat.h>
31#include <libcpu/pte121.h>
32#include <libcpu/cpuIdent.h>
33#include <bsp/vectors.h>
34#include <bsp/motorola.h>
35#include <rtems/powerpc/powerpc.h>
36
37extern void _return_to_ppcbug(void);
38extern unsigned long __rtems_end[];
39extern void L1_caches_enables(void);
40extern unsigned get_L2CR(void);
41extern void set_L2CR(unsigned);
42extern Triv121PgTbl BSP_pgtbl_setup(unsigned int *);
43extern void                     BSP_pgtbl_activate(Triv121PgTbl);
44
45SPR_RW(SPRG1)
46
47#if defined(DEBUG_BATS)
48extern void ShowBATS(void);
49#endif
50
51/*
52 *  Driver configuration parameters
53 */
54uint32_t   bsp_clicks_per_usec;
55
56/*
57 * Copy of residuals passed by firmware
58 */
59RESIDUAL residualCopy;
60/*
61 * Copy Additional boot param passed by boot loader
62 */
63#define MAX_LOADER_ADD_PARM 80
64char loaderParam[MAX_LOADER_ADD_PARM];
65
66char *BSP_commandline_string = loaderParam;
67/*
68 * Vital Board data Start using DATA RESIDUAL
69 */
70/*
71 * Total memory using RESIDUAL DATA
72 */
73unsigned int BSP_mem_size;
74
75/*
76 * PCI Bus Frequency
77 */
78unsigned int BSP_bus_frequency;
79/*
80 * processor clock frequency
81 */
82unsigned int BSP_processor_frequency;
83/*
84 * Time base divisior (how many tick for 1 second).
85 */
86unsigned int BSP_time_base_divisor;
87
88void BSP_panic(char *s)
89{
90  printk("%s PANIC %s\n",_RTEMS_version, s);
91  __asm__ __volatile ("sc");
92}
93
94void _BSP_Fatal_error(unsigned int v)
95{
96  printk("%s PANIC ERROR %x\n",_RTEMS_version, v);
97  __asm__ __volatile ("sc");
98}
99
100/*
101 *  Use the shared implementations of the following routines
102 */
103
104char * save_boot_params(
105  RESIDUAL *r3,
106  void     *r4,
107  void     *r5,
108  char     *additional_boot_options
109)
110{
111
112  residualCopy = *r3;
113  strncpy(loaderParam, additional_boot_options, MAX_LOADER_ADD_PARM);
114  loaderParam[MAX_LOADER_ADD_PARM - 1] ='\0';
115  return loaderParam;
116}
117
118#if defined(mvme2100)
119unsigned int EUMBBAR;
120
121/*
122 * Return the current value of the Embedded Utilities Memory Block Base Address
123 * Register (EUMBBAR) as read from the processor configuration register using
124 * Processor Address Map B (CHRP).
125 */
126unsigned int get_eumbbar(void) {
127  out_le32( (volatile unsigned *)0xfec00000, 0x80000078 );
128  return in_le32( (volatile unsigned *)0xfee00000 );
129}
130#endif
131
132/*
133 *  bsp_start
134 *
135 *  This routine does the bulk of the system initialization.
136 */
137
138void bsp_start( void )
139{
140  rtems_status_code sc = RTEMS_SUCCESSFUL;
141#if !defined(mvme2100)
142  unsigned l2cr;
143#endif
144  uintptr_t intrStackStart;
145  uintptr_t intrStackSize;
146/*  ppc_cpu_id_t myCpu; */
147/*  ppc_cpu_revision_t myCpuRevision; */
148  prep_t boardManufacturer;
149  motorolaBoard myBoard;
150  Triv121PgTbl  pt=0;
151
152  /*
153   * Get CPU identification dynamically. Note that the get_ppc_cpu_type()
154   * function store the result in global variables so that it can be used
155   * later...
156   */
157  /* myCpu      = */ get_ppc_cpu_type();
158  /* myCpuRevision = */ get_ppc_cpu_revision();
159
160  /*
161   * Init MMU block address translation to enable hardware access
162   */
163
164#if !defined(mvme2100)
165  /*
166   * PC legacy IO space used for inb/outb and all PC compatible hardware
167   */
168  setdbat(1, _IO_BASE, _IO_BASE, 0x10000000, IO_PAGE);
169#endif
170
171  /*
172   * PCI devices memory area. Needed to access OpenPIC features
173   * provided by the Raven
174   *
175   * T. Straumann: give more PCI address space
176   */
177  setdbat(2, PCI_MEM_BASE+PCI_MEM_WIN0, PCI_MEM_BASE+PCI_MEM_WIN0, 0x10000000, IO_PAGE);
178
179  /*
180   * Must have acces to open pic PCI ACK registers provided by the RAVEN
181   */
182#ifndef qemu
183  setdbat(3, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE);
184#else
185  setdbat(3, 0xb0000000, 0xb0000000, 0x10000000, IO_PAGE);
186#endif
187
188#if defined(mvme2100)
189  /* Need 0xfec00000 mapped for this */
190  EUMBBAR = get_eumbbar();
191#endif
192
193  /*
194   * enables L1 Cache. Note that the L1_caches_enables() codes checks for
195   * relevant CPU type so that the reason why there is no use of myCpu...
196   */
197  L1_caches_enables();
198
199  select_console(CONSOLE_LOG);
200
201  /*
202   * We check that the keyboard is present and immediately
203   * select the serial console if not.
204   */
205#if defined(BSP_KBD_IOBASE)
206  { int err;
207    err = kbdreset();
208    if (err) select_console(CONSOLE_SERIAL);
209  }
210#else
211  select_console(CONSOLE_SERIAL);
212#endif
213
214
215#if !defined(mvme2100)
216  /*
217   * Enable L2 Cache. Note that the set_L2CR(L2CR) codes checks for
218   * relevant CPU type (mpc750)...
219   */
220  l2cr = get_L2CR();
221#ifdef SHOW_LCR2_REGISTER
222  printk("Initial L2CR value = %x\n", l2cr);
223#endif
224  if ( (! (l2cr & 0x80000000)) && ((int) l2cr == -1))
225    set_L2CR(0xb9A14000);
226#endif
227
228  /*
229   * Initialize the interrupt related settings.
230   */
231  intrStackStart = (uintptr_t) __rtems_end;
232  intrStackSize = rtems_configuration_get_interrupt_stack_size();
233
234  /*
235   * Initialize default raw exception handlers.
236   */
237  sc = ppc_exc_initialize(
238    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
239    intrStackStart,
240    intrStackSize
241  );
242  if (sc != RTEMS_SUCCESSFUL) {
243    BSP_panic("cannot initialize exceptions");
244  }
245
246  boardManufacturer   =  checkPrepBoardType(&residualCopy);
247  if (boardManufacturer != PREP_Motorola) {
248    printk("Unsupported hardware vendor\n");
249    while (1);
250  }
251  myBoard = getMotorolaBoard();
252
253  printk("-----------------------------------------\n");
254  printk("Welcome to %s on %s\n", _RTEMS_version,
255                                    motorolaBoardToString(myBoard));
256  printk("-----------------------------------------\n");
257#ifdef SHOW_MORE_INIT_SETTINGS
258  printk("Residuals are located at %x\n", (unsigned) &residualCopy);
259  printk("Additionnal boot options are %s\n", loaderParam);
260  printk("Software IRQ stack starts at %x with size %u\n", intrStackStart, intrStackSize);
261  printk("-----------------------------------------\n");
262#endif
263
264#ifdef TEST_RETURN_TO_PPCBUG
265  printk("Hit <Enter> to return to PPCBUG monitor\n");
266  printk("When Finished hit GO. It should print <Back from monitor>\n");
267  debug_getc();
268  _return_to_ppcbug();
269  printk("Back from monitor\n");
270  _return_to_ppcbug();
271#endif /* TEST_RETURN_TO_PPCBUG  */
272
273#ifdef SHOW_MORE_INIT_SETTINGS
274  printk("Going to start PCI buses scanning and initialization\n");
275#endif
276
277  pci_initialize();
278  {
279    const struct _int_map *bspmap  = motorolaIntMap(currentBoard);
280    if( bspmap ) {
281       printk("pci : Configuring interrupt routing for '%s'\n",
282          motorolaBoardToString(currentBoard));
283       FixupPCI(bspmap, motorolaIntSwizzle(currentBoard));
284    }
285    else
286       printk("pci : Interrupt routing not available for this bsp\n");
287 }
288
289#ifdef SHOW_MORE_INIT_SETTINGS
290  printk("Number of PCI buses found is : %d\n", pci_bus_count());
291#endif
292#ifdef TEST_RAW_EXCEPTION_CODE
293  printk("Testing exception handling Part 1\n");
294  /*
295   * Cause a software exception
296   */
297  __asm__ __volatile ("sc");
298  /*
299   * Check we can still catch exceptions and return coorectly.
300   */
301  printk("Testing exception handling Part 2\n");
302  __asm__ __volatile ("sc");
303
304  /*
305   * Somehow doing the above seems to clobber SPRG0 on the mvme2100.  The
306   * interrupt disable mask is stored in SPRG0. Is this a problem?
307   */
308  ppc_interrupt_set_disable_mask( PPC_INTERRUPT_DISABLE_MASK_DEFAULT);
309
310#endif
311
312/* See above */
313
314  BSP_mem_size            = residualCopy.TotalMemory;
315  BSP_bus_frequency       = residualCopy.VitalProductData.ProcessorBusHz;
316  BSP_processor_frequency = residualCopy.VitalProductData.ProcessorHz;
317  BSP_time_base_divisor   = (residualCopy.VitalProductData.TimeBaseDivisor?
318                    residualCopy.VitalProductData.TimeBaseDivisor : 4000);
319
320  /* clear hostbridge errors but leave MCP disabled -
321   * PCI config space scanning code will trip otherwise :-(
322   */
323  _BSP_clear_hostbridge_errors(0 /* enableMCP */, 0/*quiet*/);
324
325  /* Allocate and set up the page table mappings
326   * This is only available on >604 CPUs.
327   *
328   * NOTE: This setup routine may modify the available memory
329   *       size. It is essential to call it before
330   *       calculating the workspace etc.
331   */
332  pt = BSP_pgtbl_setup(&BSP_mem_size);
333
334  if (!pt || TRIV121_MAP_SUCCESS != triv121PgTblMap(
335            pt, TRIV121_121_VSID,
336#ifndef qemu
337            0xfeff0000,
338#else
339            0xbffff000,
340#endif
341            1,
342            TRIV121_ATTR_IO_PAGE, TRIV121_PP_RW_PAGE)) {
343        printk("WARNING: unable to setup page tables VME "
344               "bridge must share PCI space\n");
345  }
346
347  /*
348   *  initialize the device driver parameters
349   */
350  bsp_clicks_per_usec    = BSP_bus_frequency/(BSP_time_base_divisor * 1000);
351
352  /*
353   * Initalize RTEMS IRQ system
354   */
355  BSP_rtems_irq_mng_init(0);
356
357  /* Activate the page table mappings only after
358   * initializing interrupts because the irq_mng_init()
359   * routine needs to modify the text
360   */
361  if (pt) {
362#ifdef  SHOW_MORE_INIT_SETTINGS
363    printk("Page table setup finished; will activate it NOW...\n");
364#endif
365    BSP_pgtbl_activate(pt);
366    /* finally, switch off DBAT3 */
367    setdbat(3, 0, 0, 0, 0);
368  }
369
370#if defined(DEBUG_BATS)
371  ShowBATS();
372#endif
373
374#ifdef SHOW_MORE_INIT_SETTINGS
375  printk("Exit from bspstart\n");
376#endif
377}
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