1 | /* |
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2 | * This routine starts the application. It includes application, |
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3 | * board, and monitor specific initialization and configuration. |
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4 | * The generic CPU dependent initialization has been performed |
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5 | * before this routine is invoked. |
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6 | * |
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7 | * COPYRIGHT (c) 1989-2007. |
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8 | * On-Line Applications Research Corporation (OAR). |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.com/license/LICENSE. |
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13 | * |
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14 | * Modified to support the MCP750. |
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15 | * Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr |
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16 | * |
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17 | * $Id$ |
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18 | */ |
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19 | |
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20 | #include <string.h> |
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21 | |
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22 | #include <bsp.h> |
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23 | #include <rtems/bspIo.h> |
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24 | #include <bsp/consoleIo.h> |
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25 | #include <libcpu/spr.h> |
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26 | #include <bsp/residual.h> |
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27 | #include <bsp/pci.h> |
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28 | #include <bsp/openpic.h> |
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29 | #include <bsp/irq.h> |
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30 | #include <libcpu/bat.h> |
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31 | #include <libcpu/pte121.h> |
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32 | #include <libcpu/cpuIdent.h> |
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33 | #include <bsp/vectors.h> |
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34 | #include <bsp/motorola.h> |
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35 | #include <rtems/powerpc/powerpc.h> |
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36 | |
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37 | extern void _return_to_ppcbug(void); |
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38 | extern unsigned long __rtems_end[]; |
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39 | extern void L1_caches_enables(void); |
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40 | extern unsigned get_L2CR(void); |
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41 | extern void set_L2CR(unsigned); |
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42 | extern Triv121PgTbl BSP_pgtbl_setup(unsigned int *); |
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43 | extern void BSP_pgtbl_activate(Triv121PgTbl); |
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44 | |
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45 | SPR_RW(SPRG1) |
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46 | |
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47 | #if defined(DEBUG_BATS) |
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48 | extern void ShowBATS(void); |
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49 | #endif |
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50 | |
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51 | /* |
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52 | * Driver configuration parameters |
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53 | */ |
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54 | uint32_t bsp_clicks_per_usec; |
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55 | |
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56 | /* |
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57 | * Copy of residuals passed by firmware |
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58 | */ |
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59 | RESIDUAL residualCopy; |
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60 | /* |
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61 | * Copy Additional boot param passed by boot loader |
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62 | */ |
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63 | #define MAX_LOADER_ADD_PARM 80 |
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64 | char loaderParam[MAX_LOADER_ADD_PARM]; |
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65 | |
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66 | char *BSP_commandline_string = loaderParam; |
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67 | /* |
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68 | * Vital Board data Start using DATA RESIDUAL |
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69 | */ |
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70 | /* |
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71 | * Total memory using RESIDUAL DATA |
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72 | */ |
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73 | unsigned int BSP_mem_size; |
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74 | |
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75 | /* |
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76 | * PCI Bus Frequency |
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77 | */ |
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78 | unsigned int BSP_bus_frequency; |
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79 | /* |
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80 | * processor clock frequency |
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81 | */ |
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82 | unsigned int BSP_processor_frequency; |
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83 | /* |
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84 | * Time base divisior (how many tick for 1 second). |
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85 | */ |
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86 | unsigned int BSP_time_base_divisor; |
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87 | |
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88 | void BSP_panic(char *s) |
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89 | { |
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90 | printk("%s PANIC %s\n",_RTEMS_version, s); |
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91 | __asm__ __volatile ("sc"); |
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92 | } |
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93 | |
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94 | void _BSP_Fatal_error(unsigned int v) |
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95 | { |
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96 | printk("%s PANIC ERROR %x\n",_RTEMS_version, v); |
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97 | __asm__ __volatile ("sc"); |
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98 | } |
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99 | |
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100 | /* |
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101 | * Use the shared implementations of the following routines |
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102 | */ |
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103 | |
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104 | char * save_boot_params( |
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105 | RESIDUAL *r3, |
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106 | void *r4, |
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107 | void *r5, |
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108 | char *additional_boot_options |
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109 | ) |
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110 | { |
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111 | |
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112 | residualCopy = *r3; |
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113 | strncpy(loaderParam, additional_boot_options, MAX_LOADER_ADD_PARM); |
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114 | loaderParam[MAX_LOADER_ADD_PARM - 1] ='\0'; |
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115 | return loaderParam; |
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116 | } |
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117 | |
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118 | #if defined(mvme2100) |
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119 | unsigned int EUMBBAR; |
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120 | |
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121 | /* |
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122 | * Return the current value of the Embedded Utilities Memory Block Base Address |
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123 | * Register (EUMBBAR) as read from the processor configuration register using |
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124 | * Processor Address Map B (CHRP). |
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125 | */ |
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126 | unsigned int get_eumbbar(void) { |
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127 | out_le32( (volatile unsigned *)0xfec00000, 0x80000078 ); |
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128 | return in_le32( (volatile unsigned *)0xfee00000 ); |
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129 | } |
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130 | #endif |
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131 | |
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132 | /* |
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133 | * bsp_start |
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134 | * |
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135 | * This routine does the bulk of the system initialization. |
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136 | */ |
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137 | |
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138 | void bsp_start( void ) |
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139 | { |
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140 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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141 | #if !defined(mvme2100) |
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142 | unsigned l2cr; |
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143 | #endif |
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144 | uintptr_t intrStackStart; |
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145 | uintptr_t intrStackSize; |
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146 | ppc_cpu_id_t myCpu; |
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147 | ppc_cpu_revision_t myCpuRevision; |
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148 | prep_t boardManufacturer; |
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149 | motorolaBoard myBoard; |
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150 | Triv121PgTbl pt=0; |
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151 | |
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152 | /* |
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153 | * Get CPU identification dynamically. Note that the get_ppc_cpu_type() |
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154 | * function store the result in global variables so that it can be used |
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155 | * later... |
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156 | */ |
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157 | myCpu = get_ppc_cpu_type(); |
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158 | myCpuRevision = get_ppc_cpu_revision(); |
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159 | |
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160 | /* |
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161 | * Init MMU block address translation to enable hardware access |
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162 | */ |
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163 | |
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164 | #if !defined(mvme2100) |
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165 | /* |
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166 | * PC legacy IO space used for inb/outb and all PC compatible hardware |
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167 | */ |
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168 | setdbat(1, _IO_BASE, _IO_BASE, 0x10000000, IO_PAGE); |
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169 | #endif |
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170 | |
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171 | /* |
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172 | * PCI devices memory area. Needed to access OpenPIC features |
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173 | * provided by the Raven |
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174 | * |
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175 | * T. Straumann: give more PCI address space |
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176 | */ |
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177 | setdbat(2, PCI_MEM_BASE+PCI_MEM_WIN0, PCI_MEM_BASE+PCI_MEM_WIN0, 0x10000000, IO_PAGE); |
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178 | |
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179 | /* |
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180 | * Must have acces to open pic PCI ACK registers provided by the RAVEN |
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181 | */ |
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182 | #ifndef qemu |
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183 | setdbat(3, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE); |
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184 | #else |
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185 | setdbat(3, 0xb0000000, 0xb0000000, 0x10000000, IO_PAGE); |
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186 | #endif |
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187 | |
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188 | #if defined(mvme2100) |
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189 | /* Need 0xfec00000 mapped for this */ |
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190 | EUMBBAR = get_eumbbar(); |
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191 | #endif |
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192 | |
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193 | /* |
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194 | * enables L1 Cache. Note that the L1_caches_enables() codes checks for |
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195 | * relevant CPU type so that the reason why there is no use of myCpu... |
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196 | */ |
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197 | L1_caches_enables(); |
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198 | |
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199 | select_console(CONSOLE_LOG); |
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200 | |
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201 | /* |
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202 | * We check that the keyboard is present and immediately |
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203 | * select the serial console if not. |
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204 | */ |
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205 | #if defined(BSP_KBD_IOBASE) |
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206 | { int err; |
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207 | err = kbdreset(); |
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208 | if (err) select_console(CONSOLE_SERIAL); |
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209 | } |
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210 | #else |
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211 | select_console(CONSOLE_SERIAL); |
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212 | #endif |
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213 | |
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214 | |
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215 | #if !defined(mvme2100) |
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216 | /* |
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217 | * Enable L2 Cache. Note that the set_L2CR(L2CR) codes checks for |
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218 | * relevant CPU type (mpc750)... |
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219 | */ |
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220 | l2cr = get_L2CR(); |
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221 | #ifdef SHOW_LCR2_REGISTER |
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222 | printk("Initial L2CR value = %x\n", l2cr); |
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223 | #endif |
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224 | if ( (! (l2cr & 0x80000000)) && ((int) l2cr == -1)) |
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225 | set_L2CR(0xb9A14000); |
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226 | #endif |
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227 | |
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228 | /* |
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229 | * Initialize the interrupt related settings. |
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230 | */ |
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231 | intrStackStart = (uintptr_t) __rtems_end; |
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232 | intrStackSize = rtems_configuration_get_interrupt_stack_size(); |
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233 | |
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234 | /* |
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235 | * Initialize default raw exception handlers. |
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236 | */ |
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237 | sc = ppc_exc_initialize( |
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238 | PPC_INTERRUPT_DISABLE_MASK_DEFAULT, |
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239 | intrStackStart, |
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240 | intrStackSize |
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241 | ); |
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242 | if (sc != RTEMS_SUCCESSFUL) { |
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243 | BSP_panic("cannot initialize exceptions"); |
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244 | } |
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245 | |
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246 | boardManufacturer = checkPrepBoardType(&residualCopy); |
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247 | if (boardManufacturer != PREP_Motorola) { |
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248 | printk("Unsupported hardware vendor\n"); |
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249 | while (1); |
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250 | } |
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251 | myBoard = getMotorolaBoard(); |
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252 | |
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253 | printk("-----------------------------------------\n"); |
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254 | printk("Welcome to %s on %s\n", _RTEMS_version, |
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255 | motorolaBoardToString(myBoard)); |
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256 | printk("-----------------------------------------\n"); |
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257 | #ifdef SHOW_MORE_INIT_SETTINGS |
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258 | printk("Residuals are located at %x\n", (unsigned) &residualCopy); |
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259 | printk("Additionnal boot options are %s\n", loaderParam); |
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260 | printk("Software IRQ stack starts at %x with size %u\n", intrStackStart, intrStackSize); |
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261 | printk("-----------------------------------------\n"); |
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262 | #endif |
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263 | |
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264 | #ifdef TEST_RETURN_TO_PPCBUG |
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265 | printk("Hit <Enter> to return to PPCBUG monitor\n"); |
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266 | printk("When Finished hit GO. It should print <Back from monitor>\n"); |
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267 | debug_getc(); |
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268 | _return_to_ppcbug(); |
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269 | printk("Back from monitor\n"); |
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270 | _return_to_ppcbug(); |
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271 | #endif /* TEST_RETURN_TO_PPCBUG */ |
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272 | |
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273 | #ifdef SHOW_MORE_INIT_SETTINGS |
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274 | printk("Going to start PCI buses scanning and initialization\n"); |
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275 | #endif |
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276 | |
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277 | pci_initialize(); |
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278 | { |
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279 | const struct _int_map *bspmap = motorolaIntMap(currentBoard); |
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280 | if( bspmap ) { |
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281 | printk("pci : Configuring interrupt routing for '%s'\n", |
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282 | motorolaBoardToString(currentBoard)); |
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283 | FixupPCI(bspmap, motorolaIntSwizzle(currentBoard)); |
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284 | } |
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285 | else |
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286 | printk("pci : Interrupt routing not available for this bsp\n"); |
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287 | } |
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288 | |
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289 | #ifdef SHOW_MORE_INIT_SETTINGS |
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290 | printk("Number of PCI buses found is : %d\n", pci_bus_count()); |
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291 | #endif |
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292 | #ifdef TEST_RAW_EXCEPTION_CODE |
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293 | printk("Testing exception handling Part 1\n"); |
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294 | /* |
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295 | * Cause a software exception |
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296 | */ |
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297 | __asm__ __volatile ("sc"); |
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298 | /* |
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299 | * Check we can still catch exceptions and return coorectly. |
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300 | */ |
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301 | printk("Testing exception handling Part 2\n"); |
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302 | __asm__ __volatile ("sc"); |
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303 | |
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304 | /* |
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305 | * Somehow doing the above seems to clobber SPRG0 on the mvme2100. The |
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306 | * interrupt disable mask is stored in SPRG0. Is this a problem? |
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307 | */ |
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308 | ppc_interrupt_set_disable_mask( PPC_INTERRUPT_DISABLE_MASK_DEFAULT); |
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309 | |
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310 | #endif |
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311 | |
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312 | /* See above */ |
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313 | |
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314 | BSP_mem_size = residualCopy.TotalMemory; |
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315 | BSP_bus_frequency = residualCopy.VitalProductData.ProcessorBusHz; |
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316 | BSP_processor_frequency = residualCopy.VitalProductData.ProcessorHz; |
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317 | BSP_time_base_divisor = (residualCopy.VitalProductData.TimeBaseDivisor? |
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318 | residualCopy.VitalProductData.TimeBaseDivisor : 4000); |
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319 | |
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320 | /* clear hostbridge errors but leave MCP disabled - |
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321 | * PCI config space scanning code will trip otherwise :-( |
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322 | */ |
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323 | _BSP_clear_hostbridge_errors(0 /* enableMCP */, 0/*quiet*/); |
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324 | |
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325 | /* Allocate and set up the page table mappings |
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326 | * This is only available on >604 CPUs. |
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327 | * |
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328 | * NOTE: This setup routine may modify the available memory |
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329 | * size. It is essential to call it before |
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330 | * calculating the workspace etc. |
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331 | */ |
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332 | pt = BSP_pgtbl_setup(&BSP_mem_size); |
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333 | |
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334 | if (!pt || TRIV121_MAP_SUCCESS != triv121PgTblMap( |
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335 | pt, TRIV121_121_VSID, |
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336 | #ifndef qemu |
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337 | 0xfeff0000, |
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338 | #else |
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339 | 0xbffff000, |
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340 | #endif |
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341 | 1, |
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342 | TRIV121_ATTR_IO_PAGE, TRIV121_PP_RW_PAGE)) { |
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343 | printk("WARNING: unable to setup page tables VME " |
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344 | "bridge must share PCI space\n"); |
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345 | } |
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346 | |
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347 | /* |
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348 | * initialize the device driver parameters |
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349 | */ |
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350 | bsp_clicks_per_usec = BSP_bus_frequency/(BSP_time_base_divisor * 1000); |
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351 | |
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352 | /* |
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353 | * Initalize RTEMS IRQ system |
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354 | */ |
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355 | BSP_rtems_irq_mng_init(0); |
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356 | |
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357 | /* Activate the page table mappings only after |
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358 | * initializing interrupts because the irq_mng_init() |
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359 | * routine needs to modify the text |
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360 | */ |
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361 | if (pt) { |
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362 | #ifdef SHOW_MORE_INIT_SETTINGS |
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363 | printk("Page table setup finished; will activate it NOW...\n"); |
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364 | #endif |
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365 | BSP_pgtbl_activate(pt); |
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366 | /* finally, switch off DBAT3 */ |
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367 | setdbat(3, 0, 0, 0, 0); |
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368 | } |
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369 | |
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370 | #if defined(DEBUG_BATS) |
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371 | ShowBATS(); |
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372 | #endif |
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373 | |
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374 | #ifdef SHOW_MORE_INIT_SETTINGS |
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375 | printk("Exit from bspstart\n"); |
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376 | #endif |
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377 | } |
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