[acc25ee] | 1 | /* |
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| 2 | * This routine starts the application. It includes application, |
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| 3 | * board, and monitor specific initialization and configuration. |
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| 4 | * The generic CPU dependent initialization has been performed |
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| 5 | * before this routine is invoked. |
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| 6 | * |
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| 7 | * COPYRIGHT (c) 1989-1998. |
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| 8 | * On-Line Applications Research Corporation (OAR). |
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| 9 | * |
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| 10 | * The license and distribution terms for this file may be |
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| 11 | * found in the file LICENSE in this distribution or at |
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[e831de8] | 12 | * http://www.rtems.com/license/LICENSE. |
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[acc25ee] | 13 | * |
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| 14 | * Modified to support the MCP750. |
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| 15 | * Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr |
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| 16 | * |
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| 17 | * $Id$ |
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| 18 | */ |
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| 19 | |
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| 20 | #include <string.h> |
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[eba2e4f] | 21 | |
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[e79a1947] | 22 | #include <bsp.h> |
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[eba2e4f] | 23 | #include <rtems/libio.h> |
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| 24 | #include <rtems/libcsupport.h> |
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[acc25ee] | 25 | #include <bsp/consoleIo.h> |
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| 26 | #include <libcpu/spr.h> |
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| 27 | #include <bsp/residual.h> |
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| 28 | #include <bsp/pci.h> |
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| 29 | #include <bsp/openpic.h> |
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| 30 | #include <bsp/irq.h> |
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[4f3e4f33] | 31 | #include <bsp/VME.h> |
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[acc25ee] | 32 | #include <libcpu/bat.h> |
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[4f3e4f33] | 33 | #include <libcpu/pte121.h> |
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[70f1268d] | 34 | #include <libcpu/cpuIdent.h> |
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[acc25ee] | 35 | #include <bsp/vectors.h> |
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| 36 | #include <bsp/motorola.h> |
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| 37 | |
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| 38 | extern void _return_to_ppcbug(); |
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[64f8ae4] | 39 | extern unsigned long __rtems_end[]; |
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[acc25ee] | 40 | extern void L1_caches_enables(); |
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| 41 | extern unsigned get_L2CR(); |
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| 42 | extern void set_L2CR(unsigned); |
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| 43 | extern void bsp_cleanup(void); |
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[4f3e4f33] | 44 | extern Triv121PgTbl BSP_pgtbl_setup(); |
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| 45 | extern void BSP_pgtbl_activate(); |
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| 46 | extern void BSP_vme_config(); |
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| 47 | |
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[ec821af] | 48 | SPR_RW(SPRG0) |
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| 49 | SPR_RW(SPRG1) |
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[4f3e4f33] | 50 | |
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[e79a1947] | 51 | #if defined(DEBUG_BATS) |
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| 52 | void printBAT( int bat, unsigned32 upper, unsigned32 lower ) |
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| 53 | { |
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| 54 | unsigned32 lowest_addr; |
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| 55 | unsigned32 size; |
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| 56 | |
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| 57 | printk("BAT%d raw(upper=0x%08x, lower=0x%08x) ", bat, upper, lower ); |
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| 58 | |
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| 59 | lowest_addr = (upper & 0xFFFE0000); |
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| 60 | size = (((upper & 0x00001FFC) >> 2) + 1) * (128 * 1024); |
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| 61 | printk(" range(0x%08x, 0x%08x) %s%s %s%s%s%s %s\n", |
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| 62 | lowest_addr, |
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| 63 | lowest_addr + (size - 1), |
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| 64 | (upper & 0x01) ? "P" : "p", |
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| 65 | (upper & 0x02) ? "S" : "s", |
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| 66 | (lower & 0x08) ? "G" : "g", |
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| 67 | (lower & 0x10) ? "M" : "m", |
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| 68 | (lower & 0x20) ? "I" : "i", |
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| 69 | (lower & 0x40) ? "W" : "w", |
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| 70 | (lower & 0x01) ? "Read Only" : |
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| 71 | ((lower & 0x02) ? "Read/Write" : "No Access") |
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| 72 | ); |
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| 73 | } |
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| 74 | |
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| 75 | void ShowBATS(){ |
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| 76 | unsigned32 lower; |
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| 77 | unsigned32 upper; |
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| 78 | |
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| 79 | __MFSPR(536, upper); __MFSPR(537, lower); printBAT( 0, upper, lower ); |
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| 80 | __MFSPR(538, upper); __MFSPR(539, lower); printBAT( 1, upper, lower ); |
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| 81 | __MFSPR(540, upper); __MFSPR(541, lower); printBAT( 2, upper, lower ); |
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| 82 | __MFSPR(542, upper); __MFSPR(543, lower); printBAT( 3, upper, lower ); |
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| 83 | } |
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| 84 | #endif |
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| 85 | |
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[acc25ee] | 86 | /* |
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| 87 | * Copy of residuals passed by firmware |
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| 88 | */ |
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[6128a4a] | 89 | RESIDUAL residualCopy; |
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[acc25ee] | 90 | /* |
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| 91 | * Copy Additional boot param passed by boot loader |
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| 92 | */ |
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| 93 | #define MAX_LOADER_ADD_PARM 80 |
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| 94 | char loaderParam[MAX_LOADER_ADD_PARM]; |
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| 95 | /* |
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| 96 | * Vital Board data Start using DATA RESIDUAL |
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| 97 | */ |
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| 98 | /* |
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| 99 | * Total memory using RESIDUAL DATA |
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| 100 | */ |
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| 101 | unsigned int BSP_mem_size; |
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| 102 | /* |
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| 103 | * PCI Bus Frequency |
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| 104 | */ |
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| 105 | unsigned int BSP_bus_frequency; |
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| 106 | /* |
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| 107 | * processor clock frequency |
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| 108 | */ |
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| 109 | unsigned int BSP_processor_frequency; |
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| 110 | /* |
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| 111 | * Time base divisior (how many tick for 1 second). |
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| 112 | */ |
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| 113 | unsigned int BSP_time_base_divisor; |
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| 114 | /* |
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| 115 | * system init stack and soft ir stack size |
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| 116 | */ |
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| 117 | #define INIT_STACK_SIZE 0x1000 |
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[df49c60] | 118 | #define INTR_STACK_SIZE CONFIGURE_INTERRUPT_STACK_MEMORY |
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[acc25ee] | 119 | |
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| 120 | void BSP_panic(char *s) |
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| 121 | { |
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[ef99210e] | 122 | printk("%s PANIC %s\n",_RTEMS_version, s); |
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[6128a4a] | 123 | __asm__ __volatile ("sc"); |
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[acc25ee] | 124 | } |
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| 125 | |
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| 126 | void _BSP_Fatal_error(unsigned int v) |
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| 127 | { |
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[ef99210e] | 128 | printk("%s PANIC ERROR %x\n",_RTEMS_version, v); |
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[6128a4a] | 129 | __asm__ __volatile ("sc"); |
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[acc25ee] | 130 | } |
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[6128a4a] | 131 | |
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[acc25ee] | 132 | /* |
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| 133 | * The original table from the application and our copy of it with |
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| 134 | * some changes. |
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| 135 | */ |
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| 136 | |
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| 137 | extern rtems_configuration_table Configuration; |
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| 138 | |
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| 139 | rtems_configuration_table BSP_Configuration; |
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| 140 | |
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| 141 | rtems_cpu_table Cpu_table; |
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| 142 | |
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| 143 | char *rtems_progname; |
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| 144 | |
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| 145 | /* |
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| 146 | * Use the shared implementations of the following routines |
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| 147 | */ |
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[6128a4a] | 148 | |
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[acc25ee] | 149 | void bsp_postdriver_hook(void); |
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[bde7f268] | 150 | void bsp_libc_init( void *, uint32_t, int ); |
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[acc25ee] | 151 | |
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| 152 | /* |
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| 153 | * Function: bsp_pretasking_hook |
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| 154 | * Created: 95/03/10 |
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| 155 | * |
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| 156 | * Description: |
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| 157 | * BSP pretasking hook. Called just before drivers are initialized. |
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| 158 | * Used to setup libc and install any BSP extensions. |
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| 159 | * |
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| 160 | * NOTES: |
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| 161 | * Must not use libc (to do io) from here, since drivers are |
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| 162 | * not yet initialized. |
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| 163 | * |
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| 164 | */ |
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[6128a4a] | 165 | |
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[acc25ee] | 166 | void bsp_pretasking_hook(void) |
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| 167 | { |
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[e79a1947] | 168 | rtems_unsigned32 heap_start; |
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| 169 | rtems_unsigned32 heap_size; |
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| 170 | rtems_unsigned32 heap_sbrk_spared; |
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| 171 | extern rtems_unsigned32 _bsp_sbrk_init(rtems_unsigned32, rtems_unsigned32*); |
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[acc25ee] | 172 | |
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[e79a1947] | 173 | heap_start = ((rtems_unsigned32) __rtems_end) + |
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| 174 | INIT_STACK_SIZE + INTR_STACK_SIZE; |
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| 175 | if (heap_start & (CPU_ALIGNMENT-1)) |
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| 176 | heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1); |
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[acc25ee] | 177 | |
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[e79a1947] | 178 | heap_size = (BSP_mem_size - heap_start) - BSP_Configuration.work_space_size; |
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| 179 | heap_sbrk_spared=_bsp_sbrk_init(heap_start, &heap_size); |
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[92b67b18] | 180 | |
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[acc25ee] | 181 | #ifdef SHOW_MORE_INIT_SETTINGS |
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[e79a1947] | 182 | printk( "HEAP start %x size %x (%x bytes spared for sbrk)\n", |
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| 183 | heap_start, heap_size, heap_sbrk_spared); |
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| 184 | #endif |
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[92b67b18] | 185 | |
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[e79a1947] | 186 | bsp_libc_init((void *) 0, heap_size, heap_sbrk_spared); |
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[92b67b18] | 187 | |
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[acc25ee] | 188 | #ifdef RTEMS_DEBUG |
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[e79a1947] | 189 | rtems_debug_enable( RTEMS_DEBUG_ALL_MASK ); |
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[acc25ee] | 190 | #endif |
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| 191 | } |
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| 192 | |
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| 193 | void zero_bss() |
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| 194 | { |
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[64f8ae4] | 195 | /* prevent these from being accessed in the short data areas */ |
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| 196 | extern unsigned long __bss_start[], __SBSS_START__[], __SBSS_END__[]; |
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| 197 | extern unsigned long __SBSS2_START__[], __SBSS2_END__[]; |
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| 198 | memset(__SBSS_START__, 0, ((unsigned) __SBSS_END__) - ((unsigned)__SBSS_START__)); |
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| 199 | memset(__SBSS2_START__, 0, ((unsigned) __SBSS2_END__) - ((unsigned)__SBSS2_START__)); |
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| 200 | memset(__bss_start, 0, ((unsigned) __rtems_end) - ((unsigned)__bss_start)); |
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[acc25ee] | 201 | } |
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| 202 | |
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| 203 | void save_boot_params(RESIDUAL* r3, void *r4, void* r5, char *additional_boot_options) |
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| 204 | { |
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[6128a4a] | 205 | |
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[acc25ee] | 206 | residualCopy = *r3; |
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| 207 | strncpy(loaderParam, additional_boot_options, MAX_LOADER_ADD_PARM); |
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| 208 | loaderParam[MAX_LOADER_ADD_PARM - 1] ='\0'; |
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| 209 | } |
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| 210 | |
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[e79a1947] | 211 | #if defined(mpc8240) || defined(mpc8245) |
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| 212 | unsigned int EUMBBAR; |
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| 213 | |
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| 214 | /* |
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| 215 | * Return the current value of the Embedded Utilities Memory Block Base Address |
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| 216 | * Register (EUMBBAR) as read from the processor configuration register using |
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| 217 | * Processor Address Map B (CHRP). |
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| 218 | */ |
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| 219 | unsigned int get_eumbbar() { |
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| 220 | register int a, e; |
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| 221 | |
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| 222 | asm volatile( "lis %0,0xfec0; ori %0,%0,0x0000": "=r" (a) ); |
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| 223 | asm volatile("sync"); |
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| 224 | |
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| 225 | asm volatile("lis %0,0x8000; ori %0,%0,0x0078": "=r"(e) ); |
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| 226 | asm volatile("stwbrx %0,0x0,%1": "=r"(e): "r"(a)); |
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| 227 | asm volatile("sync"); |
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| 228 | |
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| 229 | asm volatile("lis %0,0xfee0; ori %0,%0,0x0000": "=r" (a) ); |
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| 230 | asm volatile("sync"); |
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| 231 | |
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| 232 | asm volatile("lwbrx %0,0x0,%1": "=r" (e): "r" (a)); |
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| 233 | asm volatile("isync"); |
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| 234 | return e; |
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| 235 | } |
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| 236 | #endif |
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| 237 | |
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[acc25ee] | 238 | /* |
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| 239 | * bsp_start |
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| 240 | * |
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| 241 | * This routine does the bulk of the system initialization. |
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| 242 | */ |
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| 243 | |
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| 244 | void bsp_start( void ) |
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| 245 | { |
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| 246 | unsigned char *stack; |
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[e79a1947] | 247 | #if !defined(mpc8240) && !defined(mpc8245) |
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[acc25ee] | 248 | unsigned l2cr; |
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[e79a1947] | 249 | #endif |
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[acc25ee] | 250 | register unsigned char* intrStack; |
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| 251 | unsigned char *work_space_start; |
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| 252 | ppc_cpu_id_t myCpu; |
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| 253 | ppc_cpu_revision_t myCpuRevision; |
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| 254 | prep_t boardManufacturer; |
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| 255 | motorolaBoard myBoard; |
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[4f3e4f33] | 256 | Triv121PgTbl pt=0; |
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[e79a1947] | 257 | |
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[acc25ee] | 258 | /* |
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[e79a1947] | 259 | * Get CPU identification dynamically. Note that the get_ppc_cpu_type() |
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| 260 | * function store the result in global variables so that it can be used |
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| 261 | * later... |
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[acc25ee] | 262 | */ |
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| 263 | myCpu = get_ppc_cpu_type(); |
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| 264 | myCpuRevision = get_ppc_cpu_revision(); |
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[e79a1947] | 265 | |
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| 266 | #if defined(mvme2100) |
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| 267 | EUMBBAR = get_eumbbar(); |
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| 268 | |
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| 269 | Cpu_table.exceptions_in_RAM = TRUE; |
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| 270 | { unsigned v = 0x3000 ; _CPU_MSR_SET(v); } |
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| 271 | #endif |
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| 272 | |
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| 273 | #if !defined(mpc8240) && !defined(mpc8245) |
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[acc25ee] | 274 | /* |
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| 275 | * enables L1 Cache. Note that the L1_caches_enables() codes checks for |
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| 276 | * relevant CPU type so that the reason why there is no use of myCpu... |
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| 277 | */ |
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| 278 | L1_caches_enables(); |
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[e79a1947] | 279 | |
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[acc25ee] | 280 | /* |
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| 281 | * Enable L2 Cache. Note that the set_L2CR(L2CR) codes checks for |
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| 282 | * relevant CPU type (mpc750)... |
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| 283 | */ |
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| 284 | l2cr = get_L2CR(); |
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| 285 | #ifdef SHOW_LCR2_REGISTER |
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| 286 | printk("Initial L2CR value = %x\n", l2cr); |
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[6128a4a] | 287 | #endif |
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[acc25ee] | 288 | if ( (! (l2cr & 0x80000000)) && ((int) l2cr == -1)) |
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| 289 | set_L2CR(0xb9A14000); |
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[e79a1947] | 290 | #endif |
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| 291 | |
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[acc25ee] | 292 | /* |
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| 293 | * the initial stack has aready been set to this value in start.S |
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| 294 | * so there is no need to set it in r1 again... It is just for info |
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| 295 | * so that It can be printed without accessing R1. |
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| 296 | */ |
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[e79a1947] | 297 | stack = ((unsigned char*) __rtems_end) + |
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| 298 | INIT_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE; |
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[69ed59f] | 299 | |
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[e79a1947] | 300 | /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */ |
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[bde7f268] | 301 | *((uint32_t*)stack) = 0; |
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[69ed59f] | 302 | |
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[acc25ee] | 303 | /* |
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| 304 | * Initialize the interrupt related settings |
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| 305 | * SPRG1 = software managed IRQ stack |
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| 306 | * |
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[e79a1947] | 307 | * This could be done later (e.g in IRQ_INIT) but it helps to understand |
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[acc25ee] | 308 | * some settings below... |
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| 309 | */ |
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[e79a1947] | 310 | intrStack = ((unsigned char*) __rtems_end) + |
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| 311 | INIT_STACK_SIZE + INTR_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE; |
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[69ed59f] | 312 | |
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[64f8ae4] | 313 | /* make sure it's properly aligned */ |
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[bde7f268] | 314 | (uint32_t)intrStack &= ~(CPU_STACK_ALIGNMENT-1); |
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[64f8ae4] | 315 | |
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| 316 | /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */ |
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[bde7f268] | 317 | *((uint32_t*)intrStack) = 0; |
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[69ed59f] | 318 | |
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[ec821af] | 319 | _write_SPRG1((unsigned int)intrStack); |
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| 320 | |
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| 321 | /* signal them that we have fixed PR288 - eventually, this should go away */ |
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| 322 | _write_SPRG0(PPC_BSP_HAS_FIXED_PR288); |
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| 323 | |
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[acc25ee] | 324 | /* |
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[e79a1947] | 325 | * Initialize default raw exception handlers. See vectors/vectors_init.c |
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[acc25ee] | 326 | */ |
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| 327 | initialize_exceptions(); |
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[e79a1947] | 328 | |
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[acc25ee] | 329 | /* |
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[e79a1947] | 330 | * Init MMU block address translation to enable hardware access |
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[acc25ee] | 331 | */ |
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[e79a1947] | 332 | |
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| 333 | #if !defined(mvme2100) |
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[acc25ee] | 334 | /* |
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[e79a1947] | 335 | * PC legacy IO space used for inb/outb and all PC compatible hardware |
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[acc25ee] | 336 | */ |
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[4f3e4f33] | 337 | setdbat(1, _IO_BASE, _IO_BASE, 0x10000000, IO_PAGE); |
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[e79a1947] | 338 | #endif |
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| 339 | |
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[acc25ee] | 340 | /* |
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[e79a1947] | 341 | * PCI devices memory area. Needed to access OpenPIC features |
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| 342 | * provided by the Raven |
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| 343 | * |
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| 344 | * T. Straumann: give more PCI address space |
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[acc25ee] | 345 | */ |
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[35f93740] | 346 | setdbat(2, PCI_MEM_BASE, PCI_MEM_BASE, 0x10000000, IO_PAGE); |
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[e79a1947] | 347 | |
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[acc25ee] | 348 | /* |
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[e79a1947] | 349 | * Must have acces to open pic PCI ACK registers provided by the RAVEN |
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[acc25ee] | 350 | */ |
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[95273a6] | 351 | setdbat(3, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE); |
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[4f3e4f33] | 352 | |
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[acc25ee] | 353 | select_console(CONSOLE_LOG); |
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| 354 | |
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[e79a1947] | 355 | /* |
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| 356 | * We check that the keyboard is present and immediately |
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[acc25ee] | 357 | * select the serial console if not. |
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| 358 | */ |
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[e79a1947] | 359 | #if defined(BSP_KBD_IOBASE) |
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| 360 | { int err; |
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| 361 | err = kbdreset(); |
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| 362 | if (err) select_console(CONSOLE_SERIAL); |
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| 363 | } |
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| 364 | #else |
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| 365 | select_console(CONSOLE_SERIAL); |
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| 366 | #endif |
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[acc25ee] | 367 | |
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| 368 | boardManufacturer = checkPrepBoardType(&residualCopy); |
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| 369 | if (boardManufacturer != PREP_Motorola) { |
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| 370 | printk("Unsupported hardware vendor\n"); |
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| 371 | while (1); |
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| 372 | } |
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| 373 | myBoard = getMotorolaBoard(); |
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[6128a4a] | 374 | |
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[acc25ee] | 375 | printk("-----------------------------------------\n"); |
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[e79a1947] | 376 | printk("Welcome to %s on %s\n", _RTEMS_version, |
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| 377 | motorolaBoardToString(myBoard)); |
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[acc25ee] | 378 | printk("-----------------------------------------\n"); |
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[6128a4a] | 379 | #ifdef SHOW_MORE_INIT_SETTINGS |
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[acc25ee] | 380 | printk("Residuals are located at %x\n", (unsigned) &residualCopy); |
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| 381 | printk("Additionnal boot options are %s\n", loaderParam); |
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| 382 | printk("Initial system stack at %x\n",stack); |
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| 383 | printk("Software IRQ stack at %x\n",intrStack); |
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| 384 | printk("-----------------------------------------\n"); |
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| 385 | #endif |
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| 386 | |
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[6128a4a] | 387 | #ifdef TEST_RETURN_TO_PPCBUG |
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[acc25ee] | 388 | printk("Hit <Enter> to return to PPCBUG monitor\n"); |
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| 389 | printk("When Finished hit GO. It should print <Back from monitor>\n"); |
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| 390 | debug_getc(); |
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| 391 | _return_to_ppcbug(); |
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| 392 | printk("Back from monitor\n"); |
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| 393 | _return_to_ppcbug(); |
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| 394 | #endif /* TEST_RETURN_TO_PPCBUG */ |
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| 395 | |
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| 396 | #ifdef SHOW_MORE_INIT_SETTINGS |
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| 397 | printk("Going to start PCI buses scanning and initialization\n"); |
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[6128a4a] | 398 | #endif |
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[acc25ee] | 399 | InitializePCI(); |
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[3a3e0b0e] | 400 | |
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[e79a1947] | 401 | { |
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| 402 | const struct _int_map *bspmap = motorolaIntMap(currentBoard); |
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| 403 | if( bspmap ) { |
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| 404 | printk("pci : Configuring interrupt routing for '%s'\n", |
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| 405 | motorolaBoardToString(currentBoard)); |
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| 406 | FixupPCI(bspmap, motorolaIntSwizzle(currentBoard)); |
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[3a3e0b0e] | 407 | } |
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| 408 | else |
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| 409 | printk("pci : Interrupt routing not available for this bsp\n"); |
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| 410 | } |
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| 411 | |
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[acc25ee] | 412 | #ifdef SHOW_MORE_INIT_SETTINGS |
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| 413 | printk("Number of PCI buses found is : %d\n", BusCountPCI()); |
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| 414 | #endif |
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[6128a4a] | 415 | #ifdef TEST_RAW_EXCEPTION_CODE |
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[acc25ee] | 416 | printk("Testing exception handling Part 1\n"); |
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| 417 | /* |
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| 418 | * Cause a software exception |
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| 419 | */ |
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| 420 | __asm__ __volatile ("sc"); |
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| 421 | /* |
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[e79a1947] | 422 | * Check we can still catch exceptions and return coorectly. |
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[acc25ee] | 423 | */ |
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| 424 | printk("Testing exception handling Part 2\n"); |
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| 425 | __asm__ __volatile ("sc"); |
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[e79a1947] | 426 | |
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| 427 | /* |
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| 428 | * Somehow doing the above seems to clobber SPRG0 on the mvme2100. It |
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| 429 | * is probably a not so subtle hint that you do not want to use PPCBug |
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| 430 | * once RTEMS is up and running. Anyway, we still needs to indicate |
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| 431 | * that we have fixed PR288. Eventually, this should go away. |
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| 432 | */ |
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| 433 | _write_SPRG0(PPC_BSP_HAS_FIXED_PR288); |
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[6128a4a] | 434 | #endif |
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[acc25ee] | 435 | |
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[e79a1947] | 436 | BSP_mem_size = residualCopy.TotalMemory; |
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| 437 | BSP_bus_frequency = residualCopy.VitalProductData.ProcessorBusHz; |
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| 438 | BSP_processor_frequency = residualCopy.VitalProductData.ProcessorHz; |
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| 439 | BSP_time_base_divisor = (residualCopy.VitalProductData.TimeBaseDivisor? |
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| 440 | residualCopy.VitalProductData.TimeBaseDivisor : 4000); |
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[4f3e4f33] | 441 | |
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[674b9497] | 442 | /* clear hostbridge errors but leave MCP disabled - |
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| 443 | * PCI config space scanning code will trip otherwise :-( |
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| 444 | */ |
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| 445 | _BSP_clear_hostbridge_errors(0 /* enableMCP */, 0/*quiet*/); |
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[14ec2d4] | 446 | |
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[4f3e4f33] | 447 | /* Allocate and set up the page table mappings |
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| 448 | * This is only available on >604 CPUs. |
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| 449 | * |
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| 450 | * NOTE: This setup routine may modify the available memory |
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| 451 | * size. It is essential to call it before |
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| 452 | * calculating the workspace etc. |
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| 453 | */ |
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| 454 | pt = BSP_pgtbl_setup(&BSP_mem_size); |
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| 455 | |
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[e79a1947] | 456 | if (!pt || TRIV121_MAP_SUCCESS != triv121PgTblMap( |
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| 457 | pt, TRIV121_121_VSID, 0xfeff0000, 1, |
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| 458 | TRIV121_ATTR_IO_PAGE, TRIV121_PP_RW_PAGE)) { |
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| 459 | printk("WARNING: unable to setup page tables VME " |
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| 460 | "bridge must share PCI space\n"); |
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[4f3e4f33] | 461 | } |
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[6128a4a] | 462 | |
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[acc25ee] | 463 | /* |
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| 464 | * Set up our hooks |
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| 465 | * Make sure libc_init is done before drivers initialized so that |
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| 466 | * they can use atexit() |
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| 467 | */ |
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| 468 | |
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[df49c60] | 469 | Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */ |
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| 470 | Cpu_table.postdriver_hook = bsp_postdriver_hook; |
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| 471 | Cpu_table.do_zero_of_workspace = TRUE; |
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| 472 | Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY; |
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| 473 | Cpu_table.clicks_per_usec = BSP_processor_frequency/(BSP_time_base_divisor * 1000); |
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| 474 | Cpu_table.exceptions_in_RAM = TRUE; |
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[acc25ee] | 475 | |
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| 476 | #ifdef SHOW_MORE_INIT_SETTINGS |
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[e79a1947] | 477 | printk("BSP_Configuration.work_space_size = %x\n", |
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| 478 | BSP_Configuration.work_space_size); |
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[6128a4a] | 479 | #endif |
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[e79a1947] | 480 | |
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[6128a4a] | 481 | work_space_start = |
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[acc25ee] | 482 | (unsigned char *)BSP_mem_size - BSP_Configuration.work_space_size; |
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| 483 | |
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[e79a1947] | 484 | if ( work_space_start <= |
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| 485 | ((unsigned char *)__rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE) { |
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[acc25ee] | 486 | printk( "bspstart: Not enough RAM!!!\n" ); |
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| 487 | bsp_cleanup(); |
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| 488 | } |
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| 489 | |
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| 490 | BSP_Configuration.work_space_start = work_space_start; |
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| 491 | |
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| 492 | /* |
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| 493 | * Initalize RTEMS IRQ system |
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| 494 | */ |
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| 495 | BSP_rtems_irq_mng_init(0); |
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[4f3e4f33] | 496 | |
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| 497 | /* Activate the page table mappings only after |
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| 498 | * initializing interrupts because the irq_mng_init() |
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| 499 | * routine needs to modify the text |
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[6128a4a] | 500 | */ |
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[4f3e4f33] | 501 | if (pt) { |
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| 502 | #ifdef SHOW_MORE_INIT_SETTINGS |
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| 503 | printk("Page table setup finished; will activate it NOW...\n"); |
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| 504 | #endif |
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| 505 | BSP_pgtbl_activate(pt); |
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[e79a1947] | 506 | #if !defined(mvme2100) |
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| 507 | /* finally, switch off DBAT3 */ |
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| 508 | setdbat(3, 0, 0, 0, 0); |
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| 509 | #endif |
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[4f3e4f33] | 510 | } |
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| 511 | |
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| 512 | /* |
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[e79a1947] | 513 | * Initialize VME bridge - needs working PCI and IRQ subsystems... |
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[4f3e4f33] | 514 | */ |
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| 515 | #ifdef SHOW_MORE_INIT_SETTINGS |
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| 516 | printk("Going to initialize VME bridge\n"); |
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| 517 | #endif |
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[e79a1947] | 518 | /* |
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| 519 | * VME initialization is in a separate file so apps which don't use VME or |
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| 520 | * want a different configuration may link against a customized routine. |
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[4f3e4f33] | 521 | */ |
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| 522 | BSP_vme_config(); |
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| 523 | |
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[e79a1947] | 524 | #if defined(DEBUG_BATS) |
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| 525 | ShowBATS(); |
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| 526 | #endif |
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| 527 | |
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[acc25ee] | 528 | #ifdef SHOW_MORE_INIT_SETTINGS |
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| 529 | printk("Exit from bspstart\n"); |
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[6128a4a] | 530 | #endif |
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[acc25ee] | 531 | } |
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