1 | /* |
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2 | * start.S : RTEMS entry point |
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3 | * |
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4 | * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr |
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5 | * |
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6 | * The license and distribution terms for this file may be |
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7 | * found in found in the file LICENSE in this distribution or at |
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8 | * http://www.OARcorp.com/rtems/license.html. |
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9 | * |
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10 | * $Id$ |
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11 | * |
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12 | */ |
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13 | |
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14 | #include <libcpu/cpu.h> |
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15 | #include <libcpu/io.h> |
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16 | #include <asm.h> /* for targopts.h and PPC_HAS_FPU */ |
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17 | #include <rtems/score/cpu.h> /* for CPU_MINIMUM_STACK_FRAME_SIZE */ |
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18 | |
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19 | #define SYNC \ |
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20 | sync; \ |
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21 | isync |
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22 | |
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23 | #define KERNELBASE 0x0 |
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24 | |
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25 | #define MONITOR_ENTER \ |
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26 | mfmsr r10 ; \ |
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27 | ori r10,r10,MSR_IP ; \ |
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28 | mtmsr r10 ; \ |
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29 | li r10,0x63 ; \ |
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30 | sc |
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31 | |
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32 | .text |
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33 | .globl __rtems_entry_point |
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34 | .type __rtems_entry_point,@function |
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35 | __rtems_entry_point: |
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36 | #ifdef DEBUG_EARLY_START |
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37 | MONITOR_ENTER |
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38 | #endif |
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39 | |
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40 | /* |
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41 | * PREP |
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42 | * This is jumped to on prep systems right after the kernel is relocated |
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43 | * to its proper place in memory by the boot loader. The expected layout |
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44 | * of the regs is: |
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45 | * r3: ptr to residual data |
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46 | * r4: initrd_start or if no initrd then 0 |
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47 | * r5: initrd_end - unused if r4 is 0 |
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48 | * r6: Start of command line string |
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49 | * r7: End of command line string |
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50 | * |
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51 | * The Prep boot loader insure that the MMU is currently off... |
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52 | * |
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53 | */ |
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54 | |
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55 | mr r31,r3 /* save parameters */ |
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56 | mr r30,r4 |
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57 | mr r29,r5 |
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58 | mr r28,r6 |
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59 | mr r27,r7 |
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60 | /* |
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61 | * Make sure we have nothing in BATS and TLB |
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62 | */ |
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63 | bl clear_bats |
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64 | bl flush_tlbs |
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65 | /* |
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66 | * Use the first pair of BAT registers to map the 1st 64MB |
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67 | * of RAM to KERNELBASE. |
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68 | */ |
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69 | lis r11,KERNELBASE@h |
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70 | ori r11,r11,0x7fe /* set up BAT registers for 604 */ |
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71 | li r8,2 /* R/W access */ |
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72 | isync |
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73 | mtspr DBAT0L,r8 /* N.B. 6xx (not 601) have valid */ |
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74 | mtspr DBAT0U,r11 /* bit in upper BAT register */ |
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75 | mtspr IBAT0L,r8 |
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76 | mtspr IBAT0U,r11 |
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77 | isync |
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78 | |
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79 | /* |
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80 | * we now have the 1st 64M of ram mapped with the bats. We are still |
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81 | * running on the bootloader stack and cannot switch to an RTEMS allocated |
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82 | * init stack before copying the residual data that may have been set just after |
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83 | * rtems_end address. This bug has been experienced on MVME2304. Thank to |
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84 | * Till Straumann <strauman@SLAC.Stanford.EDU> for hunting it and suggesting |
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85 | * the appropriate code. |
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86 | */ |
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87 | |
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88 | enter_C_code: |
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89 | bl MMUon |
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90 | bl zero_bss |
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91 | /* |
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92 | * restore prep boot params |
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93 | */ |
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94 | mr r3,r31 |
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95 | mr r4,r30 |
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96 | mr r5,r29 |
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97 | mr r6,r28 |
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98 | mr r7,r27 |
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99 | bl save_boot_params |
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100 | /* |
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101 | * stack = &__rtems_end + 4096 |
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102 | */ |
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103 | addis r9,r0, __rtems_end+(4096-CPU_MINIMUM_STACK_FRAME_SIZE)@ha |
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104 | addi r9,r9, __rtems_end+(4096-CPU_MINIMUM_STACK_FRAME_SIZE)@l |
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105 | mr r1, r9 |
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106 | /* |
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107 | * We are know in a environment that is totally independent from bootloader setup. |
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108 | */ |
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109 | lis r5,environ@ha |
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110 | la r5,environ@l(r5) /* environp */ |
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111 | li r4, 0 /* argv */ |
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112 | li r3, 0 /* argc */ |
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113 | bl boot_card |
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114 | bl _return_to_ppcbug |
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115 | |
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116 | .globl MMUon |
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117 | .type MMUon,@function |
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118 | MMUon: |
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119 | mfmsr r0 |
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120 | #if (PPC_HAS_FPU == 0) |
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121 | ori r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP |
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122 | xori r0, r0, MSR_EE | MSR_IP | MSR_FP |
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123 | #else |
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124 | ori r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP |
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125 | xori r0, r0, MSR_EE | MSR_IP | MSR_FE0 | MSR_FE1 |
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126 | #endif |
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127 | mflr r11 |
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128 | mtsrr0 r11 |
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129 | mtsrr1 r0 |
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130 | SYNC |
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131 | rfi |
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132 | |
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133 | .globl MMUoff |
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134 | .type MMUoff,@function |
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135 | MMUoff: |
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136 | mfmsr r0 |
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137 | ori r0,r0,MSR_IR| MSR_DR | MSR_IP |
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138 | mflr r11 |
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139 | xori r0,r0,MSR_IR|MSR_DR |
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140 | mtsrr0 r11 |
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141 | mtsrr1 r0 |
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142 | SYNC |
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143 | rfi |
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144 | |
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145 | .globl _return_to_ppcbug |
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146 | .type _return_to_ppcbug,@function |
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147 | |
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148 | |
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149 | _return_to_ppcbug: |
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150 | mflr r30 |
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151 | bl MMUoff |
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152 | MONITOR_ENTER |
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153 | bl MMUon |
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154 | mtctr r30 |
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155 | bctr |
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156 | |
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157 | /* |
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158 | * An undocumented "feature" of 604e requires that the v bit |
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159 | * be cleared before changing BAT values. |
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160 | * |
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161 | * Also, newer IBM firmware does not clear bat3 and 4 so |
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162 | * this makes sure it's done. |
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163 | * -- Cort |
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164 | */ |
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165 | clear_bats: |
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166 | li r20,0 |
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167 | mfspr r9,PVR |
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168 | rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */ |
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169 | cmpwi r9, 1 |
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170 | SYNC |
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171 | beq 1f |
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172 | mtspr DBAT0U,r20 |
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173 | mtspr DBAT0L,r20 |
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174 | mtspr DBAT1U,r20 |
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175 | mtspr DBAT1L,r20 |
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176 | mtspr DBAT2U,r20 |
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177 | mtspr DBAT2L,r20 |
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178 | mtspr DBAT3U,r20 |
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179 | mtspr DBAT3L,r20 |
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180 | 1: |
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181 | mtspr IBAT0U,r20 |
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182 | mtspr IBAT0L,r20 |
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183 | mtspr IBAT1U,r20 |
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184 | mtspr IBAT1L,r20 |
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185 | mtspr IBAT2U,r20 |
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186 | mtspr IBAT2L,r20 |
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187 | mtspr IBAT3U,r20 |
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188 | mtspr IBAT3L,r20 |
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189 | SYNC |
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190 | blr |
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191 | |
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192 | flush_tlbs: |
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193 | lis r20, 0x1000 |
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194 | 1: addic. r20, r20, -0x1000 |
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195 | tlbie r20 |
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196 | blt 1b |
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197 | sync |
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198 | blr |
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199 | |
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200 | |
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201 | .comm environ,4,4 |
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