1 | /* |
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2 | * pci.c : this file contains basic PCI Io functions. |
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3 | * |
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4 | * CopyRight (C) 1999 valette@crf.canon.fr |
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5 | * |
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6 | * This code is heavilly inspired by the public specification of STREAM V2 |
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7 | * that can be found at : |
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8 | * |
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9 | * <http://www.chorus.com/Documentation/index.html> by following |
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10 | * the STREAM API Specification Document link. |
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11 | * |
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12 | * The license and distribution terms for this file may be |
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13 | * found in found in the file LICENSE in this distribution or at |
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14 | * http://www.OARcorp.com/rtems/license.html. |
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15 | * |
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16 | * $Id$ |
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17 | */ |
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18 | |
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19 | #include <bsp/consoleIo.h> |
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20 | #include <libcpu/io.h> |
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21 | #include <bsp/pci.h> |
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22 | #include <bsp/residual.h> |
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23 | #include <bsp/openpic.h> |
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24 | #include <bsp.h> |
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25 | |
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26 | #define PCI_CONFIG_ADDR 0xcf8 |
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27 | #define PCI_CONFIG_DATA 0xcfc |
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28 | #define PCI_INVALID_VENDORDEVICEID 0xffffffff |
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29 | #define PCI_MULTI_FUNCTION 0x80 |
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30 | #define RAVEN_MPIC_IOSPACE_ENABLE 0x1 |
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31 | #define RAVEN_MPIC_MEMSPACE_ENABLE 0x2 |
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32 | #define RAVEN_MASTER_ENABLE 0x4 |
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33 | #define RAVEN_PARITY_CHECK_ENABLE 0x40 |
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34 | #define RAVEN_SYSTEM_ERROR_ENABLE 0x100 |
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35 | #define RAVEN_CLEAR_EVENTS_MASK 0xf9000000 |
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36 | |
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37 | |
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38 | /* |
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39 | * Bit encode for PCI_CONFIG_HEADER_TYPE register |
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40 | */ |
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41 | unsigned char ucMaxPCIBus; |
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42 | |
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43 | static int |
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44 | indirect_pci_read_config_byte(unsigned char bus, unsigned char slot, |
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45 | unsigned char function, |
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46 | unsigned char offset, unsigned char *val) { |
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47 | out_be32((unsigned int*) pci.pci_config_addr, |
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48 | 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24)); |
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49 | *val = in_8(pci.pci_config_data + (offset&3)); |
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50 | return PCIBIOS_SUCCESSFUL; |
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51 | } |
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52 | |
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53 | static int |
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54 | indirect_pci_read_config_word(unsigned char bus, unsigned char slot, |
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55 | unsigned char function, |
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56 | unsigned char offset, unsigned short *val) { |
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57 | *val = 0xffff; |
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58 | if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER; |
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59 | out_be32((unsigned int*) pci.pci_config_addr, |
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60 | 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24)); |
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61 | *val = in_le16((volatile unsigned short *)(pci.pci_config_data + (offset&3))); |
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62 | return PCIBIOS_SUCCESSFUL; |
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63 | } |
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64 | |
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65 | static int |
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66 | indirect_pci_read_config_dword(unsigned char bus, unsigned char slot, |
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67 | unsigned char function, |
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68 | unsigned char offset, unsigned int *val) { |
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69 | *val = 0xffffffff; |
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70 | if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER; |
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71 | out_be32((unsigned int*) pci.pci_config_addr, |
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72 | 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|(offset<<24)); |
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73 | *val = in_le32((volatile unsigned int *)pci.pci_config_data); |
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74 | return PCIBIOS_SUCCESSFUL; |
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75 | } |
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76 | |
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77 | static int |
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78 | indirect_pci_write_config_byte(unsigned char bus, unsigned char slot, |
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79 | unsigned char function, |
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80 | unsigned char offset, unsigned char val) { |
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81 | out_be32((unsigned int*) pci.pci_config_addr, |
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82 | 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24)); |
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83 | out_8(pci.pci_config_data + (offset&3), val); |
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84 | return PCIBIOS_SUCCESSFUL; |
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85 | } |
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86 | |
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87 | static int |
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88 | indirect_pci_write_config_word(unsigned char bus, unsigned char slot, |
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89 | unsigned char function, |
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90 | unsigned char offset, unsigned short val) { |
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91 | if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER; |
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92 | out_be32((unsigned int*) pci.pci_config_addr, |
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93 | 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24)); |
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94 | out_le16((volatile unsigned short *)(pci.pci_config_data + (offset&3)), val); |
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95 | return PCIBIOS_SUCCESSFUL; |
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96 | } |
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97 | |
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98 | static int |
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99 | indirect_pci_write_config_dword(unsigned char bus, unsigned char slot, |
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100 | unsigned char function, |
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101 | unsigned char offset, unsigned int val) { |
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102 | if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER; |
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103 | out_be32((unsigned int*) pci.pci_config_addr, |
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104 | 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|(offset<<24)); |
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105 | out_le32((volatile unsigned int *)pci.pci_config_data, val); |
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106 | return PCIBIOS_SUCCESSFUL; |
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107 | } |
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108 | |
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109 | static const pci_config_access_functions indirect_functions = { |
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110 | indirect_pci_read_config_byte, |
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111 | indirect_pci_read_config_word, |
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112 | indirect_pci_read_config_dword, |
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113 | indirect_pci_write_config_byte, |
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114 | indirect_pci_write_config_word, |
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115 | indirect_pci_write_config_dword |
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116 | }; |
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117 | |
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118 | pci_config pci = {(volatile unsigned char*)PCI_CONFIG_ADDR, |
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119 | (volatile unsigned char*)PCI_CONFIG_DATA, |
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120 | &indirect_functions}; |
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121 | |
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122 | static int |
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123 | direct_pci_read_config_byte(unsigned char bus, unsigned char slot, |
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124 | unsigned char function, |
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125 | unsigned char offset, unsigned char *val) { |
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126 | if (bus != 0 || (1<<slot & 0xff8007fe)) { |
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127 | *val=0xff; |
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128 | return PCIBIOS_DEVICE_NOT_FOUND; |
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129 | } |
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130 | *val=in_8(pci.pci_config_data + ((1<<slot)&~1) |
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131 | + (function<<8) + offset); |
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132 | return PCIBIOS_SUCCESSFUL; |
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133 | } |
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134 | |
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135 | static int |
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136 | direct_pci_read_config_word(unsigned char bus, unsigned char slot, |
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137 | unsigned char function, |
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138 | unsigned char offset, unsigned short *val) { |
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139 | *val = 0xffff; |
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140 | if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER; |
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141 | if (bus != 0 || (1<<slot & 0xff8007fe)) { |
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142 | return PCIBIOS_DEVICE_NOT_FOUND; |
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143 | } |
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144 | *val=in_le16((volatile unsigned short *) |
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145 | (pci.pci_config_data + ((1<<slot)&~1) |
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146 | + (function<<8) + offset)); |
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147 | return PCIBIOS_SUCCESSFUL; |
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148 | } |
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149 | |
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150 | static int |
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151 | direct_pci_read_config_dword(unsigned char bus, unsigned char slot, |
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152 | unsigned char function, |
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153 | unsigned char offset, unsigned int *val) { |
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154 | *val = 0xffffffff; |
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155 | if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER; |
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156 | if (bus != 0 || (1<<slot & 0xff8007fe)) { |
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157 | return PCIBIOS_DEVICE_NOT_FOUND; |
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158 | } |
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159 | *val=in_le32((volatile unsigned int *) |
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160 | (pci.pci_config_data + ((1<<slot)&~1) |
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161 | + (function<<8) + offset)); |
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162 | return PCIBIOS_SUCCESSFUL; |
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163 | } |
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164 | |
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165 | static int |
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166 | direct_pci_write_config_byte(unsigned char bus, unsigned char slot, |
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167 | unsigned char function, |
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168 | unsigned char offset, unsigned char val) { |
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169 | if (bus != 0 || (1<<slot & 0xff8007fe)) { |
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170 | return PCIBIOS_DEVICE_NOT_FOUND; |
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171 | } |
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172 | out_8(pci.pci_config_data + ((1<<slot)&~1) |
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173 | + (function<<8) + offset, |
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174 | val); |
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175 | return PCIBIOS_SUCCESSFUL; |
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176 | } |
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177 | |
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178 | static int |
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179 | direct_pci_write_config_word(unsigned char bus, unsigned char slot, |
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180 | unsigned char function, |
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181 | unsigned char offset, unsigned short val) { |
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182 | if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER; |
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183 | if (bus != 0 || (1<<slot & 0xff8007fe)) { |
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184 | return PCIBIOS_DEVICE_NOT_FOUND; |
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185 | } |
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186 | out_le16((volatile unsigned short *) |
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187 | (pci.pci_config_data + ((1<<slot)&~1) |
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188 | + (function<<8) + offset), |
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189 | val); |
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190 | return PCIBIOS_SUCCESSFUL; |
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191 | } |
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192 | |
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193 | static int |
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194 | direct_pci_write_config_dword(unsigned char bus, unsigned char slot, |
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195 | unsigned char function, |
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196 | unsigned char offset, unsigned int val) { |
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197 | if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER; |
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198 | if (bus != 0 || (1<<slot & 0xff8007fe)) { |
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199 | return PCIBIOS_DEVICE_NOT_FOUND; |
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200 | } |
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201 | out_le32((volatile unsigned int *) |
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202 | (pci.pci_config_data + ((1<<slot)&~1) |
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203 | + (function<<8) + offset), |
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204 | val); |
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205 | return PCIBIOS_SUCCESSFUL; |
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206 | } |
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207 | |
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208 | static const pci_config_access_functions direct_functions = { |
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209 | direct_pci_read_config_byte, |
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210 | direct_pci_read_config_word, |
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211 | direct_pci_read_config_dword, |
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212 | direct_pci_write_config_byte, |
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213 | direct_pci_write_config_word, |
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214 | direct_pci_write_config_dword |
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215 | }; |
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216 | |
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217 | |
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218 | void detect_host_bridge() |
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219 | { |
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220 | PPC_DEVICE *hostbridge; |
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221 | unsigned int id0; |
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222 | unsigned int tmp; |
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223 | |
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224 | /* |
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225 | * This code assumes that the host bridge is located at |
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226 | * bus 0, dev 0, func 0 AND that the old pre PCI 2.1 |
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227 | * standart devices detection mecahnism that was used on PC |
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228 | * (still used in BSD source code) works. |
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229 | */ |
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230 | hostbridge=residual_find_device(&residualCopy, PROCESSORDEVICE, NULL, |
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231 | BridgeController, |
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232 | PCIBridge, -1, 0); |
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233 | if (hostbridge) { |
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234 | if (hostbridge->DeviceId.Interface==PCIBridgeIndirect) { |
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235 | pci.pci_functions=&indirect_functions; |
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236 | /* Should be extracted from residual data, |
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237 | * indeed MPC106 in CHRP mode is different, |
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238 | * but we should not use residual data in |
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239 | * this case anyway. |
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240 | */ |
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241 | pci.pci_config_addr = ((volatile unsigned char *) |
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242 | (ptr_mem_map->io_base+0xcf8)); |
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243 | pci.pci_config_data = ptr_mem_map->io_base+0xcfc; |
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244 | } else if(hostbridge->DeviceId.Interface==PCIBridgeDirect) { |
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245 | pci.pci_functions=&direct_functions; |
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246 | pci.pci_config_data=(unsigned char *) 0x80800000; |
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247 | } else { |
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248 | } |
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249 | } else { |
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250 | /* Let us try by experimentation at our own risk! */ |
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251 | pci.pci_functions = &direct_functions; |
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252 | /* On all direct bridges I know the host bridge itself |
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253 | * appears as device 0 function 0. |
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254 | */ |
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255 | pci_read_config_dword(0, 0, 0, PCI_VENDOR_ID, &id0); |
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256 | if (id0==~0U) { |
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257 | pci.pci_functions = &indirect_functions; |
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258 | pci.pci_config_addr = ((volatile unsigned char*) |
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259 | (ptr_mem_map->io_base+0xcf8)); |
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260 | pci.pci_config_data = ((volatile unsigned char*)ptr_mem_map->io_base+0xcfc); |
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261 | } |
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262 | /* Here we should check that the host bridge is actually |
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263 | * present, but if it not, we are in such a desperate |
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264 | * situation, that we probably can't even tell it. |
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265 | */ |
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266 | } |
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267 | pci_read_config_dword(0, 0, 0, 0, &id0); |
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268 | if(id0 == PCI_VENDOR_ID_MOTOROLA + |
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269 | (PCI_DEVICE_ID_MOTOROLA_RAVEN<<16)) { |
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270 | /* |
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271 | * We have a Raven bridge. We will get information about its settings |
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272 | */ |
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273 | pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0); |
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274 | #ifdef SHOW_RAVEN_SETTING |
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275 | printk("RAVEN PCI command register = %x\n",id0); |
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276 | #endif |
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277 | id0 |= RAVEN_CLEAR_EVENTS_MASK; |
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278 | pci_write_config_dword(0, 0, 0, PCI_COMMAND, id0); |
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279 | pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0); |
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280 | #ifdef SHOW_RAVEN_SETTING |
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281 | printk("After error clearing RAVEN PCI command register = %x\n",id0); |
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282 | #endif |
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283 | |
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284 | if (id0 & RAVEN_MPIC_IOSPACE_ENABLE) { |
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285 | pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_0, &tmp); |
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286 | #ifdef SHOW_RAVEN_SETTING |
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287 | printk("Raven MPIC is accessed via IO Space Access at address : %x\n",(tmp & ~0x1)); |
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288 | #endif |
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289 | } |
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290 | if (id0 & RAVEN_MPIC_MEMSPACE_ENABLE) { |
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291 | pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_1, &tmp); |
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292 | #ifdef SHOW_RAVEN_SETTING |
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293 | printk("Raven MPIC is accessed via memory Space Access at address : %x\n", tmp); |
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294 | #endif |
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295 | OpenPIC=(volatile struct OpenPIC *) (tmp + PREP_ISA_MEM_BASE); |
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296 | printk("OpenPIC found at %p.\n", |
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297 | OpenPIC); |
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298 | } |
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299 | } |
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300 | if (OpenPIC == (volatile struct OpenPIC *)0) { |
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301 | BSP_panic("OpenPic Not found\n"); |
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302 | } |
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303 | |
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304 | } |
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305 | |
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306 | /* |
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307 | * This routine determines the maximum bus number in the system |
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308 | */ |
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309 | void InitializePCI() |
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310 | { |
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311 | unsigned char ucSlotNumber, ucFnNumber, ucNumFuncs; |
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312 | unsigned char ucHeader; |
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313 | unsigned char ucMaxSubordinate; |
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314 | unsigned int ulClass, ulDeviceID; |
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315 | |
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316 | detect_host_bridge(); |
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317 | /* |
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318 | * Scan PCI bus 0 looking for PCI-PCI bridges |
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319 | */ |
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320 | for(ucSlotNumber=0;ucSlotNumber<PCI_MAX_DEVICES;ucSlotNumber++) { |
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321 | (void)pci_read_config_dword(0, |
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322 | ucSlotNumber, |
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323 | 0, |
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324 | PCI_VENDOR_ID, |
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325 | &ulDeviceID); |
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326 | if(ulDeviceID==PCI_INVALID_VENDORDEVICEID) { |
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327 | /* |
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328 | * This slot is empty |
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329 | */ |
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330 | continue; |
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331 | } |
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332 | (void)pci_read_config_byte(0, |
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333 | ucSlotNumber, |
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334 | 0, |
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335 | PCI_HEADER_TYPE, |
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336 | &ucHeader); |
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337 | if(ucHeader&PCI_MULTI_FUNCTION) { |
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338 | ucNumFuncs=PCI_MAX_FUNCTIONS; |
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339 | } |
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340 | else { |
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341 | ucNumFuncs=1; |
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342 | } |
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343 | for(ucFnNumber=0;ucFnNumber<ucNumFuncs;ucFnNumber++) { |
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344 | (void)pci_read_config_dword(0, |
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345 | ucSlotNumber, |
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346 | ucFnNumber, |
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347 | PCI_VENDOR_ID, |
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348 | &ulDeviceID); |
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349 | if(ulDeviceID==PCI_INVALID_VENDORDEVICEID) { |
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350 | /* |
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351 | * This slot/function is empty |
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352 | */ |
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353 | continue; |
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354 | } |
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355 | |
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356 | /* |
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357 | * This slot/function has a device fitted. |
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358 | */ |
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359 | (void)pci_read_config_dword(0, |
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360 | ucSlotNumber, |
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361 | ucFnNumber, |
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362 | PCI_CLASS_REVISION, |
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363 | &ulClass); |
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364 | ulClass >>= 16; |
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365 | if (ulClass == PCI_CLASS_BRIDGE_PCI) { |
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366 | /* |
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367 | * We have found a PCI-PCI bridge |
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368 | */ |
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369 | (void)pci_read_config_byte(0, |
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370 | ucSlotNumber, |
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371 | ucFnNumber, |
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372 | PCI_SUBORDINATE_BUS, |
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373 | &ucMaxSubordinate); |
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374 | if(ucMaxSubordinate>ucMaxPCIBus) { |
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375 | ucMaxPCIBus=ucMaxSubordinate; |
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376 | } |
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377 | } |
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378 | } |
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379 | } |
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380 | } |
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381 | |
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382 | /* |
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383 | * Return the number of PCI busses in the system |
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384 | */ |
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385 | unsigned char BusCountPCI() |
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386 | { |
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387 | return(ucMaxPCIBus+1); |
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388 | } |
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