[acc25ee] | 1 | /* |
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| 2 | * pci.c : this file contains basic PCI Io functions. |
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| 3 | * |
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[e79a1947] | 4 | * Copyright (C) 1999 valette@crf.canon.fr |
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[acc25ee] | 5 | * |
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[e79a1947] | 6 | * This code is heavily inspired by the public specification of STREAM V2 |
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[acc25ee] | 7 | * that can be found at : |
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| 8 | * |
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| 9 | * <http://www.chorus.com/Documentation/index.html> by following |
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| 10 | * the STREAM API Specification Document link. |
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| 11 | * |
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| 12 | * The license and distribution terms for this file may be |
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| 13 | * found in found in the file LICENSE in this distribution or at |
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[e831de8] | 14 | * http://www.rtems.com/license/LICENSE. |
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[acc25ee] | 15 | * |
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| 16 | * $Id$ |
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[69ed59f] | 17 | * |
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| 18 | * Till Straumann, <strauman@slac.stanford.edu>, 1/2002 |
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| 19 | * - separated bridge detection code out of this file |
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[acc25ee] | 20 | */ |
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| 21 | |
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| 22 | #include <libcpu/io.h> |
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| 23 | #include <bsp/pci.h> |
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[e79a1947] | 24 | #include <rtems/bspIo.h> |
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[acc25ee] | 25 | |
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[69ed59f] | 26 | /* allow for overriding these definitions */ |
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| 27 | #ifndef PCI_CONFIG_ADDR |
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[acc25ee] | 28 | #define PCI_CONFIG_ADDR 0xcf8 |
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[69ed59f] | 29 | #endif |
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| 30 | #ifndef PCI_CONFIG_DATA |
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[acc25ee] | 31 | #define PCI_CONFIG_DATA 0xcfc |
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[69ed59f] | 32 | #endif |
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| 33 | |
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[acc25ee] | 34 | #define PCI_INVALID_VENDORDEVICEID 0xffffffff |
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| 35 | #define PCI_MULTI_FUNCTION 0x80 |
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| 36 | |
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[69ed59f] | 37 | /* define a shortcut */ |
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| 38 | #define pci BSP_pci_configuration |
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[acc25ee] | 39 | |
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| 40 | /* |
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| 41 | * Bit encode for PCI_CONFIG_HEADER_TYPE register |
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| 42 | */ |
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| 43 | unsigned char ucMaxPCIBus; |
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| 44 | |
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| 45 | static int |
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| 46 | indirect_pci_read_config_byte(unsigned char bus, unsigned char slot, |
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[6128a4a] | 47 | unsigned char function, |
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[acc25ee] | 48 | unsigned char offset, unsigned char *val) { |
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[6128a4a] | 49 | out_be32((unsigned int*) pci.pci_config_addr, |
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[acc25ee] | 50 | 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24)); |
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| 51 | *val = in_8(pci.pci_config_data + (offset&3)); |
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| 52 | return PCIBIOS_SUCCESSFUL; |
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| 53 | } |
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| 54 | |
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| 55 | static int |
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| 56 | indirect_pci_read_config_word(unsigned char bus, unsigned char slot, |
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[6128a4a] | 57 | unsigned char function, |
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[acc25ee] | 58 | unsigned char offset, unsigned short *val) { |
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[6128a4a] | 59 | *val = 0xffff; |
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[acc25ee] | 60 | if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER; |
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[6128a4a] | 61 | out_be32((unsigned int*) pci.pci_config_addr, |
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[acc25ee] | 62 | 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24)); |
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| 63 | *val = in_le16((volatile unsigned short *)(pci.pci_config_data + (offset&3))); |
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| 64 | return PCIBIOS_SUCCESSFUL; |
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| 65 | } |
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| 66 | |
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| 67 | static int |
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| 68 | indirect_pci_read_config_dword(unsigned char bus, unsigned char slot, |
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[6128a4a] | 69 | unsigned char function, |
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[acc25ee] | 70 | unsigned char offset, unsigned int *val) { |
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[6128a4a] | 71 | *val = 0xffffffff; |
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[acc25ee] | 72 | if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER; |
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[6128a4a] | 73 | out_be32((unsigned int*) pci.pci_config_addr, |
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[acc25ee] | 74 | 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|(offset<<24)); |
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| 75 | *val = in_le32((volatile unsigned int *)pci.pci_config_data); |
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| 76 | return PCIBIOS_SUCCESSFUL; |
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| 77 | } |
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| 78 | |
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| 79 | static int |
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| 80 | indirect_pci_write_config_byte(unsigned char bus, unsigned char slot, |
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[6128a4a] | 81 | unsigned char function, |
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[acc25ee] | 82 | unsigned char offset, unsigned char val) { |
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[6128a4a] | 83 | out_be32((unsigned int*) pci.pci_config_addr, |
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[acc25ee] | 84 | 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24)); |
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| 85 | out_8(pci.pci_config_data + (offset&3), val); |
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| 86 | return PCIBIOS_SUCCESSFUL; |
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| 87 | } |
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| 88 | |
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| 89 | static int |
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| 90 | indirect_pci_write_config_word(unsigned char bus, unsigned char slot, |
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[6128a4a] | 91 | unsigned char function, |
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[acc25ee] | 92 | unsigned char offset, unsigned short val) { |
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| 93 | if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER; |
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[6128a4a] | 94 | out_be32((unsigned int*) pci.pci_config_addr, |
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[acc25ee] | 95 | 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24)); |
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| 96 | out_le16((volatile unsigned short *)(pci.pci_config_data + (offset&3)), val); |
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| 97 | return PCIBIOS_SUCCESSFUL; |
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| 98 | } |
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| 99 | |
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| 100 | static int |
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| 101 | indirect_pci_write_config_dword(unsigned char bus, unsigned char slot, |
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[6128a4a] | 102 | unsigned char function, |
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[acc25ee] | 103 | unsigned char offset, unsigned int val) { |
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| 104 | if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER; |
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[6128a4a] | 105 | out_be32((unsigned int*) pci.pci_config_addr, |
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[acc25ee] | 106 | 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|(offset<<24)); |
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| 107 | out_le32((volatile unsigned int *)pci.pci_config_data, val); |
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| 108 | return PCIBIOS_SUCCESSFUL; |
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| 109 | } |
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| 110 | |
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[69ed59f] | 111 | const pci_config_access_functions pci_indirect_functions = { |
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[acc25ee] | 112 | indirect_pci_read_config_byte, |
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| 113 | indirect_pci_read_config_word, |
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| 114 | indirect_pci_read_config_dword, |
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| 115 | indirect_pci_write_config_byte, |
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| 116 | indirect_pci_write_config_word, |
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| 117 | indirect_pci_write_config_dword |
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| 118 | }; |
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| 119 | |
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[69ed59f] | 120 | pci_config BSP_pci_configuration = {(volatile unsigned char*)PCI_CONFIG_ADDR, |
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[acc25ee] | 121 | (volatile unsigned char*)PCI_CONFIG_DATA, |
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[69ed59f] | 122 | &pci_indirect_functions}; |
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[acc25ee] | 123 | |
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| 124 | static int |
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| 125 | direct_pci_read_config_byte(unsigned char bus, unsigned char slot, |
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[6128a4a] | 126 | unsigned char function, |
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[acc25ee] | 127 | unsigned char offset, unsigned char *val) { |
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| 128 | if (bus != 0 || (1<<slot & 0xff8007fe)) { |
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| 129 | *val=0xff; |
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| 130 | return PCIBIOS_DEVICE_NOT_FOUND; |
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| 131 | } |
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[6128a4a] | 132 | *val=in_8(pci.pci_config_data + ((1<<slot)&~1) |
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[acc25ee] | 133 | + (function<<8) + offset); |
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| 134 | return PCIBIOS_SUCCESSFUL; |
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| 135 | } |
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| 136 | |
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| 137 | static int |
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| 138 | direct_pci_read_config_word(unsigned char bus, unsigned char slot, |
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[6128a4a] | 139 | unsigned char function, |
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[acc25ee] | 140 | unsigned char offset, unsigned short *val) { |
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[6128a4a] | 141 | *val = 0xffff; |
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[acc25ee] | 142 | if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER; |
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| 143 | if (bus != 0 || (1<<slot & 0xff8007fe)) { |
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| 144 | return PCIBIOS_DEVICE_NOT_FOUND; |
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| 145 | } |
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| 146 | *val=in_le16((volatile unsigned short *) |
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| 147 | (pci.pci_config_data + ((1<<slot)&~1) |
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| 148 | + (function<<8) + offset)); |
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| 149 | return PCIBIOS_SUCCESSFUL; |
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| 150 | } |
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| 151 | |
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| 152 | static int |
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| 153 | direct_pci_read_config_dword(unsigned char bus, unsigned char slot, |
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[6128a4a] | 154 | unsigned char function, |
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[acc25ee] | 155 | unsigned char offset, unsigned int *val) { |
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[6128a4a] | 156 | *val = 0xffffffff; |
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[acc25ee] | 157 | if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER; |
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| 158 | if (bus != 0 || (1<<slot & 0xff8007fe)) { |
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| 159 | return PCIBIOS_DEVICE_NOT_FOUND; |
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| 160 | } |
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| 161 | *val=in_le32((volatile unsigned int *) |
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| 162 | (pci.pci_config_data + ((1<<slot)&~1) |
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| 163 | + (function<<8) + offset)); |
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| 164 | return PCIBIOS_SUCCESSFUL; |
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| 165 | } |
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| 166 | |
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| 167 | static int |
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| 168 | direct_pci_write_config_byte(unsigned char bus, unsigned char slot, |
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[6128a4a] | 169 | unsigned char function, |
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[acc25ee] | 170 | unsigned char offset, unsigned char val) { |
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| 171 | if (bus != 0 || (1<<slot & 0xff8007fe)) { |
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| 172 | return PCIBIOS_DEVICE_NOT_FOUND; |
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| 173 | } |
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[6128a4a] | 174 | out_8(pci.pci_config_data + ((1<<slot)&~1) |
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| 175 | + (function<<8) + offset, |
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[acc25ee] | 176 | val); |
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| 177 | return PCIBIOS_SUCCESSFUL; |
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| 178 | } |
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| 179 | |
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| 180 | static int |
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| 181 | direct_pci_write_config_word(unsigned char bus, unsigned char slot, |
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[6128a4a] | 182 | unsigned char function, |
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[acc25ee] | 183 | unsigned char offset, unsigned short val) { |
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| 184 | if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER; |
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| 185 | if (bus != 0 || (1<<slot & 0xff8007fe)) { |
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| 186 | return PCIBIOS_DEVICE_NOT_FOUND; |
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| 187 | } |
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| 188 | out_le16((volatile unsigned short *) |
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| 189 | (pci.pci_config_data + ((1<<slot)&~1) |
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| 190 | + (function<<8) + offset), |
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| 191 | val); |
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| 192 | return PCIBIOS_SUCCESSFUL; |
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| 193 | } |
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| 194 | |
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| 195 | static int |
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| 196 | direct_pci_write_config_dword(unsigned char bus, unsigned char slot, |
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[6128a4a] | 197 | unsigned char function, |
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[acc25ee] | 198 | unsigned char offset, unsigned int val) { |
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| 199 | if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER; |
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| 200 | if (bus != 0 || (1<<slot & 0xff8007fe)) { |
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| 201 | return PCIBIOS_DEVICE_NOT_FOUND; |
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| 202 | } |
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| 203 | out_le32((volatile unsigned int *) |
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| 204 | (pci.pci_config_data + ((1<<slot)&~1) |
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| 205 | + (function<<8) + offset), |
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| 206 | val); |
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| 207 | return PCIBIOS_SUCCESSFUL; |
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| 208 | } |
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| 209 | |
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[69ed59f] | 210 | const pci_config_access_functions pci_direct_functions = { |
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[acc25ee] | 211 | direct_pci_read_config_byte, |
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| 212 | direct_pci_read_config_word, |
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| 213 | direct_pci_read_config_dword, |
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| 214 | direct_pci_write_config_byte, |
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| 215 | direct_pci_write_config_word, |
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| 216 | direct_pci_write_config_dword |
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| 217 | }; |
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| 218 | |
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[3a3e0b0e] | 219 | #define PRINT_MSG() \ |
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| 220 | printk("pci : Device %d:%02x routed to interrupt_line %d\n", pbus, pslot, int_name ) |
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| 221 | |
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[6128a4a] | 222 | /* |
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[3a3e0b0e] | 223 | ** Validate a test interrupt name and print a warning if its not one of |
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| 224 | ** the names defined in the routing record. |
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| 225 | */ |
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[da3b8d3] | 226 | static int test_intname( |
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[e79a1947] | 227 | const struct _int_map *row, |
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| 228 | int pbus, |
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| 229 | int pslot, |
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| 230 | int int_pin, |
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| 231 | int int_name |
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| 232 | ) |
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[3a3e0b0e] | 233 | { |
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[e79a1947] | 234 | int j, k; |
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[3a3e0b0e] | 235 | int _nopin= -1, _noname= -1; |
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| 236 | |
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| 237 | for(j=0; row->pin_route[j].pin > -1; j++) |
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| 238 | { |
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[6128a4a] | 239 | if( row->pin_route[j].pin == int_pin ) |
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[3a3e0b0e] | 240 | { |
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| 241 | _nopin = 0; |
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[6128a4a] | 242 | |
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[3a3e0b0e] | 243 | for(k=0; k<4 && row->pin_route[j].int_name[k] > -1; k++ ) |
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| 244 | { |
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[6128a4a] | 245 | if( row->pin_route[j].int_name[k] == int_name ){ _noname=0; break; } |
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[3a3e0b0e] | 246 | } |
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| 247 | break; |
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| 248 | } |
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| 249 | } |
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| 250 | |
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[6128a4a] | 251 | if( _nopin ) |
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[3a3e0b0e] | 252 | { |
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| 253 | printk("pci : Device %d:%02x supplied a bogus interrupt_pin %d\n", pbus, pslot, int_pin ); |
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| 254 | return -1; |
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| 255 | } |
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| 256 | else |
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| 257 | { |
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| 258 | if( _noname ) |
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| 259 | printk("pci : Device %d:%02x supplied a suspicious interrupt_line %d, using it anyway\n", pbus, pslot, int_name ); |
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| 260 | } |
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| 261 | return 0; |
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| 262 | } |
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| 263 | |
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| 264 | struct pcibridge |
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| 265 | { |
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| 266 | int bus,slot; |
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| 267 | }; |
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| 268 | |
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| 269 | static int FindPCIbridge( int mybus, struct pcibridge *pb ) |
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| 270 | { |
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| 271 | int pbus, pslot; |
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[bde7f268] | 272 | uint8_t bussec, buspri; |
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| 273 | uint16_t devid, vendorid, dclass; |
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[3a3e0b0e] | 274 | |
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| 275 | for(pbus=0; pbus< BusCountPCI(); pbus++) |
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| 276 | { |
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| 277 | for(pslot=0; pslot< PCI_MAX_DEVICES; pslot++) |
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[6128a4a] | 278 | { |
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[3a3e0b0e] | 279 | pci_read_config_word(pbus, pslot, 0, PCI_DEVICE_ID, &devid); |
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| 280 | if( devid == 0xffff ) continue; |
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| 281 | |
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| 282 | pci_read_config_word(pbus, pslot, 0, PCI_DEVICE_ID, &vendorid); |
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| 283 | if( vendorid == 0xffff ) continue; |
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| 284 | |
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| 285 | pci_read_config_word(pbus, pslot, 0, PCI_CLASS_DEVICE, &dclass); |
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| 286 | |
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[6128a4a] | 287 | if( dclass == PCI_CLASS_BRIDGE_PCI ) |
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[3a3e0b0e] | 288 | { |
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| 289 | pci_read_config_byte(pbus, pslot, 0, PCI_PRIMARY_BUS, &buspri); |
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| 290 | pci_read_config_byte(pbus, pslot, 0, PCI_SECONDARY_BUS, &bussec); |
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| 291 | |
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| 292 | #if 0 |
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| 293 | printk("pci : Found bridge at %d:%d, mybus %d, pribus %d, secbus %d ", pbus, pslot, mybus, buspri, bussec ); |
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| 294 | #endif |
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| 295 | if( bussec == mybus ) |
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| 296 | { |
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| 297 | #if 0 |
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| 298 | printk("match\n"); |
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| 299 | #endif |
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| 300 | /* found our nearest bridge going towards the root */ |
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| 301 | pb->bus = pbus; |
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| 302 | pb->slot = pslot; |
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| 303 | |
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| 304 | return 0; |
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| 305 | } |
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| 306 | #if 0 |
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| 307 | printk("no match\n"); |
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| 308 | #endif |
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| 309 | } |
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| 310 | |
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| 311 | } |
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| 312 | } |
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| 313 | return -1; |
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| 314 | } |
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| 315 | |
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[da3b8d3] | 316 | void FixupPCI( const struct _int_map *bspmap, int (*swizzler)(int,int) ) |
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[3a3e0b0e] | 317 | { |
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| 318 | unsigned char cvalue; |
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[bde7f268] | 319 | uint16_t devid; |
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[3a3e0b0e] | 320 | int ismatch, i, j, pbus, pslot, int_pin, int_name; |
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| 321 | |
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| 322 | /* |
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| 323 | ** If the device has a non-zero INTERRUPT_PIN, assign a bsp-specific |
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| 324 | ** INTERRUPT_NAME if one isn't already in place. Then, drivers can |
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| 325 | ** trivially use INTERRUPT_NAME to hook up with devices. |
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| 326 | */ |
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| 327 | |
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| 328 | for(pbus=0; pbus< BusCountPCI(); pbus++) |
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| 329 | { |
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| 330 | for(pslot=0; pslot< PCI_MAX_DEVICES; pslot++) |
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[6128a4a] | 331 | { |
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[3a3e0b0e] | 332 | pci_read_config_word(pbus, pslot, 0, PCI_DEVICE_ID, &devid); |
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| 333 | if( devid == 0xffff ) continue; |
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| 334 | |
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| 335 | /* got a device */ |
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| 336 | |
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| 337 | pci_read_config_byte( pbus, pslot, 0, PCI_INTERRUPT_PIN, &cvalue); |
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| 338 | int_pin = cvalue; |
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| 339 | |
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| 340 | pci_read_config_byte( pbus, pslot, 0, PCI_INTERRUPT_LINE, &cvalue); |
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| 341 | int_name = cvalue; |
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| 342 | |
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| 343 | /* printk("pci : device %d:%02x devid %04x, intpin %d, intline %d\n", pbus, pslot, devid, int_pin, int_name ); */ |
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| 344 | |
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[513b6c4b] | 345 | #if 0 |
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| 346 | { |
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| 347 | unsigned short cmd,stat; |
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| 348 | unsigned char lat, seclat, csize; |
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| 349 | |
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| 350 | pci_read_config_word(pbus,pslot,0,PCI_COMMAND, &cmd ); |
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| 351 | pci_read_config_word(pbus,pslot,0,PCI_STATUS, &stat ); |
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| 352 | pci_read_config_byte(pbus,pslot,0,PCI_LATENCY_TIMER, &lat ); |
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| 353 | pci_read_config_byte(pbus,pslot,0,PCI_SEC_LATENCY_TIMER, &seclat ); |
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| 354 | pci_read_config_byte(pbus,pslot,0,PCI_CACHE_LINE_SIZE, &csize ); |
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| 355 | |
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| 356 | |
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| 357 | printk("pci : device %d:%02x cmd %04X, stat %04X, latency %d, sec_latency %d, clsize %d\n", pbus, pslot, |
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| 358 | cmd, |
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| 359 | stat, |
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| 360 | lat, |
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| 361 | seclat, |
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| 362 | csize); |
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| 363 | } |
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| 364 | #endif |
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| 365 | |
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[3a3e0b0e] | 366 | if( int_pin > 0 ) |
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| 367 | { |
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| 368 | ismatch = 0; |
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| 369 | |
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| 370 | /* |
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| 371 | ** first run thru the bspmap table and see if we have an explicit configuration |
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| 372 | */ |
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| 373 | for(i=0; bspmap[i].bus > -1; i++) |
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| 374 | { |
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| 375 | if( bspmap[i].bus == pbus && bspmap[i].slot == pslot ) |
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| 376 | { |
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| 377 | ismatch = -1; |
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| 378 | /* we have a record in the table that gives specific |
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| 379 | * pins and interrupts for devices in this slot */ |
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| 380 | if( int_name == 255 ) |
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| 381 | { |
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| 382 | /* find the vector associated with whatever pin the device gives us */ |
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| 383 | for( int_name=-1, j=0; bspmap[i].pin_route[j].pin > -1; j++ ) |
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| 384 | { |
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| 385 | if( bspmap[i].pin_route[j].pin == int_pin ) |
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| 386 | { |
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| 387 | int_name = bspmap[i].pin_route[j].int_name[0]; |
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| 388 | break; |
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| 389 | } |
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| 390 | } |
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| 391 | if( int_name == -1 ) |
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| 392 | { |
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[513b6c4b] | 393 | printk("pci : Unable to resolve device %d:%d w/ swizzled int pin %i to an interrupt_line.\n", pbus, pslot, int_pin ); |
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[3a3e0b0e] | 394 | } |
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| 395 | else |
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| 396 | { |
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| 397 | PRINT_MSG(); |
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| 398 | pci_write_config_byte(pbus,pslot,0,PCI_INTERRUPT_LINE,(cvalue= int_name, cvalue)); |
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| 399 | } |
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| 400 | } |
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| 401 | else |
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| 402 | { |
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| 403 | test_intname( &bspmap[i],pbus,pslot,int_pin,int_name); |
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| 404 | } |
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| 405 | break; |
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| 406 | } |
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| 407 | } |
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| 408 | |
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| 409 | if( !ismatch ) |
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| 410 | { |
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[6128a4a] | 411 | /* |
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[3a3e0b0e] | 412 | ** no match, which means we're on a bus someplace. Work |
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| 413 | ** backwards from it to one of our defined busses, |
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[6128a4a] | 414 | ** swizzling thru each bridge on the way. |
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[3a3e0b0e] | 415 | */ |
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| 416 | |
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| 417 | /* keep pbus, pslot pointed to the device being |
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| 418 | configured while we track down the bridges using |
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| 419 | tbus,tslot. We keep searching the routing table because |
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| 420 | we may end up finding our bridge in it */ |
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| 421 | |
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| 422 | int tbus= pbus, tslot= pslot; |
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| 423 | |
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| 424 | for(;;) |
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| 425 | { |
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| 426 | |
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| 427 | for(i=0; bspmap[i].bus > -1; i++) |
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| 428 | { |
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| 429 | if( bspmap[i].bus == tbus && (bspmap[i].slot == tslot || bspmap[i].slot == -1) ) |
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| 430 | { |
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| 431 | ismatch = -1; |
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| 432 | /* found a record for this bus, so swizzle the |
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| 433 | * int_pin which we then use to find the |
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| 434 | * interrupt_name. |
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| 435 | */ |
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| 436 | |
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| 437 | if( int_name == 255 ) |
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| 438 | { |
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| 439 | /* |
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| 440 | ** FIXME. I can't believe this little hack |
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| 441 | ** is right. It does not yield an error in |
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| 442 | ** convienently simple situations. |
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| 443 | */ |
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| 444 | if( tbus ) int_pin = (*swizzler)(tslot,int_pin); |
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| 445 | |
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| 446 | /* |
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| 447 | ** int_pin points to the interrupt channel |
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| 448 | ** this card ends up delivering interrupts |
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| 449 | ** on. Find the int_name servicing it. |
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| 450 | */ |
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| 451 | for( int_name=-1, j=0; bspmap[i].pin_route[j].pin > -1; j++ ) |
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| 452 | { |
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| 453 | if( bspmap[i].pin_route[j].pin == int_pin ) |
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| 454 | { |
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| 455 | int_name = bspmap[i].pin_route[j].int_name[0]; |
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| 456 | break; |
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| 457 | } |
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| 458 | } |
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| 459 | if( int_name == -1 ) |
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| 460 | { |
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[513b6c4b] | 461 | printk("pci : Unable to resolve device %d:%d w/ swizzled int pin %i to an interrupt_line.\n", pbus, pslot, int_pin ); |
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[3a3e0b0e] | 462 | } |
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| 463 | else |
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| 464 | { |
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| 465 | PRINT_MSG(); |
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| 466 | pci_write_config_byte(pbus,pslot,0,PCI_INTERRUPT_LINE,(cvalue= int_name, cvalue)); |
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| 467 | } |
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| 468 | } |
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| 469 | else |
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| 470 | { |
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| 471 | test_intname(&bspmap[i],pbus,pslot,int_pin,int_name); |
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| 472 | } |
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| 473 | goto donesearch; |
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| 474 | } |
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| 475 | } |
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| 476 | |
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| 477 | if( !ismatch ) |
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| 478 | { |
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| 479 | struct pcibridge pb; |
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| 480 | |
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[6128a4a] | 481 | /* |
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[3a3e0b0e] | 482 | ** Haven't found our bus in the int map, so work |
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| 483 | ** upwards thru the bridges till we find it. |
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| 484 | */ |
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| 485 | |
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| 486 | if( FindPCIbridge( tbus, &pb )== 0 ) |
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| 487 | { |
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| 488 | int_pin = (*swizzler)(tslot,int_pin); |
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| 489 | |
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| 490 | /* our next bridge up is on pb.bus, pb.slot- now |
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| 491 | ** instead of pointing to the device we're |
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| 492 | ** trying to configure, we move from bridge to |
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| 493 | ** bridge. |
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| 494 | */ |
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| 495 | |
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| 496 | tbus = pb.bus; |
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| 497 | tslot = pb.slot; |
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| 498 | } |
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| 499 | else |
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| 500 | { |
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[513b6c4b] | 501 | printk("pci : No bridge from bus %i towards root found\n", tbus ); |
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[3a3e0b0e] | 502 | goto donesearch; |
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| 503 | } |
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[6128a4a] | 504 | |
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[3a3e0b0e] | 505 | } |
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| 506 | |
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| 507 | } |
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| 508 | } |
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| 509 | donesearch: |
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| 510 | |
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| 511 | if( !ismatch && int_pin != 0 && int_name == 255 ) |
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| 512 | { |
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| 513 | printk("pci : Unable to match device %d:%d with an int routing table entry\n", pbus, pslot ); |
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| 514 | } |
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| 515 | |
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| 516 | } |
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| 517 | } |
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| 518 | } |
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| 519 | } |
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| 520 | |
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[acc25ee] | 521 | /* |
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| 522 | * This routine determines the maximum bus number in the system |
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| 523 | */ |
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| 524 | void InitializePCI() |
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| 525 | { |
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[69ed59f] | 526 | extern void detect_host_bridge(); |
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[acc25ee] | 527 | unsigned char ucSlotNumber, ucFnNumber, ucNumFuncs; |
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| 528 | unsigned char ucHeader; |
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| 529 | unsigned char ucMaxSubordinate; |
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| 530 | unsigned int ulClass, ulDeviceID; |
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| 531 | |
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| 532 | detect_host_bridge(); |
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[3a3e0b0e] | 533 | |
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[acc25ee] | 534 | /* |
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| 535 | * Scan PCI bus 0 looking for PCI-PCI bridges |
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| 536 | */ |
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| 537 | for(ucSlotNumber=0;ucSlotNumber<PCI_MAX_DEVICES;ucSlotNumber++) { |
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| 538 | (void)pci_read_config_dword(0, |
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| 539 | ucSlotNumber, |
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| 540 | 0, |
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| 541 | PCI_VENDOR_ID, |
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| 542 | &ulDeviceID); |
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| 543 | if(ulDeviceID==PCI_INVALID_VENDORDEVICEID) { |
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| 544 | /* |
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| 545 | * This slot is empty |
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| 546 | */ |
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| 547 | continue; |
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| 548 | } |
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| 549 | (void)pci_read_config_byte(0, |
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| 550 | ucSlotNumber, |
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| 551 | 0, |
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| 552 | PCI_HEADER_TYPE, |
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| 553 | &ucHeader); |
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| 554 | if(ucHeader&PCI_MULTI_FUNCTION) { |
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| 555 | ucNumFuncs=PCI_MAX_FUNCTIONS; |
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| 556 | } |
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| 557 | else { |
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| 558 | ucNumFuncs=1; |
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| 559 | } |
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| 560 | for(ucFnNumber=0;ucFnNumber<ucNumFuncs;ucFnNumber++) { |
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| 561 | (void)pci_read_config_dword(0, |
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| 562 | ucSlotNumber, |
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| 563 | ucFnNumber, |
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| 564 | PCI_VENDOR_ID, |
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| 565 | &ulDeviceID); |
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| 566 | if(ulDeviceID==PCI_INVALID_VENDORDEVICEID) { |
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| 567 | /* |
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| 568 | * This slot/function is empty |
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| 569 | */ |
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| 570 | continue; |
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| 571 | } |
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| 572 | |
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| 573 | /* |
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| 574 | * This slot/function has a device fitted. |
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| 575 | */ |
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| 576 | (void)pci_read_config_dword(0, |
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| 577 | ucSlotNumber, |
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| 578 | ucFnNumber, |
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| 579 | PCI_CLASS_REVISION, |
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| 580 | &ulClass); |
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| 581 | ulClass >>= 16; |
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| 582 | if (ulClass == PCI_CLASS_BRIDGE_PCI) { |
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| 583 | /* |
---|
| 584 | * We have found a PCI-PCI bridge |
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| 585 | */ |
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| 586 | (void)pci_read_config_byte(0, |
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| 587 | ucSlotNumber, |
---|
| 588 | ucFnNumber, |
---|
| 589 | PCI_SUBORDINATE_BUS, |
---|
| 590 | &ucMaxSubordinate); |
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| 591 | if(ucMaxSubordinate>ucMaxPCIBus) { |
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| 592 | ucMaxPCIBus=ucMaxSubordinate; |
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| 593 | } |
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| 594 | } |
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| 595 | } |
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| 596 | } |
---|
| 597 | } |
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| 598 | |
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| 599 | /* |
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| 600 | * Return the number of PCI busses in the system |
---|
| 601 | */ |
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| 602 | unsigned char BusCountPCI() |
---|
| 603 | { |
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| 604 | return(ucMaxPCIBus+1); |
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| 605 | } |
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