[acc25ee] | 1 | /* |
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| 2 | * pci.c : this file contains basic PCI Io functions. |
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| 3 | * |
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| 4 | * CopyRight (C) 1999 valette@crf.canon.fr |
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| 5 | * |
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| 6 | * This code is heavilly inspired by the public specification of STREAM V2 |
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| 7 | * that can be found at : |
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| 8 | * |
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| 9 | * <http://www.chorus.com/Documentation/index.html> by following |
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| 10 | * the STREAM API Specification Document link. |
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| 11 | * |
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| 12 | * The license and distribution terms for this file may be |
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| 13 | * found in found in the file LICENSE in this distribution or at |
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[e831de8] | 14 | * http://www.rtems.com/license/LICENSE. |
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[acc25ee] | 15 | * |
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| 16 | * $Id$ |
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[69ed59f] | 17 | * |
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| 18 | * Till Straumann, <strauman@slac.stanford.edu>, 1/2002 |
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| 19 | * - separated bridge detection code out of this file |
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[acc25ee] | 20 | */ |
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| 21 | |
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| 22 | #include <libcpu/io.h> |
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| 23 | #include <bsp/pci.h> |
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| 24 | |
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[69ed59f] | 25 | /* allow for overriding these definitions */ |
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| 26 | #ifndef PCI_CONFIG_ADDR |
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[acc25ee] | 27 | #define PCI_CONFIG_ADDR 0xcf8 |
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[69ed59f] | 28 | #endif |
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| 29 | #ifndef PCI_CONFIG_DATA |
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[acc25ee] | 30 | #define PCI_CONFIG_DATA 0xcfc |
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[69ed59f] | 31 | #endif |
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| 32 | |
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[acc25ee] | 33 | #define PCI_INVALID_VENDORDEVICEID 0xffffffff |
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| 34 | #define PCI_MULTI_FUNCTION 0x80 |
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| 35 | |
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[69ed59f] | 36 | /* define a shortcut */ |
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| 37 | #define pci BSP_pci_configuration |
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[acc25ee] | 38 | |
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[844c273] | 39 | |
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| 40 | |
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[acc25ee] | 41 | /* |
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| 42 | * Bit encode for PCI_CONFIG_HEADER_TYPE register |
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| 43 | */ |
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| 44 | unsigned char ucMaxPCIBus; |
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| 45 | |
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| 46 | static int |
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| 47 | indirect_pci_read_config_byte(unsigned char bus, unsigned char slot, |
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[6128a4a] | 48 | unsigned char function, |
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[acc25ee] | 49 | unsigned char offset, unsigned char *val) { |
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[6128a4a] | 50 | out_be32((unsigned int*) pci.pci_config_addr, |
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[acc25ee] | 51 | 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24)); |
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| 52 | *val = in_8(pci.pci_config_data + (offset&3)); |
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| 53 | return PCIBIOS_SUCCESSFUL; |
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| 54 | } |
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| 55 | |
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| 56 | static int |
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| 57 | indirect_pci_read_config_word(unsigned char bus, unsigned char slot, |
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[6128a4a] | 58 | unsigned char function, |
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[acc25ee] | 59 | unsigned char offset, unsigned short *val) { |
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[6128a4a] | 60 | *val = 0xffff; |
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[acc25ee] | 61 | if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER; |
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[6128a4a] | 62 | out_be32((unsigned int*) pci.pci_config_addr, |
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[acc25ee] | 63 | 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24)); |
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| 64 | *val = in_le16((volatile unsigned short *)(pci.pci_config_data + (offset&3))); |
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| 65 | return PCIBIOS_SUCCESSFUL; |
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| 66 | } |
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| 67 | |
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| 68 | static int |
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| 69 | indirect_pci_read_config_dword(unsigned char bus, unsigned char slot, |
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[6128a4a] | 70 | unsigned char function, |
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[acc25ee] | 71 | unsigned char offset, unsigned int *val) { |
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[6128a4a] | 72 | *val = 0xffffffff; |
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[acc25ee] | 73 | if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER; |
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[6128a4a] | 74 | out_be32((unsigned int*) pci.pci_config_addr, |
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[acc25ee] | 75 | 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|(offset<<24)); |
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| 76 | *val = in_le32((volatile unsigned int *)pci.pci_config_data); |
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| 77 | return PCIBIOS_SUCCESSFUL; |
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| 78 | } |
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| 79 | |
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| 80 | static int |
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| 81 | indirect_pci_write_config_byte(unsigned char bus, unsigned char slot, |
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[6128a4a] | 82 | unsigned char function, |
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[acc25ee] | 83 | unsigned char offset, unsigned char val) { |
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[6128a4a] | 84 | out_be32((unsigned int*) pci.pci_config_addr, |
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[acc25ee] | 85 | 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24)); |
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| 86 | out_8(pci.pci_config_data + (offset&3), val); |
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| 87 | return PCIBIOS_SUCCESSFUL; |
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| 88 | } |
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| 89 | |
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| 90 | static int |
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| 91 | indirect_pci_write_config_word(unsigned char bus, unsigned char slot, |
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[6128a4a] | 92 | unsigned char function, |
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[acc25ee] | 93 | unsigned char offset, unsigned short val) { |
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| 94 | if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER; |
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[6128a4a] | 95 | out_be32((unsigned int*) pci.pci_config_addr, |
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[acc25ee] | 96 | 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24)); |
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| 97 | out_le16((volatile unsigned short *)(pci.pci_config_data + (offset&3)), val); |
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| 98 | return PCIBIOS_SUCCESSFUL; |
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| 99 | } |
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| 100 | |
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| 101 | static int |
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| 102 | indirect_pci_write_config_dword(unsigned char bus, unsigned char slot, |
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[6128a4a] | 103 | unsigned char function, |
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[acc25ee] | 104 | unsigned char offset, unsigned int val) { |
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| 105 | if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER; |
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[6128a4a] | 106 | out_be32((unsigned int*) pci.pci_config_addr, |
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[acc25ee] | 107 | 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|(offset<<24)); |
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| 108 | out_le32((volatile unsigned int *)pci.pci_config_data, val); |
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| 109 | return PCIBIOS_SUCCESSFUL; |
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| 110 | } |
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| 111 | |
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[69ed59f] | 112 | const pci_config_access_functions pci_indirect_functions = { |
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[acc25ee] | 113 | indirect_pci_read_config_byte, |
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| 114 | indirect_pci_read_config_word, |
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| 115 | indirect_pci_read_config_dword, |
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| 116 | indirect_pci_write_config_byte, |
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| 117 | indirect_pci_write_config_word, |
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| 118 | indirect_pci_write_config_dword |
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| 119 | }; |
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| 120 | |
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[69ed59f] | 121 | pci_config BSP_pci_configuration = {(volatile unsigned char*)PCI_CONFIG_ADDR, |
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[acc25ee] | 122 | (volatile unsigned char*)PCI_CONFIG_DATA, |
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[69ed59f] | 123 | &pci_indirect_functions}; |
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[acc25ee] | 124 | |
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| 125 | static int |
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| 126 | direct_pci_read_config_byte(unsigned char bus, unsigned char slot, |
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[6128a4a] | 127 | unsigned char function, |
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[acc25ee] | 128 | unsigned char offset, unsigned char *val) { |
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| 129 | if (bus != 0 || (1<<slot & 0xff8007fe)) { |
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| 130 | *val=0xff; |
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| 131 | return PCIBIOS_DEVICE_NOT_FOUND; |
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| 132 | } |
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[6128a4a] | 133 | *val=in_8(pci.pci_config_data + ((1<<slot)&~1) |
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[acc25ee] | 134 | + (function<<8) + offset); |
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| 135 | return PCIBIOS_SUCCESSFUL; |
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| 136 | } |
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| 137 | |
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| 138 | static int |
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| 139 | direct_pci_read_config_word(unsigned char bus, unsigned char slot, |
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[6128a4a] | 140 | unsigned char function, |
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[acc25ee] | 141 | unsigned char offset, unsigned short *val) { |
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[6128a4a] | 142 | *val = 0xffff; |
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[acc25ee] | 143 | if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER; |
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| 144 | if (bus != 0 || (1<<slot & 0xff8007fe)) { |
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| 145 | return PCIBIOS_DEVICE_NOT_FOUND; |
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| 146 | } |
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| 147 | *val=in_le16((volatile unsigned short *) |
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| 148 | (pci.pci_config_data + ((1<<slot)&~1) |
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| 149 | + (function<<8) + offset)); |
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| 150 | return PCIBIOS_SUCCESSFUL; |
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| 151 | } |
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| 152 | |
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| 153 | static int |
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| 154 | direct_pci_read_config_dword(unsigned char bus, unsigned char slot, |
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[6128a4a] | 155 | unsigned char function, |
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[acc25ee] | 156 | unsigned char offset, unsigned int *val) { |
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[6128a4a] | 157 | *val = 0xffffffff; |
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[acc25ee] | 158 | if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER; |
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| 159 | if (bus != 0 || (1<<slot & 0xff8007fe)) { |
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| 160 | return PCIBIOS_DEVICE_NOT_FOUND; |
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| 161 | } |
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| 162 | *val=in_le32((volatile unsigned int *) |
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| 163 | (pci.pci_config_data + ((1<<slot)&~1) |
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| 164 | + (function<<8) + offset)); |
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| 165 | return PCIBIOS_SUCCESSFUL; |
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| 166 | } |
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| 167 | |
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| 168 | static int |
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| 169 | direct_pci_write_config_byte(unsigned char bus, unsigned char slot, |
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[6128a4a] | 170 | unsigned char function, |
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[acc25ee] | 171 | unsigned char offset, unsigned char val) { |
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| 172 | if (bus != 0 || (1<<slot & 0xff8007fe)) { |
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| 173 | return PCIBIOS_DEVICE_NOT_FOUND; |
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| 174 | } |
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[6128a4a] | 175 | out_8(pci.pci_config_data + ((1<<slot)&~1) |
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| 176 | + (function<<8) + offset, |
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[acc25ee] | 177 | val); |
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| 178 | return PCIBIOS_SUCCESSFUL; |
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| 179 | } |
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| 180 | |
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| 181 | static int |
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| 182 | direct_pci_write_config_word(unsigned char bus, unsigned char slot, |
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[6128a4a] | 183 | unsigned char function, |
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[acc25ee] | 184 | unsigned char offset, unsigned short val) { |
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| 185 | if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER; |
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| 186 | if (bus != 0 || (1<<slot & 0xff8007fe)) { |
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| 187 | return PCIBIOS_DEVICE_NOT_FOUND; |
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| 188 | } |
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| 189 | out_le16((volatile unsigned short *) |
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| 190 | (pci.pci_config_data + ((1<<slot)&~1) |
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| 191 | + (function<<8) + offset), |
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| 192 | val); |
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| 193 | return PCIBIOS_SUCCESSFUL; |
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| 194 | } |
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| 195 | |
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| 196 | static int |
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| 197 | direct_pci_write_config_dword(unsigned char bus, unsigned char slot, |
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[6128a4a] | 198 | unsigned char function, |
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[acc25ee] | 199 | unsigned char offset, unsigned int val) { |
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| 200 | if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER; |
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| 201 | if (bus != 0 || (1<<slot & 0xff8007fe)) { |
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| 202 | return PCIBIOS_DEVICE_NOT_FOUND; |
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| 203 | } |
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| 204 | out_le32((volatile unsigned int *) |
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| 205 | (pci.pci_config_data + ((1<<slot)&~1) |
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| 206 | + (function<<8) + offset), |
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| 207 | val); |
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| 208 | return PCIBIOS_SUCCESSFUL; |
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| 209 | } |
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| 210 | |
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[69ed59f] | 211 | const pci_config_access_functions pci_direct_functions = { |
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[acc25ee] | 212 | direct_pci_read_config_byte, |
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| 213 | direct_pci_read_config_word, |
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| 214 | direct_pci_read_config_dword, |
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| 215 | direct_pci_write_config_byte, |
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| 216 | direct_pci_write_config_word, |
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| 217 | direct_pci_write_config_dword |
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| 218 | }; |
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| 219 | |
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[3a3e0b0e] | 220 | #define PRINT_MSG() \ |
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| 221 | printk("pci : Device %d:%02x routed to interrupt_line %d\n", pbus, pslot, int_name ) |
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| 222 | |
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[6128a4a] | 223 | /* |
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[3a3e0b0e] | 224 | ** Validate a test interrupt name and print a warning if its not one of |
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| 225 | ** the names defined in the routing record. |
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| 226 | */ |
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[da3b8d3] | 227 | static int test_intname( |
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| 228 | const struct _int_map *row, int pbus, int pslot, int int_pin, int int_name ) |
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[3a3e0b0e] | 229 | { |
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| 230 | int j,k; |
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| 231 | int _nopin= -1, _noname= -1; |
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| 232 | |
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| 233 | for(j=0; row->pin_route[j].pin > -1; j++) |
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| 234 | { |
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[6128a4a] | 235 | if( row->pin_route[j].pin == int_pin ) |
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[3a3e0b0e] | 236 | { |
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| 237 | _nopin = 0; |
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[6128a4a] | 238 | |
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[3a3e0b0e] | 239 | for(k=0; k<4 && row->pin_route[j].int_name[k] > -1; k++ ) |
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| 240 | { |
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[6128a4a] | 241 | if( row->pin_route[j].int_name[k] == int_name ){ _noname=0; break; } |
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[3a3e0b0e] | 242 | } |
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| 243 | break; |
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| 244 | } |
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| 245 | } |
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| 246 | |
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[6128a4a] | 247 | if( _nopin ) |
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[3a3e0b0e] | 248 | { |
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| 249 | printk("pci : Device %d:%02x supplied a bogus interrupt_pin %d\n", pbus, pslot, int_pin ); |
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| 250 | return -1; |
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| 251 | } |
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| 252 | else |
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| 253 | { |
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| 254 | if( _noname ) |
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| 255 | printk("pci : Device %d:%02x supplied a suspicious interrupt_line %d, using it anyway\n", pbus, pslot, int_name ); |
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| 256 | } |
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| 257 | return 0; |
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| 258 | } |
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| 259 | |
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| 260 | struct pcibridge |
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| 261 | { |
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| 262 | int bus,slot; |
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| 263 | }; |
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| 264 | |
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| 265 | static int FindPCIbridge( int mybus, struct pcibridge *pb ) |
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| 266 | { |
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| 267 | int pbus, pslot; |
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[bde7f268] | 268 | uint8_t bussec, buspri; |
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| 269 | uint16_t devid, vendorid, dclass; |
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[3a3e0b0e] | 270 | |
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| 271 | for(pbus=0; pbus< BusCountPCI(); pbus++) |
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| 272 | { |
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| 273 | for(pslot=0; pslot< PCI_MAX_DEVICES; pslot++) |
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[6128a4a] | 274 | { |
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[3a3e0b0e] | 275 | pci_read_config_word(pbus, pslot, 0, PCI_DEVICE_ID, &devid); |
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| 276 | if( devid == 0xffff ) continue; |
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| 277 | |
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| 278 | pci_read_config_word(pbus, pslot, 0, PCI_DEVICE_ID, &vendorid); |
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| 279 | if( vendorid == 0xffff ) continue; |
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| 280 | |
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| 281 | pci_read_config_word(pbus, pslot, 0, PCI_CLASS_DEVICE, &dclass); |
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| 282 | |
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[6128a4a] | 283 | if( dclass == PCI_CLASS_BRIDGE_PCI ) |
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[3a3e0b0e] | 284 | { |
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| 285 | pci_read_config_byte(pbus, pslot, 0, PCI_PRIMARY_BUS, &buspri); |
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| 286 | pci_read_config_byte(pbus, pslot, 0, PCI_SECONDARY_BUS, &bussec); |
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| 287 | |
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| 288 | #if 0 |
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| 289 | printk("pci : Found bridge at %d:%d, mybus %d, pribus %d, secbus %d ", pbus, pslot, mybus, buspri, bussec ); |
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| 290 | #endif |
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| 291 | if( bussec == mybus ) |
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| 292 | { |
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| 293 | #if 0 |
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| 294 | printk("match\n"); |
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| 295 | #endif |
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| 296 | /* found our nearest bridge going towards the root */ |
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| 297 | pb->bus = pbus; |
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| 298 | pb->slot = pslot; |
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| 299 | |
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| 300 | return 0; |
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| 301 | } |
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| 302 | #if 0 |
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| 303 | printk("no match\n"); |
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| 304 | #endif |
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| 305 | } |
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| 306 | |
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| 307 | } |
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| 308 | } |
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| 309 | return -1; |
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| 310 | } |
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| 311 | |
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[da3b8d3] | 312 | void FixupPCI( const struct _int_map *bspmap, int (*swizzler)(int,int) ) |
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[3a3e0b0e] | 313 | { |
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| 314 | unsigned char cvalue; |
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[bde7f268] | 315 | uint16_t devid; |
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[3a3e0b0e] | 316 | int ismatch, i, j, pbus, pslot, int_pin, int_name; |
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| 317 | |
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| 318 | /* |
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| 319 | ** If the device has a non-zero INTERRUPT_PIN, assign a bsp-specific |
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| 320 | ** INTERRUPT_NAME if one isn't already in place. Then, drivers can |
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| 321 | ** trivially use INTERRUPT_NAME to hook up with devices. |
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| 322 | */ |
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| 323 | |
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| 324 | for(pbus=0; pbus< BusCountPCI(); pbus++) |
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| 325 | { |
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| 326 | for(pslot=0; pslot< PCI_MAX_DEVICES; pslot++) |
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[6128a4a] | 327 | { |
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[3a3e0b0e] | 328 | pci_read_config_word(pbus, pslot, 0, PCI_DEVICE_ID, &devid); |
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| 329 | if( devid == 0xffff ) continue; |
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| 330 | |
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| 331 | /* got a device */ |
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| 332 | |
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| 333 | pci_read_config_byte( pbus, pslot, 0, PCI_INTERRUPT_PIN, &cvalue); |
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| 334 | int_pin = cvalue; |
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| 335 | |
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| 336 | pci_read_config_byte( pbus, pslot, 0, PCI_INTERRUPT_LINE, &cvalue); |
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| 337 | int_name = cvalue; |
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| 338 | |
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| 339 | /* printk("pci : device %d:%02x devid %04x, intpin %d, intline %d\n", pbus, pslot, devid, int_pin, int_name ); */ |
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| 340 | |
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[513b6c4b] | 341 | #if 0 |
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| 342 | { |
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| 343 | unsigned short cmd,stat; |
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| 344 | unsigned char lat, seclat, csize; |
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| 345 | |
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| 346 | pci_read_config_word(pbus,pslot,0,PCI_COMMAND, &cmd ); |
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| 347 | pci_read_config_word(pbus,pslot,0,PCI_STATUS, &stat ); |
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| 348 | pci_read_config_byte(pbus,pslot,0,PCI_LATENCY_TIMER, &lat ); |
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| 349 | pci_read_config_byte(pbus,pslot,0,PCI_SEC_LATENCY_TIMER, &seclat ); |
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| 350 | pci_read_config_byte(pbus,pslot,0,PCI_CACHE_LINE_SIZE, &csize ); |
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| 351 | |
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| 352 | |
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| 353 | printk("pci : device %d:%02x cmd %04X, stat %04X, latency %d, sec_latency %d, clsize %d\n", pbus, pslot, |
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| 354 | cmd, |
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| 355 | stat, |
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| 356 | lat, |
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| 357 | seclat, |
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| 358 | csize); |
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| 359 | } |
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| 360 | #endif |
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| 361 | |
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[3a3e0b0e] | 362 | if( int_pin > 0 ) |
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| 363 | { |
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| 364 | ismatch = 0; |
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| 365 | |
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| 366 | /* |
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| 367 | ** first run thru the bspmap table and see if we have an explicit configuration |
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| 368 | */ |
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| 369 | for(i=0; bspmap[i].bus > -1; i++) |
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| 370 | { |
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| 371 | if( bspmap[i].bus == pbus && bspmap[i].slot == pslot ) |
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| 372 | { |
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| 373 | ismatch = -1; |
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| 374 | /* we have a record in the table that gives specific |
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| 375 | * pins and interrupts for devices in this slot */ |
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| 376 | if( int_name == 255 ) |
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| 377 | { |
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| 378 | /* find the vector associated with whatever pin the device gives us */ |
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| 379 | for( int_name=-1, j=0; bspmap[i].pin_route[j].pin > -1; j++ ) |
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| 380 | { |
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| 381 | if( bspmap[i].pin_route[j].pin == int_pin ) |
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| 382 | { |
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| 383 | int_name = bspmap[i].pin_route[j].int_name[0]; |
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| 384 | break; |
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| 385 | } |
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| 386 | } |
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| 387 | if( int_name == -1 ) |
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| 388 | { |
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[513b6c4b] | 389 | printk("pci : Unable to resolve device %d:%d w/ swizzled int pin %i to an interrupt_line.\n", pbus, pslot, int_pin ); |
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[3a3e0b0e] | 390 | } |
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| 391 | else |
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| 392 | { |
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| 393 | PRINT_MSG(); |
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| 394 | pci_write_config_byte(pbus,pslot,0,PCI_INTERRUPT_LINE,(cvalue= int_name, cvalue)); |
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| 395 | } |
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| 396 | } |
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| 397 | else |
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| 398 | { |
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| 399 | test_intname( &bspmap[i],pbus,pslot,int_pin,int_name); |
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| 400 | } |
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| 401 | break; |
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| 402 | } |
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| 403 | } |
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| 404 | |
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| 405 | if( !ismatch ) |
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| 406 | { |
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[6128a4a] | 407 | /* |
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[3a3e0b0e] | 408 | ** no match, which means we're on a bus someplace. Work |
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| 409 | ** backwards from it to one of our defined busses, |
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[6128a4a] | 410 | ** swizzling thru each bridge on the way. |
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[3a3e0b0e] | 411 | */ |
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| 412 | |
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| 413 | /* keep pbus, pslot pointed to the device being |
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| 414 | configured while we track down the bridges using |
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| 415 | tbus,tslot. We keep searching the routing table because |
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| 416 | we may end up finding our bridge in it */ |
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| 417 | |
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| 418 | int tbus= pbus, tslot= pslot; |
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| 419 | |
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| 420 | for(;;) |
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| 421 | { |
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| 422 | |
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| 423 | for(i=0; bspmap[i].bus > -1; i++) |
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| 424 | { |
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| 425 | if( bspmap[i].bus == tbus && (bspmap[i].slot == tslot || bspmap[i].slot == -1) ) |
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| 426 | { |
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| 427 | ismatch = -1; |
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| 428 | /* found a record for this bus, so swizzle the |
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| 429 | * int_pin which we then use to find the |
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| 430 | * interrupt_name. |
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| 431 | */ |
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| 432 | |
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| 433 | if( int_name == 255 ) |
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| 434 | { |
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| 435 | /* |
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| 436 | ** FIXME. I can't believe this little hack |
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| 437 | ** is right. It does not yield an error in |
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| 438 | ** convienently simple situations. |
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| 439 | */ |
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| 440 | if( tbus ) int_pin = (*swizzler)(tslot,int_pin); |
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| 441 | |
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| 442 | /* |
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| 443 | ** int_pin points to the interrupt channel |
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| 444 | ** this card ends up delivering interrupts |
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| 445 | ** on. Find the int_name servicing it. |
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| 446 | */ |
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| 447 | for( int_name=-1, j=0; bspmap[i].pin_route[j].pin > -1; j++ ) |
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| 448 | { |
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| 449 | if( bspmap[i].pin_route[j].pin == int_pin ) |
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| 450 | { |
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| 451 | int_name = bspmap[i].pin_route[j].int_name[0]; |
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| 452 | break; |
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| 453 | } |
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| 454 | } |
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| 455 | if( int_name == -1 ) |
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| 456 | { |
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[513b6c4b] | 457 | printk("pci : Unable to resolve device %d:%d w/ swizzled int pin %i to an interrupt_line.\n", pbus, pslot, int_pin ); |
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[3a3e0b0e] | 458 | } |
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| 459 | else |
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| 460 | { |
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| 461 | PRINT_MSG(); |
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| 462 | pci_write_config_byte(pbus,pslot,0,PCI_INTERRUPT_LINE,(cvalue= int_name, cvalue)); |
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| 463 | } |
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| 464 | } |
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| 465 | else |
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| 466 | { |
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| 467 | test_intname(&bspmap[i],pbus,pslot,int_pin,int_name); |
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| 468 | } |
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| 469 | goto donesearch; |
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| 470 | } |
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| 471 | } |
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| 472 | |
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| 473 | if( !ismatch ) |
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| 474 | { |
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| 475 | struct pcibridge pb; |
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| 476 | |
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[6128a4a] | 477 | /* |
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[3a3e0b0e] | 478 | ** Haven't found our bus in the int map, so work |
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| 479 | ** upwards thru the bridges till we find it. |
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| 480 | */ |
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| 481 | |
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| 482 | if( FindPCIbridge( tbus, &pb )== 0 ) |
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| 483 | { |
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| 484 | int_pin = (*swizzler)(tslot,int_pin); |
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| 485 | |
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| 486 | /* our next bridge up is on pb.bus, pb.slot- now |
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| 487 | ** instead of pointing to the device we're |
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| 488 | ** trying to configure, we move from bridge to |
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| 489 | ** bridge. |
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| 490 | */ |
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| 491 | |
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| 492 | tbus = pb.bus; |
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| 493 | tslot = pb.slot; |
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| 494 | } |
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| 495 | else |
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| 496 | { |
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[513b6c4b] | 497 | printk("pci : No bridge from bus %i towards root found\n", tbus ); |
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[3a3e0b0e] | 498 | goto donesearch; |
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| 499 | } |
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[6128a4a] | 500 | |
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[3a3e0b0e] | 501 | } |
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| 502 | |
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| 503 | } |
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| 504 | } |
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| 505 | donesearch: |
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| 506 | |
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| 507 | if( !ismatch && int_pin != 0 && int_name == 255 ) |
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| 508 | { |
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| 509 | printk("pci : Unable to match device %d:%d with an int routing table entry\n", pbus, pslot ); |
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| 510 | } |
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| 511 | |
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| 512 | } |
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| 513 | } |
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| 514 | } |
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| 515 | } |
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| 516 | |
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[acc25ee] | 517 | /* |
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| 518 | * This routine determines the maximum bus number in the system |
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| 519 | */ |
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| 520 | void InitializePCI() |
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| 521 | { |
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[69ed59f] | 522 | extern void detect_host_bridge(); |
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[acc25ee] | 523 | unsigned char ucSlotNumber, ucFnNumber, ucNumFuncs; |
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| 524 | unsigned char ucHeader; |
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| 525 | unsigned char ucMaxSubordinate; |
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| 526 | unsigned int ulClass, ulDeviceID; |
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| 527 | |
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| 528 | detect_host_bridge(); |
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[3a3e0b0e] | 529 | |
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[acc25ee] | 530 | /* |
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| 531 | * Scan PCI bus 0 looking for PCI-PCI bridges |
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| 532 | */ |
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| 533 | for(ucSlotNumber=0;ucSlotNumber<PCI_MAX_DEVICES;ucSlotNumber++) { |
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| 534 | (void)pci_read_config_dword(0, |
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| 535 | ucSlotNumber, |
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| 536 | 0, |
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| 537 | PCI_VENDOR_ID, |
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| 538 | &ulDeviceID); |
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| 539 | if(ulDeviceID==PCI_INVALID_VENDORDEVICEID) { |
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| 540 | /* |
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| 541 | * This slot is empty |
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| 542 | */ |
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| 543 | continue; |
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| 544 | } |
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| 545 | (void)pci_read_config_byte(0, |
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| 546 | ucSlotNumber, |
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| 547 | 0, |
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| 548 | PCI_HEADER_TYPE, |
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| 549 | &ucHeader); |
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| 550 | if(ucHeader&PCI_MULTI_FUNCTION) { |
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| 551 | ucNumFuncs=PCI_MAX_FUNCTIONS; |
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| 552 | } |
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| 553 | else { |
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| 554 | ucNumFuncs=1; |
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| 555 | } |
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| 556 | for(ucFnNumber=0;ucFnNumber<ucNumFuncs;ucFnNumber++) { |
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| 557 | (void)pci_read_config_dword(0, |
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| 558 | ucSlotNumber, |
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| 559 | ucFnNumber, |
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| 560 | PCI_VENDOR_ID, |
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| 561 | &ulDeviceID); |
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| 562 | if(ulDeviceID==PCI_INVALID_VENDORDEVICEID) { |
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| 563 | /* |
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| 564 | * This slot/function is empty |
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| 565 | */ |
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| 566 | continue; |
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| 567 | } |
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| 568 | |
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| 569 | /* |
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| 570 | * This slot/function has a device fitted. |
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| 571 | */ |
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| 572 | (void)pci_read_config_dword(0, |
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| 573 | ucSlotNumber, |
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| 574 | ucFnNumber, |
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| 575 | PCI_CLASS_REVISION, |
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| 576 | &ulClass); |
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| 577 | ulClass >>= 16; |
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| 578 | if (ulClass == PCI_CLASS_BRIDGE_PCI) { |
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| 579 | /* |
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| 580 | * We have found a PCI-PCI bridge |
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| 581 | */ |
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| 582 | (void)pci_read_config_byte(0, |
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| 583 | ucSlotNumber, |
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| 584 | ucFnNumber, |
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| 585 | PCI_SUBORDINATE_BUS, |
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| 586 | &ucMaxSubordinate); |
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| 587 | if(ucMaxSubordinate>ucMaxPCIBus) { |
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| 588 | ucMaxPCIBus=ucMaxSubordinate; |
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| 589 | } |
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| 590 | } |
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| 591 | } |
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| 592 | } |
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| 593 | } |
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| 594 | |
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| 595 | /* |
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| 596 | * Return the number of PCI busses in the system |
---|
| 597 | */ |
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| 598 | unsigned char BusCountPCI() |
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| 599 | { |
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| 600 | return(ucMaxPCIBus+1); |
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| 601 | } |
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