source: rtems/c/src/lib/libbsp/powerpc/shared/pci/detect_raven_bridge.c @ cc2fcc1

4.104.114.84.9
Last change on this file since cc2fcc1 was cc2fcc1, checked in by Eric Norum <WENorum@…>, on Oct 20, 2005 at 6:38:26 PM

Numerous changes and cleanups to support MVME2100.

  • Property mode set to 100644
File size: 5.7 KB
Line 
1/*
2 *  $Id$
3 */
4
5#include <libcpu/io.h>
6#include <libcpu/spr.h>
7
8#include <bsp.h>
9#include <bsp/pci.h>
10#include <bsp/consoleIo.h>
11#include <bsp/residual.h>
12#include <bsp/openpic.h>
13
14#include <rtems/bspIo.h>
15#include <libcpu/cpuIdent.h>
16
17#define RAVEN_MPIC_IOSPACE_ENABLE  0x0001
18#define RAVEN_MPIC_MEMSPACE_ENABLE 0x0002
19#define RAVEN_MASTER_ENABLE        0x0004
20#define RAVEN_PARITY_CHECK_ENABLE  0x0040
21#define RAVEN_SYSTEM_ERROR_ENABLE  0x0100
22#define RAVEN_CLEAR_EVENTS_MASK    0xf9000000
23
24#define RAVEN_MPIC_MEREN    ((volatile unsigned *)0xfeff0020)
25#define RAVEN_MPIC_MERST    ((volatile unsigned *)0xfeff0024)
26/* enable machine check on all conditions */
27#define MEREN_VAL           0x2f00
28
29#define pci BSP_pci_configuration
30extern unsigned int EUMBBAR;
31
32extern const pci_config_access_functions pci_direct_functions;
33extern const pci_config_access_functions pci_indirect_functions;
34
35#define PCI_ERR_BITS        0xf900
36#define PCI_STATUS_OK(x)    (!((x)&PCI_ERR_BITS))
37
38/* For now, just clear errors in the PCI status reg.
39 *
40 * Returns: (for diagnostic purposes)
41 *          original settings (i.e. before applying the clearing
42 *          sequence) or the error bits or 0 if there were no errors.
43 *
44 */
45
46unsigned long
47_BSP_clear_hostbridge_errors(int enableMCP, int quiet)
48{
49unsigned long   rval;
50unsigned short  pcistat;
51int             count;
52
53    if (enableMCP)
54        return -1; /* exceptions not supported / MCP not wired */
55
56    /* read error status for info return */
57    pci_read_config_word(0,0,0,PCI_STATUS,&pcistat);
58    rval = pcistat;
59
60    count=10;
61    do {
62        /* clear error reporting registers */
63
64        /* clear PCI status register */
65        pci_write_config_word(0,0,0,PCI_STATUS, PCI_ERR_BITS);
66
67        /* read  new status */
68        pci_read_config_word(0,0,0,PCI_STATUS, &pcistat);
69
70    } while ( ! PCI_STATUS_OK(pcistat) && count-- );
71
72    if ( !PCI_STATUS_OK(rval) && !quiet) {
73        printk("Cleared PCI errors: pci_stat was 0x%04x\n", rval);
74    }
75    if ( !PCI_STATUS_OK(pcistat) ) {
76        printk("Unable to clear PCI errors: still 0x%04x after 10 attempts\n", pcistat);
77    }
78    return rval & PCI_ERR_BITS;
79}
80
81void detect_host_bridge()
82{
83#if (defined(mpc8240) || defined(mpc8245))
84  /*
85   * If the processor is an 8240 or an 8245 then the PIC is built
86   * in instead of being on the PCI bus. The MVME2100 is using Processor
87   * Address Map B (CHRP) although the Programmer's Reference Guide says
88   * it defaults to Map A.
89   */
90  /* We have an EPIC Interrupt Controller  */
91  OpenPIC = (volatile struct OpenPIC *) (EUMBBAR + BSP_OPEN_PIC_BASE_OFFSET);
92  pci.pci_functions = &pci_indirect_functions;
93  pci.pci_config_addr = (volatile unsigned char *) 0xfec00000;
94  pci.pci_config_data = (volatile unsigned char *) 0xfee00000;
95
96#else
97  PPC_DEVICE *hostbridge;
98  unsigned int id0;
99  unsigned int tmp;
100
101  /*
102   * This code assumes that the host bridge is located at
103   * bus 0, dev 0, func 0 AND that the old pre PCI 2.1
104   * standart devices detection mecahnism that was used on PC
105   * (still used in BSD source code) works.
106   */
107  hostbridge=residual_find_device(&residualCopy, PROCESSORDEVICE, NULL,
108                                  BridgeController,
109                                  PCIBridge, -1, 0);
110  if (hostbridge) {
111    if (hostbridge->DeviceId.Interface==PCIBridgeIndirect) {
112      pci.pci_functions=&pci_indirect_functions;
113      /* Should be extracted from residual data,
114       * indeed MPC106 in CHRP mode is different,
115       * but we should not use residual data in
116       * this case anyway.
117       */
118      pci.pci_config_addr = ((volatile unsigned char *)
119                              (ptr_mem_map->io_base+0xcf8));
120      pci.pci_config_data = ptr_mem_map->io_base+0xcfc;
121    } else if(hostbridge->DeviceId.Interface==PCIBridgeDirect) {
122      pci.pci_functions=&pci_direct_functions;
123      pci.pci_config_data=(unsigned char *) 0x80800000;
124    } else {
125    }
126  } else {
127    /* Let us try by experimentation at our own risk! */
128    pci.pci_functions = &pci_direct_functions;
129    /* On all direct bridges I know the host bridge itself
130     * appears as device 0 function 0.
131                 */
132    pci_read_config_dword(0, 0, 0, PCI_VENDOR_ID, &id0);
133    if (id0==~0U) {
134      pci.pci_functions = &pci_indirect_functions;
135      pci.pci_config_addr = ((volatile unsigned char*)
136                              (ptr_mem_map->io_base+0xcf8));
137      pci.pci_config_data = ((volatile unsigned char*)ptr_mem_map->io_base+0xcfc);
138    }
139    /* Here we should check that the host bridge is actually
140     * present, but if it not, we are in such a desperate
141     * situation, that we probably can't even tell it.
142     */
143  }
144  pci_read_config_dword(0, 0, 0, 0, &id0);
145  if(id0 == PCI_VENDOR_ID_MOTOROLA +
146     (PCI_DEVICE_ID_MOTOROLA_RAVEN<<16)) {
147    /*
148     * We have a Raven bridge. We will get information about its settings
149     */
150    pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0);
151#ifdef SHOW_RAVEN_SETTING
152    printk("RAVEN PCI command register = %x\n",id0);
153#endif
154    id0 |= RAVEN_CLEAR_EVENTS_MASK;
155    pci_write_config_dword(0, 0, 0, PCI_COMMAND, id0);
156    pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0);
157#ifdef SHOW_RAVEN_SETTING
158    printk("After error clearing RAVEN PCI command register = %x\n",id0);
159#endif
160
161    if (id0 & RAVEN_MPIC_IOSPACE_ENABLE) {
162      pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_0, &tmp);
163#ifdef SHOW_RAVEN_SETTING
164      printk("Raven MPIC is accessed via IO Space Access at address : %x\n",(tmp & ~0x1));
165#endif
166    }
167    if (id0 & RAVEN_MPIC_MEMSPACE_ENABLE) {
168      pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_1, &tmp);
169#ifdef SHOW_RAVEN_SETTING
170      printk("Raven MPIC is accessed via memory Space Access at address : %x\n", tmp);
171#endif
172      OpenPIC=(volatile struct OpenPIC *) (tmp + PREP_ISA_MEM_BASE);
173      printk("OpenPIC found at %x.\n", OpenPIC);
174    }
175  }
176#endif
177  if (OpenPIC == (volatile struct OpenPIC *)0) {
178    BSP_panic("OpenPic Not found\n");
179  }
180
181}
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