source: rtems/c/src/lib/libbsp/powerpc/shared/pci/detect_raven_bridge.c @ 98afe31

4.104.114.84.9
Last change on this file since 98afe31 was 98afe31, checked in by Till Straumann <strauman@…>, on Nov 4, 2005 at 3:34:08 AM

2005-11-03 Till Straumann <strauman@…>

  • shared/motorola/motorola.c, shared/pci/detect_raven_bridge.c, shared/pci/pci.c, shared/pci/pci.h, shared/pci/pcifinddevice.c: Several PCI enhancements and fixes: all BSP flavors now use the generic clear_hostbridge_errors() routine (this means that only polling memory probing is possible [see detect_raven_bridge.c for details]). Interrupt fixup routine now supports multi-function devices. Interrupt fixup routine now honours a flag/option so that wrong firmware values can be overridden. Fixed irq routing table for mvme2100 [PMC]. Added irq routing table for mvme2300. Added a BSP_pciScan() routine that executes a user callback on each non-empty slot/fun. Added BSP_pciConfigDump() to display basic config headers.
  • Property mode set to 100644
File size: 7.2 KB
Line 
1/*
2 *  $Id$
3 */
4
5#include <libcpu/io.h>
6#include <libcpu/spr.h>
7
8#include <bsp.h>
9#include <bsp/pci.h>
10#include <bsp/consoleIo.h>
11#include <bsp/residual.h>
12#include <bsp/openpic.h>
13
14#include <rtems/bspIo.h>
15#include <libcpu/cpuIdent.h>
16
17#define RAVEN_MPIC_IOSPACE_ENABLE  0x0001
18#define RAVEN_MPIC_MEMSPACE_ENABLE 0x0002
19#define RAVEN_MASTER_ENABLE        0x0004
20#define RAVEN_PARITY_CHECK_ENABLE  0x0040
21#define RAVEN_SYSTEM_ERROR_ENABLE  0x0100
22#define RAVEN_CLEAR_EVENTS_MASK    0xf9000000
23
24#define RAVEN_MPIC_MEREN    ((volatile unsigned *)0xfeff0020)
25#define RAVEN_MPIC_MERST    ((volatile unsigned *)0xfeff0024)
26#define MEREN_VAL           0x2f00
27
28#define pci BSP_pci_configuration
29
30extern const pci_config_access_functions pci_direct_functions;
31extern const pci_config_access_functions pci_indirect_functions;
32
33
34#define PCI_ERR_BITS        0xf900
35#define PCI_STATUS_OK(x)    (!((x)&PCI_ERR_BITS))
36
37/* For now, just clear errors in the PCI status reg.
38 *
39 * Returns: (for diagnostic purposes)
40 *          original settings (i.e. before applying the clearing
41 *          sequence) or the error bits or 0 if there were no errors.
42 *
43 */
44
45unsigned long
46_BSP_clear_hostbridge_errors(int enableMCP, int quiet)
47{
48unsigned long   rval;
49unsigned short  pcistat;
50int             count;
51
52    if (enableMCP)
53        return -1; /* exceptions not supported / MCP not wired */
54
55    /* read error status for info return */
56    pci_read_config_word(0,0,0,PCI_STATUS,&pcistat);
57    rval = pcistat;
58
59    count=10;
60    do {
61        /* clear error reporting registers */
62
63        /* clear PCI status register */
64        pci_write_config_word(0,0,0,PCI_STATUS, PCI_ERR_BITS);
65
66        /* read  new status */
67        pci_read_config_word(0,0,0,PCI_STATUS, &pcistat);
68
69    } while ( ! PCI_STATUS_OK(pcistat) && count-- );
70
71    if ( !PCI_STATUS_OK(rval) && !quiet) {
72        printk("Cleared PCI errors: pci_stat was 0x%04x\n", rval);
73    }
74    if ( !PCI_STATUS_OK(pcistat) ) {
75        printk("Unable to clear PCI errors: still 0x%04x after 10 attempts\n", pcistat);
76    }
77    return rval & PCI_ERR_BITS;
78}
79
80#if (defined(mpc8240) || defined(mpc8245))
81/* FIXME - this should really be in a separate file - the 2100 doesn't
82 *         have a raven chip so there is no point having 2100 code here
83 */
84
85extern unsigned int EUMBBAR;
86
87void detect_host_bridge()
88{
89  /*
90   * If the processor is an 8240 or an 8245 then the PIC is built
91   * in instead of being on the PCI bus. The MVME2100 is using Processor
92   * Address Map B (CHRP) although the Programmer's Reference Guide says
93   * it defaults to Map A.
94   */
95  /* We have an EPIC Interrupt Controller  */
96  OpenPIC = (volatile struct OpenPIC *) (EUMBBAR + BSP_OPEN_PIC_BASE_OFFSET);
97  pci.pci_functions = &pci_indirect_functions;
98  pci.pci_config_addr = (volatile unsigned char *) 0xfec00000;
99  pci.pci_config_data = (volatile unsigned char *) 0xfee00000;
100}
101
102#else
103
104#if 0
105/* Unfortunately, PCI config space access to empty slots generates
106 * a 'signalled master abort' condition --> we can't really use
107 * the machine check interrupt for memory probing unless
108 * we use probing for PCI scanning also (which would make
109 * all that code either BSP dependent or requiring yet another
110 * API, sigh...).
111 * So for the moment, we just don't use MCP on all mvme2xxx
112 * boards (using the generic, hostbridge-independent 'clear'
113 * implementation above).
114 */
115/*
116 * enableMCP: whether to enable MCP checkstop / machine check interrupts
117 *            on the hostbridge and in HID0.
118 *
119 *            NOTE: HID0 and MEREN are left alone if this flag is 0
120 *
121 * quiet    : be silent
122 *
123 * RETURNS  : raven MERST register contents (lowermost 16 bits), 0 if
124 *            there were no errors
125 */
126unsigned long
127_BSP_clear_hostbridge_errors(int enableMCP, int quiet)
128{
129unsigned merst;
130
131    merst = in_be32(RAVEN_MPIC_MERST);
132    /* write back value to clear status */
133    out_be32(RAVEN_MPIC_MERST, merst);
134
135    if (enableMCP) {
136      if (!quiet)
137        printk("Enabling MCP generation on hostbridge errors\n");
138      out_be32(RAVEN_MPIC_MEREN, MEREN_VAL);
139    } else {
140      out_be32(RAVEN_MPIC_MEREN, 0);
141      if ( !quiet && enableMCP ) {
142        printk("leaving MCP interrupt disabled\n");
143      }
144    }
145    return (merst & 0xffff);
146}
147#endif
148
149void detect_host_bridge()
150{
151  PPC_DEVICE *hostbridge;
152  unsigned int id0;
153  unsigned int tmp;
154
155  /*
156   * This code assumes that the host bridge is located at
157   * bus 0, dev 0, func 0 AND that the old pre PCI 2.1
158   * standart devices detection mecahnism that was used on PC
159   * (still used in BSD source code) works.
160   */
161  hostbridge=residual_find_device(&residualCopy, PROCESSORDEVICE, NULL,
162                                  BridgeController,
163                                  PCIBridge, -1, 0);
164  if (hostbridge) {
165    if (hostbridge->DeviceId.Interface==PCIBridgeIndirect) {
166      pci.pci_functions=&pci_indirect_functions;
167      /* Should be extracted from residual data,
168       * indeed MPC106 in CHRP mode is different,
169       * but we should not use residual data in
170       * this case anyway.
171       */
172      pci.pci_config_addr = ((volatile unsigned char *)
173                              (ptr_mem_map->io_base+0xcf8));
174      pci.pci_config_data = ptr_mem_map->io_base+0xcfc;
175    } else if(hostbridge->DeviceId.Interface==PCIBridgeDirect) {
176      pci.pci_functions=&pci_direct_functions;
177      pci.pci_config_data=(unsigned char *) 0x80800000;
178    } else {
179    }
180  } else {
181    /* Let us try by experimentation at our own risk! */
182    pci.pci_functions = &pci_direct_functions;
183    /* On all direct bridges I know the host bridge itself
184     * appears as device 0 function 0.
185                 */
186    pci_read_config_dword(0, 0, 0, PCI_VENDOR_ID, &id0);
187    if (id0==~0U) {
188      pci.pci_functions = &pci_indirect_functions;
189      pci.pci_config_addr = ((volatile unsigned char*)
190                              (ptr_mem_map->io_base+0xcf8));
191      pci.pci_config_data = ((volatile unsigned char*)ptr_mem_map->io_base+0xcfc);
192    }
193    /* Here we should check that the host bridge is actually
194     * present, but if it not, we are in such a desperate
195     * situation, that we probably can't even tell it.
196     */
197  }
198  pci_read_config_dword(0, 0, 0, 0, &id0);
199  if(id0 == PCI_VENDOR_ID_MOTOROLA +
200     (PCI_DEVICE_ID_MOTOROLA_RAVEN<<16)) {
201    /*
202     * We have a Raven bridge. We will get information about its settings
203     */
204    pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0);
205#ifdef SHOW_RAVEN_SETTING
206    printk("RAVEN PCI command register = %x\n",id0);
207#endif
208    id0 |= RAVEN_CLEAR_EVENTS_MASK;
209    pci_write_config_dword(0, 0, 0, PCI_COMMAND, id0);
210    pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0);
211#ifdef SHOW_RAVEN_SETTING
212    printk("After error clearing RAVEN PCI command register = %x\n",id0);
213#endif
214
215    if (id0 & RAVEN_MPIC_IOSPACE_ENABLE) {
216      pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_0, &tmp);
217#ifdef SHOW_RAVEN_SETTING
218      printk("Raven MPIC is accessed via IO Space Access at address : %x\n",(tmp & ~0x1));
219#endif
220    }
221    if (id0 & RAVEN_MPIC_MEMSPACE_ENABLE) {
222      pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_1, &tmp);
223#ifdef SHOW_RAVEN_SETTING
224      printk("Raven MPIC is accessed via memory Space Access at address : %x\n", tmp);
225#endif
226      OpenPIC=(volatile struct OpenPIC *) (tmp + PREP_ISA_MEM_BASE);
227      printk("OpenPIC found at %x.\n", OpenPIC);
228    }
229  }
230  if (OpenPIC == (volatile struct OpenPIC *)0) {
231    BSP_panic("OpenPic Not found\n");
232  }
233
234}
235
236#endif
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