1 | /* |
---|
2 | * $Id$ |
---|
3 | */ |
---|
4 | |
---|
5 | #include <libcpu/io.h> |
---|
6 | #include <libcpu/spr.h> |
---|
7 | |
---|
8 | #include <bsp.h> |
---|
9 | #include <bsp/pci.h> |
---|
10 | #include <bsp/consoleIo.h> |
---|
11 | #include <bsp/residual.h> |
---|
12 | #include <bsp/openpic.h> |
---|
13 | |
---|
14 | #include <rtems/bspIo.h> |
---|
15 | #include <libcpu/cpuIdent.h> |
---|
16 | |
---|
17 | #define SHOW_RAVEN_SETTINGS |
---|
18 | |
---|
19 | #define RAVEN_MPIC_IOSPACE_ENABLE 0x0001 |
---|
20 | #define RAVEN_MPIC_MEMSPACE_ENABLE 0x0002 |
---|
21 | #define RAVEN_MASTER_ENABLE 0x0004 |
---|
22 | #define RAVEN_PARITY_CHECK_ENABLE 0x0040 |
---|
23 | #define RAVEN_SYSTEM_ERROR_ENABLE 0x0100 |
---|
24 | #define RAVEN_CLEAR_EVENTS_MASK 0xf9000000 |
---|
25 | |
---|
26 | #define RAVEN_MPIC_MEREN ((volatile unsigned *)0xfeff0020) |
---|
27 | #define RAVEN_MPIC_MERST ((volatile unsigned *)0xfeff0024) |
---|
28 | #define MEREN_VAL 0x2f00 |
---|
29 | |
---|
30 | #define pci BSP_pci_configuration |
---|
31 | |
---|
32 | extern const pci_config_access_functions pci_direct_functions; |
---|
33 | extern const pci_config_access_functions pci_indirect_functions; |
---|
34 | |
---|
35 | #if (defined(mpc8240) || defined(mpc8245)) |
---|
36 | /* FIXME - this should really be in a separate file - the 2100 doesn't |
---|
37 | * have a raven chip so there is no point having 2100 code here |
---|
38 | */ |
---|
39 | |
---|
40 | extern unsigned int EUMBBAR; |
---|
41 | |
---|
42 | void detect_host_bridge() |
---|
43 | { |
---|
44 | /* |
---|
45 | * If the processor is an 8240 or an 8245 then the PIC is built |
---|
46 | * in instead of being on the PCI bus. The MVME2100 is using Processor |
---|
47 | * Address Map B (CHRP) although the Programmer's Reference Guide says |
---|
48 | * it defaults to Map A. |
---|
49 | */ |
---|
50 | /* We have an EPIC Interrupt Controller */ |
---|
51 | OpenPIC = (volatile struct OpenPIC *) (EUMBBAR + BSP_OPEN_PIC_BASE_OFFSET); |
---|
52 | pci.pci_functions = &pci_indirect_functions; |
---|
53 | pci.pci_config_addr = (volatile unsigned char *) 0xfec00000; |
---|
54 | pci.pci_config_data = (volatile unsigned char *) 0xfee00000; |
---|
55 | } |
---|
56 | |
---|
57 | #else |
---|
58 | |
---|
59 | #if 0 |
---|
60 | /* Unfortunately, PCI config space access to empty slots generates |
---|
61 | * a 'signalled master abort' condition --> we can't really use |
---|
62 | * the machine check interrupt for memory probing unless |
---|
63 | * we use probing for PCI scanning also (which would make |
---|
64 | * all that code either BSP dependent or requiring yet another |
---|
65 | * API, sigh...). |
---|
66 | * So for the moment, we just don't use MCP on all mvme2xxx |
---|
67 | * boards (using the generic, hostbridge-independent 'clear' |
---|
68 | * implementation [generic_clear_hberrs.c]). |
---|
69 | */ |
---|
70 | /* |
---|
71 | * enableMCP: whether to enable MCP checkstop / machine check interrupts |
---|
72 | * on the hostbridge and in HID0. |
---|
73 | * |
---|
74 | * NOTE: HID0 and MEREN are left alone if this flag is 0 |
---|
75 | * |
---|
76 | * quiet : be silent |
---|
77 | * |
---|
78 | * RETURNS : raven MERST register contents (lowermost 16 bits), 0 if |
---|
79 | * there were no errors |
---|
80 | */ |
---|
81 | unsigned long |
---|
82 | _BSP_clear_hostbridge_errors(int enableMCP, int quiet) |
---|
83 | { |
---|
84 | unsigned merst; |
---|
85 | |
---|
86 | merst = in_be32(RAVEN_MPIC_MERST); |
---|
87 | /* write back value to clear status */ |
---|
88 | out_be32(RAVEN_MPIC_MERST, merst); |
---|
89 | |
---|
90 | if (enableMCP) { |
---|
91 | if (!quiet) |
---|
92 | printk("Enabling MCP generation on hostbridge errors\n"); |
---|
93 | out_be32(RAVEN_MPIC_MEREN, MEREN_VAL); |
---|
94 | } else { |
---|
95 | out_be32(RAVEN_MPIC_MEREN, 0); |
---|
96 | if ( !quiet && enableMCP ) { |
---|
97 | printk("leaving MCP interrupt disabled\n"); |
---|
98 | } |
---|
99 | } |
---|
100 | return (merst & 0xffff); |
---|
101 | } |
---|
102 | #endif |
---|
103 | |
---|
104 | void detect_host_bridge() |
---|
105 | { |
---|
106 | PPC_DEVICE *hostbridge; |
---|
107 | uint32_t id0; |
---|
108 | uint32_t tmp; |
---|
109 | |
---|
110 | /* |
---|
111 | * This code assumes that the host bridge is located at |
---|
112 | * bus 0, dev 0, func 0 AND that the old pre PCI 2.1 |
---|
113 | * standart devices detection mecahnism that was used on PC |
---|
114 | * (still used in BSD source code) works. |
---|
115 | */ |
---|
116 | hostbridge=residual_find_device(&residualCopy, PROCESSORDEVICE, NULL, |
---|
117 | BridgeController, |
---|
118 | PCIBridge, -1, 0); |
---|
119 | if (hostbridge) { |
---|
120 | if (hostbridge->DeviceId.Interface==PCIBridgeIndirect) { |
---|
121 | pci.pci_functions=&pci_indirect_functions; |
---|
122 | /* Should be extracted from residual data, |
---|
123 | * indeed MPC106 in CHRP mode is different, |
---|
124 | * but we should not use residual data in |
---|
125 | * this case anyway. |
---|
126 | */ |
---|
127 | pci.pci_config_addr = ((volatile unsigned char *) |
---|
128 | (ptr_mem_map->io_base+0xcf8)); |
---|
129 | pci.pci_config_data = ptr_mem_map->io_base+0xcfc; |
---|
130 | } else if(hostbridge->DeviceId.Interface==PCIBridgeDirect) { |
---|
131 | pci.pci_functions=&pci_direct_functions; |
---|
132 | pci.pci_config_data=(unsigned char *) 0x80800000; |
---|
133 | } else { |
---|
134 | } |
---|
135 | } else { |
---|
136 | /* Let us try by experimentation at our own risk! */ |
---|
137 | pci.pci_functions = &pci_direct_functions; |
---|
138 | /* On all direct bridges I know the host bridge itself |
---|
139 | * appears as device 0 function 0. |
---|
140 | */ |
---|
141 | pci_read_config_dword(0, 0, 0, PCI_VENDOR_ID, &id0); |
---|
142 | if (id0==~0U) { |
---|
143 | pci.pci_functions = &pci_indirect_functions; |
---|
144 | pci.pci_config_addr = ((volatile unsigned char*) |
---|
145 | (ptr_mem_map->io_base+0xcf8)); |
---|
146 | pci.pci_config_data = ((volatile unsigned char*)ptr_mem_map->io_base+0xcfc); |
---|
147 | } |
---|
148 | /* Here we should check that the host bridge is actually |
---|
149 | * present, but if it not, we are in such a desperate |
---|
150 | * situation, that we probably can't even tell it. |
---|
151 | */ |
---|
152 | } |
---|
153 | pci_read_config_dword(0, 0, 0, 0, &id0); |
---|
154 | #ifdef SHOW_RAVEN_SETTINGS |
---|
155 | printk("idreg 0 = 0x%x\n",id0); |
---|
156 | #endif |
---|
157 | if((id0 == PCI_VENDOR_ID_MOTOROLA + |
---|
158 | (PCI_DEVICE_ID_MOTOROLA_RAVEN<<16)) || |
---|
159 | (id0 == PCI_VENDOR_ID_MOTOROLA + |
---|
160 | (PCI_DEVICE_ID_MOTOROLA_HAWK<<16))) { |
---|
161 | /* |
---|
162 | * We have a Raven bridge. We will get information about its settings |
---|
163 | */ |
---|
164 | pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0); |
---|
165 | #ifdef SHOW_RAVEN_SETTING |
---|
166 | printk("RAVEN PCI command register = %x\n",id0); |
---|
167 | #endif |
---|
168 | id0 |= RAVEN_CLEAR_EVENTS_MASK; |
---|
169 | pci_write_config_dword(0, 0, 0, PCI_COMMAND, id0); |
---|
170 | pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0); |
---|
171 | #ifdef SHOW_RAVEN_SETTING |
---|
172 | printk("After error clearing RAVEN PCI command register = %x\n",id0); |
---|
173 | #endif |
---|
174 | |
---|
175 | if (id0 & RAVEN_MPIC_IOSPACE_ENABLE) { |
---|
176 | pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_0, &tmp); |
---|
177 | #ifdef SHOW_RAVEN_SETTING |
---|
178 | printk("Raven MPIC is accessed via IO Space Access at address : %x\n",(tmp & ~0x1)); |
---|
179 | #endif |
---|
180 | } |
---|
181 | if (id0 & RAVEN_MPIC_MEMSPACE_ENABLE) { |
---|
182 | pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_1, &tmp); |
---|
183 | #ifdef SHOW_RAVEN_SETTING |
---|
184 | printk("Raven MPIC is accessed via memory Space Access at address : %x\n", tmp); |
---|
185 | #endif |
---|
186 | OpenPIC=(volatile struct OpenPIC *) (tmp + PREP_ISA_MEM_BASE); |
---|
187 | printk("OpenPIC found at %x.\n", OpenPIC); |
---|
188 | } |
---|
189 | } |
---|
190 | if (OpenPIC == (volatile struct OpenPIC *)0) { |
---|
191 | BSP_panic("OpenPic Not found\n"); |
---|
192 | } |
---|
193 | |
---|
194 | } |
---|
195 | |
---|
196 | #endif |
---|