source: rtems/c/src/lib/libbsp/powerpc/shared/pci/detect_raven_bridge.c @ 006ac513

Last change on this file since 006ac513 was 006ac513, checked in by Cillian O'Donnell <cpodonnell8@…>, on Apr 8, 2017 at 10:25:28 AM

libbsp/powerpc/./pci/detect_raven_bridge.c: Use inttypes.h to fix 1 warning.

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File size: 6.2 KB
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1#include <libcpu/io.h>
2#include <libcpu/spr.h>
3#include <inttypes.h>
4
5#include <bsp.h>
6#include <bsp/pci.h>
7#include <bsp/consoleIo.h>
8#include <bsp/residual.h>
9#include <bsp/openpic.h>
10#include <bsp/irq.h>
11
12#include <rtems/bspIo.h>
13#include <libcpu/cpuIdent.h>
14
15#define SHOW_RAVEN_SETTINGS
16
17#define RAVEN_MPIC_IOSPACE_ENABLE  0x0001
18#define RAVEN_MPIC_MEMSPACE_ENABLE 0x0002
19#define RAVEN_MASTER_ENABLE        0x0004
20#define RAVEN_PARITY_CHECK_ENABLE  0x0040
21#define RAVEN_SYSTEM_ERROR_ENABLE  0x0100
22#define RAVEN_CLEAR_EVENTS_MASK    0xf9000000
23
24#define RAVEN_MPIC_MEREN    ((volatile unsigned *)0xfeff0020)
25#define RAVEN_MPIC_MERST    ((volatile unsigned *)0xfeff0024)
26#define MEREN_VAL           0x2f00
27
28#define pci BSP_pci_configuration
29
30extern const pci_config_access_functions pci_direct_functions;
31extern const pci_config_access_functions pci_indirect_functions;
32
33#if defined(mvme2100)
34/* FIXME - this should really be in a separate file - the 2100 doesn't
35 *         have a raven chip so there is no point having 2100 code here
36 */
37
38extern unsigned int EUMBBAR;
39
40void detect_host_bridge(void)
41{
42  /*
43   * If the processor is an 8240 or an 8245 then the PIC is built
44   * in instead of being on the PCI bus. The MVME2100 is using Processor
45   * Address Map B (CHRP) although the Programmer's Reference Guide says
46   * it defaults to Map A.
47   */
48  /* We have an EPIC Interrupt Controller  */
49  OpenPIC = (volatile struct OpenPIC *) (EUMBBAR + BSP_OPEN_PIC_BASE_OFFSET);
50  pci.pci_functions = &pci_indirect_functions;
51  pci.pci_config_addr = (volatile unsigned char *) 0xfec00000;
52  pci.pci_config_data = (volatile unsigned char *) 0xfee00000;
53}
54
55#else
56
57#if 0
58/* Unfortunately, PCI config space access to empty slots generates
59 * a 'signalled master abort' condition --> we can't really use
60 * the machine check interrupt for memory probing unless
61 * we use probing for PCI scanning also (which would make
62 * all that code either BSP dependent or requiring yet another
63 * API, sigh...).
64 * So for the moment, we just don't use MCP on all mvme2xxx
65 * boards (using the generic, hostbridge-independent 'clear'
66 * implementation [generic_clear_hberrs.c]).
67 */
68/*
69 * enableMCP: whether to enable MCP checkstop / machine check interrupts
70 *            on the hostbridge and in HID0.
71 *
72 *            NOTE: HID0 and MEREN are left alone if this flag is 0
73 *
74 * quiet    : be silent
75 *
76 * RETURNS  : raven MERST register contents (lowermost 16 bits), 0 if
77 *            there were no errors
78 */
79unsigned long
80_BSP_clear_hostbridge_errors(int enableMCP, int quiet)
81{
82unsigned merst;
83
84    merst = in_be32(RAVEN_MPIC_MERST);
85    /* write back value to clear status */
86    out_be32(RAVEN_MPIC_MERST, merst);
87
88    if (enableMCP) {
89      if (!quiet)
90        printk("Enabling MCP generation on hostbridge errors\n");
91      out_be32(RAVEN_MPIC_MEREN, MEREN_VAL);
92    } else {
93      out_be32(RAVEN_MPIC_MEREN, 0);
94      if ( !quiet && enableMCP ) {
95        printk("leaving MCP interrupt disabled\n");
96      }
97    }
98    return (merst & 0xffff);
99}
100#endif
101
102void detect_host_bridge(void)
103{
104  PPC_DEVICE *hostbridge;
105  uint32_t id0;
106  uint32_t tmp;
107
108  /*
109   * This code assumes that the host bridge is located at
110   * bus 0, dev 0, func 0 AND that the old pre PCI 2.1
111   * standard devices detection mechanism that was used on PC
112   * (still used in BSD source code) works.
113   */
114  hostbridge=residual_find_device(&residualCopy, PROCESSORDEVICE, NULL,
115                                  BridgeController,
116                                  PCIBridge, -1, 0);
117  if (hostbridge) {
118    if (hostbridge->DeviceId.Interface==PCIBridgeIndirect) {
119      pci.pci_functions=&pci_indirect_functions;
120      /* Should be extracted from residual data,
121       * indeed MPC106 in CHRP mode is different,
122       * but we should not use residual data in
123       * this case anyway.
124       */
125      pci.pci_config_addr = ((volatile unsigned char *)
126                              (ptr_mem_map->io_base+0xcf8));
127      pci.pci_config_data = ptr_mem_map->io_base+0xcfc;
128    } else if(hostbridge->DeviceId.Interface==PCIBridgeDirect) {
129      pci.pci_functions=&pci_direct_functions;
130      pci.pci_config_data=(unsigned char *) 0x80800000;
131    } else {
132    }
133  } else {
134    /* Let us try by experimentation at our own risk! */
135    pci.pci_functions = &pci_direct_functions;
136    /* On all direct bridges I know the host bridge itself
137     * appears as device 0 function 0.
138                 */
139    pci_read_config_dword(0, 0, 0, PCI_VENDOR_ID, &id0);
140    if (id0==~0U) {
141      pci.pci_functions = &pci_indirect_functions;
142      pci.pci_config_addr = ((volatile unsigned char*)
143                              (ptr_mem_map->io_base+0xcf8));
144      pci.pci_config_data = ((volatile unsigned char*)ptr_mem_map->io_base+0xcfc);
145    }
146    /* Here we should check that the host bridge is actually
147     * present, but if it not, we are in such a desperate
148     * situation, that we probably can't even tell it.
149     */
150  }
151  pci_read_config_dword(0, 0, 0, 0, &id0);
152#ifdef SHOW_RAVEN_SETTINGS
153  printk("idreg 0 = 0x%" PRIu32 "\n",id0);
154#endif
155  if((id0 == PCI_VENDOR_ID_MOTOROLA +
156      (PCI_DEVICE_ID_MOTOROLA_RAVEN<<16)) ||
157     (id0 == PCI_VENDOR_ID_MOTOROLA +
158      (PCI_DEVICE_ID_MOTOROLA_HAWK<<16))) {
159    /*
160     * We have a Raven bridge. We will get information about its settings
161     */
162    pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0);
163#ifdef SHOW_RAVEN_SETTING
164    printk("RAVEN PCI command register = %x\n",id0);
165#endif
166    id0 |= RAVEN_CLEAR_EVENTS_MASK;
167    pci_write_config_dword(0, 0, 0, PCI_COMMAND, id0);
168    pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0);
169#ifdef SHOW_RAVEN_SETTING
170    printk("After error clearing RAVEN PCI command register = %x\n",id0);
171#endif
172
173    if (id0 & RAVEN_MPIC_IOSPACE_ENABLE) {
174      pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_0, &tmp);
175#ifdef SHOW_RAVEN_SETTING
176      printk("Raven MPIC is accessed via IO Space Access at address : %x\n",(tmp & ~0x1));
177#endif
178    }
179    if (id0 & RAVEN_MPIC_MEMSPACE_ENABLE) {
180      pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_1, &tmp);
181#ifdef SHOW_RAVEN_SETTING
182      printk("Raven MPIC is accessed via memory Space Access at address : %x\n", tmp);
183#endif
184      OpenPIC=(volatile struct OpenPIC *) (tmp + PREP_ISA_MEM_BASE);
185      printk("OpenPIC found at %x.\n", OpenPIC);
186    }
187  }
188
189#if BSP_PCI_IRQ_NUMBER > 0
190  if (OpenPIC == (volatile struct OpenPIC *)0) {
191    BSP_panic("OpenPic Not found\n");
192  }
193#endif
194
195}
196
197#endif
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