1 | #include <libcpu/io.h> |
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2 | #include <libcpu/spr.h> |
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3 | #include <inttypes.h> |
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4 | |
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5 | #include <bsp.h> |
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6 | #include <bsp/pci.h> |
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7 | #include <bsp/consoleIo.h> |
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8 | #include <bsp/residual.h> |
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9 | #include <bsp/openpic.h> |
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10 | #include <bsp/irq.h> |
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11 | |
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12 | #include <rtems/bspIo.h> |
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13 | #include <libcpu/cpuIdent.h> |
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14 | |
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15 | #define SHOW_RAVEN_SETTINGS |
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16 | |
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17 | #define RAVEN_MPIC_IOSPACE_ENABLE 0x0001 |
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18 | #define RAVEN_MPIC_MEMSPACE_ENABLE 0x0002 |
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19 | #define RAVEN_MASTER_ENABLE 0x0004 |
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20 | #define RAVEN_PARITY_CHECK_ENABLE 0x0040 |
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21 | #define RAVEN_SYSTEM_ERROR_ENABLE 0x0100 |
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22 | #define RAVEN_CLEAR_EVENTS_MASK 0xf9000000 |
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23 | |
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24 | #define RAVEN_MPIC_MEREN ((volatile unsigned *)0xfeff0020) |
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25 | #define RAVEN_MPIC_MERST ((volatile unsigned *)0xfeff0024) |
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26 | #define MEREN_VAL 0x2f00 |
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27 | |
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28 | #define pci BSP_pci_configuration |
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29 | |
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30 | extern const pci_config_access_functions pci_direct_functions; |
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31 | extern const pci_config_access_functions pci_indirect_functions; |
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32 | |
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33 | #if defined(mvme2100) |
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34 | /* FIXME - this should really be in a separate file - the 2100 doesn't |
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35 | * have a raven chip so there is no point having 2100 code here |
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36 | */ |
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37 | |
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38 | extern unsigned int EUMBBAR; |
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39 | |
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40 | void detect_host_bridge(void) |
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41 | { |
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42 | /* |
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43 | * If the processor is an 8240 or an 8245 then the PIC is built |
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44 | * in instead of being on the PCI bus. The MVME2100 is using Processor |
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45 | * Address Map B (CHRP) although the Programmer's Reference Guide says |
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46 | * it defaults to Map A. |
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47 | */ |
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48 | /* We have an EPIC Interrupt Controller */ |
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49 | OpenPIC = (volatile struct OpenPIC *) (EUMBBAR + BSP_OPEN_PIC_BASE_OFFSET); |
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50 | pci.pci_functions = &pci_indirect_functions; |
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51 | pci.pci_config_addr = (volatile unsigned char *) 0xfec00000; |
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52 | pci.pci_config_data = (volatile unsigned char *) 0xfee00000; |
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53 | } |
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54 | |
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55 | #else |
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56 | |
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57 | #if 0 |
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58 | /* Unfortunately, PCI config space access to empty slots generates |
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59 | * a 'signalled master abort' condition --> we can't really use |
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60 | * the machine check interrupt for memory probing unless |
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61 | * we use probing for PCI scanning also (which would make |
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62 | * all that code either BSP dependent or requiring yet another |
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63 | * API, sigh...). |
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64 | * So for the moment, we just don't use MCP on all mvme2xxx |
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65 | * boards (using the generic, hostbridge-independent 'clear' |
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66 | * implementation [generic_clear_hberrs.c]). |
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67 | */ |
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68 | /* |
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69 | * enableMCP: whether to enable MCP checkstop / machine check interrupts |
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70 | * on the hostbridge and in HID0. |
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71 | * |
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72 | * NOTE: HID0 and MEREN are left alone if this flag is 0 |
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73 | * |
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74 | * quiet : be silent |
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75 | * |
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76 | * RETURNS : raven MERST register contents (lowermost 16 bits), 0 if |
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77 | * there were no errors |
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78 | */ |
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79 | unsigned long |
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80 | _BSP_clear_hostbridge_errors(int enableMCP, int quiet) |
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81 | { |
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82 | unsigned merst; |
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83 | |
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84 | merst = in_be32(RAVEN_MPIC_MERST); |
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85 | /* write back value to clear status */ |
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86 | out_be32(RAVEN_MPIC_MERST, merst); |
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87 | |
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88 | if (enableMCP) { |
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89 | if (!quiet) |
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90 | printk("Enabling MCP generation on hostbridge errors\n"); |
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91 | out_be32(RAVEN_MPIC_MEREN, MEREN_VAL); |
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92 | } else { |
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93 | out_be32(RAVEN_MPIC_MEREN, 0); |
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94 | if ( !quiet && enableMCP ) { |
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95 | printk("leaving MCP interrupt disabled\n"); |
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96 | } |
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97 | } |
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98 | return (merst & 0xffff); |
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99 | } |
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100 | #endif |
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101 | |
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102 | void detect_host_bridge(void) |
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103 | { |
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104 | PPC_DEVICE *hostbridge; |
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105 | uint32_t id0; |
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106 | uint32_t tmp; |
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107 | |
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108 | /* |
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109 | * This code assumes that the host bridge is located at |
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110 | * bus 0, dev 0, func 0 AND that the old pre PCI 2.1 |
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111 | * standard devices detection mechanism that was used on PC |
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112 | * (still used in BSD source code) works. |
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113 | */ |
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114 | hostbridge=residual_find_device(&residualCopy, PROCESSORDEVICE, NULL, |
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115 | BridgeController, |
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116 | PCIBridge, -1, 0); |
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117 | if (hostbridge) { |
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118 | if (hostbridge->DeviceId.Interface==PCIBridgeIndirect) { |
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119 | pci.pci_functions=&pci_indirect_functions; |
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120 | /* Should be extracted from residual data, |
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121 | * indeed MPC106 in CHRP mode is different, |
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122 | * but we should not use residual data in |
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123 | * this case anyway. |
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124 | */ |
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125 | pci.pci_config_addr = ((volatile unsigned char *) |
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126 | (ptr_mem_map->io_base+0xcf8)); |
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127 | pci.pci_config_data = ptr_mem_map->io_base+0xcfc; |
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128 | } else if(hostbridge->DeviceId.Interface==PCIBridgeDirect) { |
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129 | pci.pci_functions=&pci_direct_functions; |
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130 | pci.pci_config_data=(unsigned char *) 0x80800000; |
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131 | } else { |
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132 | } |
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133 | } else { |
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134 | /* Let us try by experimentation at our own risk! */ |
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135 | pci.pci_functions = &pci_direct_functions; |
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136 | /* On all direct bridges I know the host bridge itself |
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137 | * appears as device 0 function 0. |
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138 | */ |
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139 | pci_read_config_dword(0, 0, 0, PCI_VENDOR_ID, &id0); |
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140 | if (id0==~0U) { |
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141 | pci.pci_functions = &pci_indirect_functions; |
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142 | pci.pci_config_addr = ((volatile unsigned char*) |
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143 | (ptr_mem_map->io_base+0xcf8)); |
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144 | pci.pci_config_data = ((volatile unsigned char*)ptr_mem_map->io_base+0xcfc); |
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145 | } |
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146 | /* Here we should check that the host bridge is actually |
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147 | * present, but if it not, we are in such a desperate |
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148 | * situation, that we probably can't even tell it. |
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149 | */ |
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150 | } |
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151 | pci_read_config_dword(0, 0, 0, 0, &id0); |
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152 | #ifdef SHOW_RAVEN_SETTINGS |
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153 | printk("idreg 0 = 0x%" PRIu32 "\n",id0); |
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154 | #endif |
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155 | if((id0 == PCI_VENDOR_ID_MOTOROLA + |
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156 | (PCI_DEVICE_ID_MOTOROLA_RAVEN<<16)) || |
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157 | (id0 == PCI_VENDOR_ID_MOTOROLA + |
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158 | (PCI_DEVICE_ID_MOTOROLA_HAWK<<16))) { |
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159 | /* |
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160 | * We have a Raven bridge. We will get information about its settings |
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161 | */ |
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162 | pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0); |
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163 | #ifdef SHOW_RAVEN_SETTING |
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164 | printk("RAVEN PCI command register = %x\n",id0); |
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165 | #endif |
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166 | id0 |= RAVEN_CLEAR_EVENTS_MASK; |
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167 | pci_write_config_dword(0, 0, 0, PCI_COMMAND, id0); |
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168 | pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0); |
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169 | #ifdef SHOW_RAVEN_SETTING |
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170 | printk("After error clearing RAVEN PCI command register = %x\n",id0); |
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171 | #endif |
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172 | |
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173 | if (id0 & RAVEN_MPIC_IOSPACE_ENABLE) { |
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174 | pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_0, &tmp); |
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175 | #ifdef SHOW_RAVEN_SETTING |
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176 | printk("Raven MPIC is accessed via IO Space Access at address : %x\n",(tmp & ~0x1)); |
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177 | #endif |
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178 | } |
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179 | if (id0 & RAVEN_MPIC_MEMSPACE_ENABLE) { |
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180 | pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_1, &tmp); |
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181 | #ifdef SHOW_RAVEN_SETTING |
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182 | printk("Raven MPIC is accessed via memory Space Access at address : %x\n", tmp); |
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183 | #endif |
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184 | OpenPIC=(volatile struct OpenPIC *) (tmp + PREP_ISA_MEM_BASE); |
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185 | printk("OpenPIC found at %x.\n", OpenPIC); |
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186 | } |
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187 | } |
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188 | |
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189 | #if BSP_PCI_IRQ_NUMBER > 0 |
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190 | if (OpenPIC == (volatile struct OpenPIC *)0) { |
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191 | BSP_panic("OpenPic Not found\n"); |
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192 | } |
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193 | #endif |
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194 | |
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195 | } |
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196 | |
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197 | #endif |
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