[9966204] | 1 | /* |
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| 2 | * $Id$ |
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| 3 | */ |
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| 4 | |
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| 5 | #include <libcpu/io.h> |
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[14ec2d4] | 6 | #include <libcpu/spr.h> |
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[9966204] | 7 | |
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| 8 | #include <bsp.h> |
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| 9 | #include <bsp/pci.h> |
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| 10 | #include <bsp/consoleIo.h> |
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| 11 | #include <bsp/residual.h> |
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| 12 | #include <bsp/openpic.h> |
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| 13 | |
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[7657233d] | 14 | #include <rtems/bspIo.h> |
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[e79a1947] | 15 | #include <libcpu/cpuIdent.h> |
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[7657233d] | 16 | |
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[e79a1947] | 17 | #define RAVEN_MPIC_IOSPACE_ENABLE 0x0001 |
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| 18 | #define RAVEN_MPIC_MEMSPACE_ENABLE 0x0002 |
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| 19 | #define RAVEN_MASTER_ENABLE 0x0004 |
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| 20 | #define RAVEN_PARITY_CHECK_ENABLE 0x0040 |
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| 21 | #define RAVEN_SYSTEM_ERROR_ENABLE 0x0100 |
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| 22 | #define RAVEN_CLEAR_EVENTS_MASK 0xf9000000 |
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[9966204] | 23 | |
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[e79a1947] | 24 | #define RAVEN_MPIC_MEREN ((volatile unsigned *)0xfeff0020) |
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| 25 | #define RAVEN_MPIC_MERST ((volatile unsigned *)0xfeff0024) |
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[674b9497] | 26 | /* enable machine check on all conditions */ |
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[e79a1947] | 27 | #define MEREN_VAL 0x2f00 |
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[14ec2d4] | 28 | |
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[9966204] | 29 | #define pci BSP_pci_configuration |
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[e79a1947] | 30 | extern unsigned int EUMBBAR; |
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[9966204] | 31 | |
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| 32 | extern const pci_config_access_functions pci_direct_functions; |
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| 33 | extern const pci_config_access_functions pci_indirect_functions; |
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| 34 | |
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[14ec2d4] | 35 | unsigned long |
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| 36 | _BSP_clear_hostbridge_errors(int enableMCP, int quiet) |
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| 37 | { |
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| 38 | unsigned merst; |
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| 39 | |
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[e79a1947] | 40 | merst = in_be32(RAVEN_MPIC_MERST); |
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| 41 | /* write back value to clear status */ |
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| 42 | out_be32(RAVEN_MPIC_MERST, merst); |
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[14ec2d4] | 43 | |
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[e79a1947] | 44 | if (enableMCP) { |
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| 45 | if (!quiet) |
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| 46 | printk("Enabling MCP generation on hostbridge errors\n"); |
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| 47 | out_be32(RAVEN_MPIC_MEREN, MEREN_VAL); |
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| 48 | } else { |
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| 49 | out_be32(RAVEN_MPIC_MEREN, 0); |
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| 50 | if ( !quiet && enableMCP ) { |
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| 51 | printk("leaving MCP interrupt disabled\n"); |
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| 52 | } |
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| 53 | } |
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| 54 | return (merst & 0xffff); |
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[14ec2d4] | 55 | } |
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| 56 | |
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[9966204] | 57 | void detect_host_bridge() |
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| 58 | { |
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[e79a1947] | 59 | #if (defined(mpc8240) || defined(mpc8245)) |
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| 60 | /* |
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| 61 | * If the processor is an 8240 or an 8245 then the PIC is built |
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| 62 | * in instead of being on the PCI bus. The MVME2100 is using Processor |
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| 63 | * Address Map B (CHRP) although the Programmer's Reference Guide says |
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| 64 | * it defaults to Map A. |
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| 65 | */ |
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| 66 | /* We have an EPIC Interrupt Controller */ |
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| 67 | OpenPIC = (volatile struct OpenPIC *) (EUMBBAR + BSP_OPEN_PIC_BASE_OFFSET); |
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| 68 | pci.pci_functions = &pci_indirect_functions; |
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| 69 | pci.pci_config_addr = (volatile unsigned char *) 0xfec00000; |
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| 70 | pci.pci_config_data = (volatile unsigned char *) 0xfee00000; |
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| 71 | |
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| 72 | #else |
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[9966204] | 73 | PPC_DEVICE *hostbridge; |
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| 74 | unsigned int id0; |
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| 75 | unsigned int tmp; |
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[6128a4a] | 76 | |
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[9966204] | 77 | /* |
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| 78 | * This code assumes that the host bridge is located at |
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| 79 | * bus 0, dev 0, func 0 AND that the old pre PCI 2.1 |
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| 80 | * standart devices detection mecahnism that was used on PC |
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| 81 | * (still used in BSD source code) works. |
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| 82 | */ |
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[6128a4a] | 83 | hostbridge=residual_find_device(&residualCopy, PROCESSORDEVICE, NULL, |
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[9966204] | 84 | BridgeController, |
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| 85 | PCIBridge, -1, 0); |
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| 86 | if (hostbridge) { |
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| 87 | if (hostbridge->DeviceId.Interface==PCIBridgeIndirect) { |
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| 88 | pci.pci_functions=&pci_indirect_functions; |
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[6128a4a] | 89 | /* Should be extracted from residual data, |
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[9966204] | 90 | * indeed MPC106 in CHRP mode is different, |
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| 91 | * but we should not use residual data in |
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[6128a4a] | 92 | * this case anyway. |
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[9966204] | 93 | */ |
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[6128a4a] | 94 | pci.pci_config_addr = ((volatile unsigned char *) |
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[9966204] | 95 | (ptr_mem_map->io_base+0xcf8)); |
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| 96 | pci.pci_config_data = ptr_mem_map->io_base+0xcfc; |
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| 97 | } else if(hostbridge->DeviceId.Interface==PCIBridgeDirect) { |
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| 98 | pci.pci_functions=&pci_direct_functions; |
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| 99 | pci.pci_config_data=(unsigned char *) 0x80800000; |
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| 100 | } else { |
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| 101 | } |
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| 102 | } else { |
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| 103 | /* Let us try by experimentation at our own risk! */ |
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| 104 | pci.pci_functions = &pci_direct_functions; |
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| 105 | /* On all direct bridges I know the host bridge itself |
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[6128a4a] | 106 | * appears as device 0 function 0. |
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[9966204] | 107 | */ |
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| 108 | pci_read_config_dword(0, 0, 0, PCI_VENDOR_ID, &id0); |
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| 109 | if (id0==~0U) { |
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| 110 | pci.pci_functions = &pci_indirect_functions; |
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| 111 | pci.pci_config_addr = ((volatile unsigned char*) |
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| 112 | (ptr_mem_map->io_base+0xcf8)); |
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| 113 | pci.pci_config_data = ((volatile unsigned char*)ptr_mem_map->io_base+0xcfc); |
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| 114 | } |
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| 115 | /* Here we should check that the host bridge is actually |
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| 116 | * present, but if it not, we are in such a desperate |
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| 117 | * situation, that we probably can't even tell it. |
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| 118 | */ |
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| 119 | } |
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| 120 | pci_read_config_dword(0, 0, 0, 0, &id0); |
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| 121 | if(id0 == PCI_VENDOR_ID_MOTOROLA + |
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| 122 | (PCI_DEVICE_ID_MOTOROLA_RAVEN<<16)) { |
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| 123 | /* |
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| 124 | * We have a Raven bridge. We will get information about its settings |
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| 125 | */ |
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| 126 | pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0); |
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[6128a4a] | 127 | #ifdef SHOW_RAVEN_SETTING |
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[9966204] | 128 | printk("RAVEN PCI command register = %x\n",id0); |
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[6128a4a] | 129 | #endif |
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[9966204] | 130 | id0 |= RAVEN_CLEAR_EVENTS_MASK; |
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| 131 | pci_write_config_dword(0, 0, 0, PCI_COMMAND, id0); |
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| 132 | pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0); |
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[6128a4a] | 133 | #ifdef SHOW_RAVEN_SETTING |
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[9966204] | 134 | printk("After error clearing RAVEN PCI command register = %x\n",id0); |
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[6128a4a] | 135 | #endif |
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| 136 | |
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[9966204] | 137 | if (id0 & RAVEN_MPIC_IOSPACE_ENABLE) { |
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| 138 | pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_0, &tmp); |
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[6128a4a] | 139 | #ifdef SHOW_RAVEN_SETTING |
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[9966204] | 140 | printk("Raven MPIC is accessed via IO Space Access at address : %x\n",(tmp & ~0x1)); |
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[6128a4a] | 141 | #endif |
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[9966204] | 142 | } |
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| 143 | if (id0 & RAVEN_MPIC_MEMSPACE_ENABLE) { |
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| 144 | pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_1, &tmp); |
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[6128a4a] | 145 | #ifdef SHOW_RAVEN_SETTING |
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[9966204] | 146 | printk("Raven MPIC is accessed via memory Space Access at address : %x\n", tmp); |
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[6128a4a] | 147 | #endif |
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[9966204] | 148 | OpenPIC=(volatile struct OpenPIC *) (tmp + PREP_ISA_MEM_BASE); |
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[e79a1947] | 149 | printk("OpenPIC found at %x.\n", OpenPIC); |
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[9966204] | 150 | } |
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| 151 | } |
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[e79a1947] | 152 | #endif |
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[9966204] | 153 | if (OpenPIC == (volatile struct OpenPIC *)0) { |
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| 154 | BSP_panic("OpenPic Not found\n"); |
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| 155 | } |
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| 156 | |
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| 157 | } |
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