[9966204] | 1 | /* |
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| 2 | * $Id$ |
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| 3 | */ |
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| 4 | |
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| 5 | #include <libcpu/io.h> |
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[14ec2d4] | 6 | #include <libcpu/spr.h> |
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[9966204] | 7 | |
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| 8 | #include <bsp.h> |
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| 9 | #include <bsp/pci.h> |
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| 10 | #include <bsp/consoleIo.h> |
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| 11 | #include <bsp/residual.h> |
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| 12 | #include <bsp/openpic.h> |
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| 13 | |
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[7657233d] | 14 | #include <rtems/bspIo.h> |
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[e79a1947] | 15 | #include <libcpu/cpuIdent.h> |
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[7657233d] | 16 | |
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[e79a1947] | 17 | #define RAVEN_MPIC_IOSPACE_ENABLE 0x0001 |
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| 18 | #define RAVEN_MPIC_MEMSPACE_ENABLE 0x0002 |
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| 19 | #define RAVEN_MASTER_ENABLE 0x0004 |
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| 20 | #define RAVEN_PARITY_CHECK_ENABLE 0x0040 |
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| 21 | #define RAVEN_SYSTEM_ERROR_ENABLE 0x0100 |
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| 22 | #define RAVEN_CLEAR_EVENTS_MASK 0xf9000000 |
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[9966204] | 23 | |
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[e79a1947] | 24 | #define RAVEN_MPIC_MEREN ((volatile unsigned *)0xfeff0020) |
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| 25 | #define RAVEN_MPIC_MERST ((volatile unsigned *)0xfeff0024) |
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| 26 | #define MEREN_VAL 0x2f00 |
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[14ec2d4] | 27 | |
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[9966204] | 28 | #define pci BSP_pci_configuration |
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| 29 | |
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| 30 | extern const pci_config_access_functions pci_direct_functions; |
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| 31 | extern const pci_config_access_functions pci_indirect_functions; |
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| 32 | |
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[98afe31] | 33 | |
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[cc2fcc1] | 34 | #define PCI_ERR_BITS 0xf900 |
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| 35 | #define PCI_STATUS_OK(x) (!((x)&PCI_ERR_BITS)) |
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| 36 | |
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| 37 | /* For now, just clear errors in the PCI status reg. |
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| 38 | * |
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| 39 | * Returns: (for diagnostic purposes) |
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| 40 | * original settings (i.e. before applying the clearing |
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| 41 | * sequence) or the error bits or 0 if there were no errors. |
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| 42 | * |
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| 43 | */ |
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| 44 | |
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[14ec2d4] | 45 | unsigned long |
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| 46 | _BSP_clear_hostbridge_errors(int enableMCP, int quiet) |
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| 47 | { |
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[cc2fcc1] | 48 | unsigned long rval; |
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| 49 | unsigned short pcistat; |
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| 50 | int count; |
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| 51 | |
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| 52 | if (enableMCP) |
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| 53 | return -1; /* exceptions not supported / MCP not wired */ |
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| 54 | |
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| 55 | /* read error status for info return */ |
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| 56 | pci_read_config_word(0,0,0,PCI_STATUS,&pcistat); |
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| 57 | rval = pcistat; |
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| 58 | |
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| 59 | count=10; |
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| 60 | do { |
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| 61 | /* clear error reporting registers */ |
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| 62 | |
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| 63 | /* clear PCI status register */ |
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| 64 | pci_write_config_word(0,0,0,PCI_STATUS, PCI_ERR_BITS); |
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| 65 | |
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| 66 | /* read new status */ |
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| 67 | pci_read_config_word(0,0,0,PCI_STATUS, &pcistat); |
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| 68 | |
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| 69 | } while ( ! PCI_STATUS_OK(pcistat) && count-- ); |
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| 70 | |
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| 71 | if ( !PCI_STATUS_OK(rval) && !quiet) { |
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| 72 | printk("Cleared PCI errors: pci_stat was 0x%04x\n", rval); |
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| 73 | } |
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| 74 | if ( !PCI_STATUS_OK(pcistat) ) { |
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| 75 | printk("Unable to clear PCI errors: still 0x%04x after 10 attempts\n", pcistat); |
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[e79a1947] | 76 | } |
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[cc2fcc1] | 77 | return rval & PCI_ERR_BITS; |
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[14ec2d4] | 78 | } |
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| 79 | |
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[98afe31] | 80 | #if (defined(mpc8240) || defined(mpc8245)) |
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| 81 | /* FIXME - this should really be in a separate file - the 2100 doesn't |
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| 82 | * have a raven chip so there is no point having 2100 code here |
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| 83 | */ |
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| 84 | |
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| 85 | extern unsigned int EUMBBAR; |
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| 86 | |
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[9966204] | 87 | void detect_host_bridge() |
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| 88 | { |
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[e79a1947] | 89 | /* |
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| 90 | * If the processor is an 8240 or an 8245 then the PIC is built |
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| 91 | * in instead of being on the PCI bus. The MVME2100 is using Processor |
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| 92 | * Address Map B (CHRP) although the Programmer's Reference Guide says |
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| 93 | * it defaults to Map A. |
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| 94 | */ |
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| 95 | /* We have an EPIC Interrupt Controller */ |
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| 96 | OpenPIC = (volatile struct OpenPIC *) (EUMBBAR + BSP_OPEN_PIC_BASE_OFFSET); |
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| 97 | pci.pci_functions = &pci_indirect_functions; |
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| 98 | pci.pci_config_addr = (volatile unsigned char *) 0xfec00000; |
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| 99 | pci.pci_config_data = (volatile unsigned char *) 0xfee00000; |
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[98afe31] | 100 | } |
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[e79a1947] | 101 | |
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| 102 | #else |
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[98afe31] | 103 | |
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| 104 | #if 0 |
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| 105 | /* Unfortunately, PCI config space access to empty slots generates |
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| 106 | * a 'signalled master abort' condition --> we can't really use |
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| 107 | * the machine check interrupt for memory probing unless |
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| 108 | * we use probing for PCI scanning also (which would make |
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| 109 | * all that code either BSP dependent or requiring yet another |
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| 110 | * API, sigh...). |
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| 111 | * So for the moment, we just don't use MCP on all mvme2xxx |
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| 112 | * boards (using the generic, hostbridge-independent 'clear' |
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| 113 | * implementation above). |
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| 114 | */ |
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| 115 | /* |
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| 116 | * enableMCP: whether to enable MCP checkstop / machine check interrupts |
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| 117 | * on the hostbridge and in HID0. |
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| 118 | * |
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| 119 | * NOTE: HID0 and MEREN are left alone if this flag is 0 |
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| 120 | * |
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| 121 | * quiet : be silent |
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| 122 | * |
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| 123 | * RETURNS : raven MERST register contents (lowermost 16 bits), 0 if |
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| 124 | * there were no errors |
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| 125 | */ |
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| 126 | unsigned long |
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| 127 | _BSP_clear_hostbridge_errors(int enableMCP, int quiet) |
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| 128 | { |
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| 129 | unsigned merst; |
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| 130 | |
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| 131 | merst = in_be32(RAVEN_MPIC_MERST); |
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| 132 | /* write back value to clear status */ |
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| 133 | out_be32(RAVEN_MPIC_MERST, merst); |
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| 134 | |
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| 135 | if (enableMCP) { |
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| 136 | if (!quiet) |
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| 137 | printk("Enabling MCP generation on hostbridge errors\n"); |
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| 138 | out_be32(RAVEN_MPIC_MEREN, MEREN_VAL); |
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| 139 | } else { |
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| 140 | out_be32(RAVEN_MPIC_MEREN, 0); |
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| 141 | if ( !quiet && enableMCP ) { |
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| 142 | printk("leaving MCP interrupt disabled\n"); |
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| 143 | } |
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| 144 | } |
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| 145 | return (merst & 0xffff); |
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| 146 | } |
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| 147 | #endif |
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| 148 | |
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| 149 | void detect_host_bridge() |
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| 150 | { |
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[9966204] | 151 | PPC_DEVICE *hostbridge; |
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| 152 | unsigned int id0; |
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| 153 | unsigned int tmp; |
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[6128a4a] | 154 | |
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[9966204] | 155 | /* |
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| 156 | * This code assumes that the host bridge is located at |
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| 157 | * bus 0, dev 0, func 0 AND that the old pre PCI 2.1 |
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| 158 | * standart devices detection mecahnism that was used on PC |
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| 159 | * (still used in BSD source code) works. |
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| 160 | */ |
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[6128a4a] | 161 | hostbridge=residual_find_device(&residualCopy, PROCESSORDEVICE, NULL, |
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[9966204] | 162 | BridgeController, |
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| 163 | PCIBridge, -1, 0); |
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| 164 | if (hostbridge) { |
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| 165 | if (hostbridge->DeviceId.Interface==PCIBridgeIndirect) { |
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| 166 | pci.pci_functions=&pci_indirect_functions; |
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[6128a4a] | 167 | /* Should be extracted from residual data, |
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[9966204] | 168 | * indeed MPC106 in CHRP mode is different, |
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| 169 | * but we should not use residual data in |
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[6128a4a] | 170 | * this case anyway. |
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[9966204] | 171 | */ |
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[6128a4a] | 172 | pci.pci_config_addr = ((volatile unsigned char *) |
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[9966204] | 173 | (ptr_mem_map->io_base+0xcf8)); |
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| 174 | pci.pci_config_data = ptr_mem_map->io_base+0xcfc; |
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| 175 | } else if(hostbridge->DeviceId.Interface==PCIBridgeDirect) { |
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| 176 | pci.pci_functions=&pci_direct_functions; |
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| 177 | pci.pci_config_data=(unsigned char *) 0x80800000; |
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| 178 | } else { |
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| 179 | } |
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| 180 | } else { |
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| 181 | /* Let us try by experimentation at our own risk! */ |
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| 182 | pci.pci_functions = &pci_direct_functions; |
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| 183 | /* On all direct bridges I know the host bridge itself |
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[6128a4a] | 184 | * appears as device 0 function 0. |
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[9966204] | 185 | */ |
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| 186 | pci_read_config_dword(0, 0, 0, PCI_VENDOR_ID, &id0); |
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| 187 | if (id0==~0U) { |
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| 188 | pci.pci_functions = &pci_indirect_functions; |
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| 189 | pci.pci_config_addr = ((volatile unsigned char*) |
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| 190 | (ptr_mem_map->io_base+0xcf8)); |
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| 191 | pci.pci_config_data = ((volatile unsigned char*)ptr_mem_map->io_base+0xcfc); |
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| 192 | } |
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| 193 | /* Here we should check that the host bridge is actually |
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| 194 | * present, but if it not, we are in such a desperate |
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| 195 | * situation, that we probably can't even tell it. |
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| 196 | */ |
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| 197 | } |
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| 198 | pci_read_config_dword(0, 0, 0, 0, &id0); |
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| 199 | if(id0 == PCI_VENDOR_ID_MOTOROLA + |
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| 200 | (PCI_DEVICE_ID_MOTOROLA_RAVEN<<16)) { |
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| 201 | /* |
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| 202 | * We have a Raven bridge. We will get information about its settings |
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| 203 | */ |
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| 204 | pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0); |
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[6128a4a] | 205 | #ifdef SHOW_RAVEN_SETTING |
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[9966204] | 206 | printk("RAVEN PCI command register = %x\n",id0); |
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[6128a4a] | 207 | #endif |
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[9966204] | 208 | id0 |= RAVEN_CLEAR_EVENTS_MASK; |
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| 209 | pci_write_config_dword(0, 0, 0, PCI_COMMAND, id0); |
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| 210 | pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0); |
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[6128a4a] | 211 | #ifdef SHOW_RAVEN_SETTING |
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[9966204] | 212 | printk("After error clearing RAVEN PCI command register = %x\n",id0); |
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[6128a4a] | 213 | #endif |
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| 214 | |
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[9966204] | 215 | if (id0 & RAVEN_MPIC_IOSPACE_ENABLE) { |
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| 216 | pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_0, &tmp); |
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[6128a4a] | 217 | #ifdef SHOW_RAVEN_SETTING |
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[9966204] | 218 | printk("Raven MPIC is accessed via IO Space Access at address : %x\n",(tmp & ~0x1)); |
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[6128a4a] | 219 | #endif |
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[9966204] | 220 | } |
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| 221 | if (id0 & RAVEN_MPIC_MEMSPACE_ENABLE) { |
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| 222 | pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_1, &tmp); |
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[6128a4a] | 223 | #ifdef SHOW_RAVEN_SETTING |
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[9966204] | 224 | printk("Raven MPIC is accessed via memory Space Access at address : %x\n", tmp); |
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[6128a4a] | 225 | #endif |
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[9966204] | 226 | OpenPIC=(volatile struct OpenPIC *) (tmp + PREP_ISA_MEM_BASE); |
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[e79a1947] | 227 | printk("OpenPIC found at %x.\n", OpenPIC); |
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[9966204] | 228 | } |
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| 229 | } |
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| 230 | if (OpenPIC == (volatile struct OpenPIC *)0) { |
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| 231 | BSP_panic("OpenPic Not found\n"); |
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| 232 | } |
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| 233 | |
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| 234 | } |
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[98afe31] | 235 | |
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| 236 | #endif |
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